CN210693555U - Oring circuit - Google Patents

Oring circuit Download PDF

Info

Publication number
CN210693555U
CN210693555U CN201922182384.4U CN201922182384U CN210693555U CN 210693555 U CN210693555 U CN 210693555U CN 201922182384 U CN201922182384 U CN 201922182384U CN 210693555 U CN210693555 U CN 210693555U
Authority
CN
China
Prior art keywords
voltage stabilizing
circuit
mos tube
voltage
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201922182384.4U
Other languages
Chinese (zh)
Inventor
张登峰
陈小军
黄章良
鲁星华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangzhou Lubangtong IoT Co Ltd
Original Assignee
Guangzhou Robustel Technologies Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangzhou Robustel Technologies Co ltd filed Critical Guangzhou Robustel Technologies Co ltd
Priority to CN201922182384.4U priority Critical patent/CN210693555U/en
Application granted granted Critical
Publication of CN210693555U publication Critical patent/CN210693555U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Dc-Dc Converters (AREA)
  • Stand-By Power Supply Arrangements (AREA)

Abstract

The utility model discloses an Oring circuit, which comprises an adapter and a battery, and also comprises a first voltage stabilizing circuit, a second voltage stabilizing circuit and a switching control circuit; the switching control circuit comprises a first MOS tube, a second MOS tube and a power output end which is respectively connected with a drain electrode of the first MOS tube and a source electrode of the second MOS tube, wherein a grid electrode of the first MOS tube is connected with the adapter through a first resistor, the grid electrode of the first MOS tube is further respectively connected with a source electrode of the first MOS tube through a first voltage stabilizing diode and a second resistor, the source electrode of the first MOS tube is connected with an output end of a first voltage stabilizing circuit and is further connected with a ground wire through a fourth resistor and a second voltage stabilizing diode in sequence, the source electrode of the first MOS tube is further connected with a grid electrode of the second MOS tube through a fifth resistor, and the drain electrode of the second MOS tube is connected with an output end of a second voltage stabilizing circuit. Through the utility model discloses can effectively guarantee power control and switch, save the cost.

Description

Oring circuit
Technical Field
The utility model relates to a power control field especially relates to an Oring circuit.
Background
The Oring circuit requires power architecture current with redundant design, power capability aggregation, or multiple power selection functions for many modern devices and systems. The Oring circuit is used for a multi-power supply system with higher power supply reliability or equipment needing seamless switching between commercial power and a backup battery; more than 2 multi-power supply systems are mostly applied to the field of special equipment. In the case of ordinary equipment, more demand is for seamless switching of the mains and the backup battery; the following two schemes are generally used for commercial power and backup battery power switching: diode mode and MOS-FET mode. The diode mode has good efficiency when applied to a high battery voltage system, but when applied to a low battery voltage power supply system, such as a single 3.7V lithium battery, the tube voltage drop will greatly affect the battery efficiency, so that the mode Oring cannot be used. The MOS-FET scheme can better guarantee battery efficiency in a low battery voltage power supply system, but because of the MOS-FET characteristics, a peripheral circuit must be used to control the G-pole to ensure correct power supply, and the implementation is usually performed using an Oring controller chip, which results in higher cost.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an Oring circuit can effectively guarantee the power control and switch, saves the cost.
In order to achieve the purpose, the Oring circuit comprises an adapter for accessing a mains supply, a battery for backup power utilization, a first voltage stabilizing circuit connected with the adapter and used for stabilizing the output voltage of the adapter, a second voltage stabilizing circuit connected with the battery and used for stabilizing the output voltage of the battery, and a switching control circuit respectively connected with the adapter, the first voltage stabilizing circuit and the second voltage stabilizing circuit and used for seamless power supply switching; the switching control circuit comprises a first MOS tube, a second MOS tube and a power output end which is respectively connected with a drain electrode of the first MOS tube and a source electrode of the second MOS tube, wherein a grid electrode of the first MOS tube is connected with the adapter through a first resistor, the grid electrode of the first MOS tube is further respectively connected with a source electrode of the first MOS tube through a first voltage stabilizing diode and a second resistor, the source electrode of the first MOS tube is connected with an output end of a first voltage stabilizing circuit and is further connected with a ground wire through a fourth resistor and a second voltage stabilizing diode in sequence, the source electrode of the first MOS tube is further connected with a grid electrode of the second MOS tube through a fifth resistor, and the drain electrode of the second MOS tube is connected with an output end of a second voltage stabilizing circuit.
Preferably, the first voltage stabilizing circuit comprises an adaptive connection input end and a voltage-reducing and voltage-stabilizing chip, the adaptive connection input end is connected with the adaptive connection input end, the adaptive connection input end is connected with the grid electrode of the first MOS transistor through a first resistor, the voltage-reducing and voltage-stabilizing chip is connected with the source electrode of the first MOS transistor sequentially through a first capacitor and a first inductor, the connection end of the first capacitor and the first inductor is connected with the conversion end of the voltage-reducing and voltage-stabilizing chip, the connection end of the first inductor and the source electrode of the first MOS transistor is connected with the ground wire sequentially through a third resistor and a seventh resistor and is further connected with the ground wire through a fourth capacitor, and the connection end of the third resistor and the seventh resistor is connected with the feedback end of the voltage-reducing and voltage-stabilizing chip.
Preferably, the second voltage stabilizing circuit is provided with a boost voltage stabilizing chip for boosting the output voltage of the battery, the input end of the boost voltage stabilizing chip is connected with the battery, and the output end of the boost voltage stabilizing chip is connected with the drain electrode of the second MOS transistor.
Preferably, the first MOS tube is an N-MOS tube, and the second MOS tube is a P-MOS tube.
Preferably, the first zener diode and the second zener diode are both 5V zener diodes.
Preferably, the first resistance is 4K Ω; the fourth resistance is 100 Ω.
Preferably, the power output terminal outputs a direct current 5V voltage.
Compared with the prior art, the utility model, its beneficial effect lies in:
the utility model discloses well switching control circuit carries out seamless switching automatic control to mains supply and reserve battery power supply through first MOS pipe and second MOS pipe, can effectively guarantee that power control switches, saves the cost. The utility model discloses it is general in dual power supply system, removed the higher cost of Oring controller among the current control circuit from. The adapter power supply uses high-order N-MOS control, corresponding to the traditional Oring circuit that uses P-MOS, the utility model discloses well adapter power supply uses high-order N-MOS control, corresponding to the traditional Oring circuit that uses P-MOS, the adapter power supply has higher transmission efficiency and ability.
Drawings
FIG. 1 is a block diagram of the present invention;
fig. 2 is a schematic diagram of the circuit structure of the present invention.
Detailed Description
The present invention will be further described with reference to the following examples, which are not intended to limit the scope of the invention, but are intended to be within the scope of the claims.
As shown in fig. 1 to 2, the utility model provides an Oring circuit, including the adapter 400 that is used for inserting the commercial power and the battery BAT that is used for the reserve power consumption, still include be connected with adapter 400 and be used for carrying out the first voltage stabilizing circuit 100 of steady voltage to the output voltage of adapter 400, be connected with battery BAT and be used for carrying out the second voltage stabilizing circuit 200 of steady voltage to the output voltage of battery BAT to and be connected with adapter 400, first voltage stabilizing circuit 100 and second voltage stabilizing circuit 200 respectively and carry out the switching control circuit 300 of seamless power supply switching; the switching control circuit 300 comprises a first MOS transistor Q1, a second MOS transistor Q2 and a power output end VDD connected with the drain of the first MOS transistor Q1 and the source of the second MOS transistor Q2 respectively, the gate of the first MOS transistor Q1 is connected with the adapter 400 through a first resistor R1, the gate of the first MOS transistor Q1 is further connected with the source of the first MOS transistor Q1 through a first zener diode V1 and a second resistor R2 respectively, the source of the first MOS transistor Q1 is connected with the output end of the first voltage stabilizing circuit 100 and is further connected with the ground through a fourth resistor R4 and a second zener diode V2 in sequence, the source of the first MOS transistor Q1 is further connected with the gate of the second MOS transistor Q2 through a fifth resistor R5, and the drain of the second MOS transistor Q2 is connected with the output end of the second voltage stabilizing circuit 200. The first MOS transistor Q1 is an N-MOS transistor, and the second MOS transistor Q2 is a P-MOS transistor.
The first voltage stabilizing circuit 100 comprises an adaptive connection input end VIN and a voltage-reducing and voltage-stabilizing chip U1, the adaptive connection input end VIN is used for being connected with the adapter 400, the adaptive connection input end VIN is connected with a gate of the first MOS tube Q1 through a first resistor R1, the voltage-reducing and voltage-stabilizing chip U1 is connected with a source of the first MOS tube Q1 through a first capacitor C1 and a first inductor L1 in sequence, a connection end of the first capacitor C1 and the first inductor L1 is connected with a conversion end of the voltage-reducing and voltage-stabilizing chip U1, a connection end of the first inductor L1 and a source of the first MOS tube Q1 is connected with a ground wire through a third resistor R3 and a seventh resistor R7 in sequence and is further connected with the ground wire through a fourth capacitor C4, and a third resistor R3 is connected with a connection end of the seventh resistor R7 and a feedback end of the voltage-reducing and voltage-stabilizing.
The second voltage stabilizing circuit 200 is provided with a voltage boosting and stabilizing chip U2 for boosting the output voltage of the battery BAT, the input end of the voltage boosting and stabilizing chip U2 is connected with the battery BAT, and the output end of the voltage boosting and stabilizing chip U2 is connected with the drain electrode of the second MOS transistor Q2.
The first zener diode V1 and the second zener diode V2 are both 5V zener diodes. The first resistor R1 is 4K omega; the fourth resistor R4 is 100 Ω. The power output terminal VDD outputs a dc 5V voltage.
In this embodiment, the adapter 400 outputs DC 12V-36V, and the battery BAT is a single lithium battery outputting DC 3V-4.2V. The buck regulator chip U1 and the boost regulator chip U2 regulate the output voltage of the adapter 400 and the output voltage of the battery BAT to dc 5V, respectively. The input voltage of the adapter 400 forms a loop through the first resistor R1, the first zener diode V1, the fourth resistor R4 and the second zener diode V2, and the first zener diode V1 clamps the gate and source voltage of the first MOS transistor Q1, i.e., the GS voltage, to 5V, so that the first MOS transistor Q1 is shorted out of the body diode and is fully turned on, and the voltage of the dc 5V output by the power output terminal VDD is ensured to be stable. In addition, the resistance value and the power of the first resistor R1 are selected to meet the requirement of the input voltage range of the adapter and the requirement of the stabilized current of the first voltage stabilizing diode V1. The fourth resistor R4 and the second zener diode V2 are used to protect the voltage of the first voltage regulating circuit 100 from the influence of the first resistor R1 and the first zener diode V1 circuit.
In this embodiment, when the adapter 400 supplies power, the first voltage regulator circuit 100 outputs a 5V dc power, and the GS voltage difference of the second MOS transistor Q2 is zero, so that the second MOS transistor Q2 is turned off, and the power supply circuit of the battery BAT is completely disconnected. When the power supply of the adapter 400 is interrupted, the GS voltage difference of the first MOS transistor Q1 is zero, which causes the first MOS transistor Q1 to be completely closed; the gate voltage of the second MOS transistor Q2 is pulled down to zero, and the source voltage is kept at about 4.3V due to the body diode action of the second MOS transistor Q2, i.e., the GS voltage difference of the second MOS transistor Q2 is about-4.3V at this time, so that the second MOS transistor Q2 is fully turned on, and then the source voltage of the second MOS transistor Q2 is raised to about 5V due to the complete turn-on of the second MOS transistor Q2, thereby ensuring that the dc output from the power output terminal VDD is uninterrupted at 5V, and realizing high-efficiency power supply.
The above is only a preferred embodiment of the present invention, and it should be noted that for those skilled in the art, without departing from the structure of the present invention, several modifications and improvements can be made, which will not affect the utility of the invention and the utility of the patent.

Claims (7)

1. An Oring circuit comprising an adapter (400) for accessing mains and a Battery (BAT) for backup power, characterized in that: the power supply system also comprises a first voltage stabilizing circuit (100) connected with the adapter (400) and used for stabilizing the output voltage of the adapter (400), a second voltage stabilizing circuit (200) connected with the Battery (BAT) and used for stabilizing the output voltage of the Battery (BAT), and a switching control circuit (300) which is respectively connected with the adapter (400), the first voltage stabilizing circuit (100) and the second voltage stabilizing circuit (200) and used for seamless power supply switching; the switching control circuit (300) comprises a first MOS tube (Q1), a second MOS tube (Q2) and a power output end (VDD) which is respectively connected with the drain electrode of the first MOS tube (Q1) and the source electrode of the second MOS tube (Q2), the grid electrode of the first MOS tube (Q1) is connected with the adapter (400) through a first resistor (R1), the grid electrode of the first MOS tube (Q1) is also connected with the source electrode of the first MOS tube (Q1) through a first voltage-stabilizing diode (V1) and a second resistor (R2) respectively, the source electrode of the first MOS tube (Q1) is connected with the output end of the first voltage stabilizing circuit (100) and is also connected with the ground wire through a fourth resistor (R4) and a second voltage stabilizing diode (V2) in turn, the source electrode of the first MOS tube (Q1) is also connected with the gate electrode of the second MOS tube (Q2) through a fifth resistor (R5), and the drain electrode of the second MOS tube (Q2) is connected with the output end of the second voltage stabilizing circuit (200).
2. An Oring circuit as claimed in claim 1, wherein: the first voltage stabilizing circuit (100) comprises an adaptive connection input end (VIN) and a buck voltage stabilizing chip (U1), wherein the adaptive connection input end (VIN) is used for being connected with an adapter (400), the input end of the buck voltage stabilizing chip (U1) is connected with the adaptive connection input end (VIN), the adaptive connection input end (VIN) is connected with a grid electrode of a first MOS (Q1) through a first resistor (R1), the buck voltage stabilizing chip is connected with a source electrode of the first MOS (Q1) through a first capacitor (C1) and a first inductor (L1) in sequence, a connection end of the first capacitor (C1) and the first inductor (L1) is connected with a conversion end of the buck voltage stabilizing chip (U1), a connection end of the first inductor (L1) and a source electrode of the first MOS (Q1) is connected with a ground wire through a third resistor (R3) and a seventh resistor (R7) in sequence and is also connected with a ground wire through a fourth capacitor (C4), and a feedback connection end of the third resistor (R3) is connected with a feedback end of the buck voltage stabilizing chip (U632).
3. An Oring circuit as claimed in claim 1, wherein: the second voltage stabilizing circuit (200) is provided with a boosting voltage stabilizing chip (U2) for boosting the output voltage of a Battery (BAT), the input end of the boosting voltage stabilizing chip (U2) is connected with the Battery (BAT), and the output end of the boosting voltage stabilizing chip (U2) is connected with the drain electrode of the second MOS tube (Q2).
4. An Oring circuit as claimed in claim 1, 2 or 3, wherein: the first MOS transistor (Q1) is an N-MOS transistor, and the second MOS transistor (Q2) is a P-MOS transistor.
5. An Oring circuit as claimed in claim 1, wherein: the first zener diode (V1) and the second zener diode (V2) are both 5V zener diodes.
6. An Oring circuit as claimed in claim 1, wherein: the first resistance (R1) is 4K Ω; the fourth resistance (R4) is 100 Ω.
7. An Oring circuit as claimed in claim 1, wherein: and the power supply output end (VDD) outputs direct current 5V voltage.
CN201922182384.4U 2019-12-07 2019-12-07 Oring circuit Active CN210693555U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201922182384.4U CN210693555U (en) 2019-12-07 2019-12-07 Oring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201922182384.4U CN210693555U (en) 2019-12-07 2019-12-07 Oring circuit

Publications (1)

Publication Number Publication Date
CN210693555U true CN210693555U (en) 2020-06-05

Family

ID=70904112

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201922182384.4U Active CN210693555U (en) 2019-12-07 2019-12-07 Oring circuit

Country Status (1)

Country Link
CN (1) CN210693555U (en)

Similar Documents

Publication Publication Date Title
US9391467B2 (en) Step-up battery charging management system and control method thereof
US8508963B2 (en) Step-down switching regulator capable of providing high-speed response with compact structure
CN202798467U (en) DC/DC converter, power supply device applying DC/DC converter, and electronic device
CN205355935U (en) Dual supply automatic switchover power supply and prevent circuit that power joins conversely
CN204131210U (en) Power supply switch circuit and portable electric appts
CN102118052B (en) Power supply management system
CN203313144U (en) Backflow prevention circuit
US20210091598A1 (en) Dual-mode high-efficiency voltage regulator for wireless charging modules
CN104779783B (en) A kind of power supply circuit and Switching Power Supply
CN103219893A (en) Switch power supply controller and switch power supply circuit
CN105162313B (en) A kind of inverse-excitation type switch power-supply
CN115498883A (en) Circuit for supplying power to switching power supply control circuit based on auxiliary winding
CN108110835B (en) Low-power consumption control circuit for high-voltage battery system
CN208904889U (en) Power supply timing control circuit
CN201638100U (en) High efficiency and low loss linear voltage-stabilizing and energy-saving device
CN109194126B (en) Power supply switching circuit
TW200931778A (en) Asynchronous boost converter
CN210693555U (en) Oring circuit
CN107733413B (en) Intelligent switch circuit and intelligent terminal of pre-installation battery system
CN115657538A (en) MCU uninterrupted power supply circuit
CN110048607A (en) A kind of conversion circuit and implementation method of seamless switching boosting and straight-through operating mode
CN109412436A (en) A kind of synchronous rectification control chip and circuit
CN205160203U (en) Automatic switching power stepup transformer of no relay
CN208939817U (en) High-voltage starting circuit and switching power supply
CN209072364U (en) A kind of synchronous rectification control chip and circuit

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
CP03 Change of name, title or address

Address after: 511356 Room 501, building 2, No. 63, Yong'an Avenue, Huangpu District, Guangzhou, Guangdong

Patentee after: Guangzhou lubangtong Internet of things Technology Co.,Ltd.

Address before: 510653 3rd floor, building F, kehuiyuan, 95 Daguan Road, Tianhe District, Guangzhou City, Guangdong Province

Patentee before: GUANGZHOU ROBUSTEL TECHNOLOGIES Co.,Ltd.

CP03 Change of name, title or address