CN210691297U - Starting device of controller and controller - Google Patents
Starting device of controller and controller Download PDFInfo
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- CN210691297U CN210691297U CN201922337878.5U CN201922337878U CN210691297U CN 210691297 U CN210691297 U CN 210691297U CN 201922337878 U CN201922337878 U CN 201922337878U CN 210691297 U CN210691297 U CN 210691297U
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Abstract
The utility model provides a starting drive and controller of controller, include: a processing chip and a switching circuit; after the processing chip is powered on, when the processing chip is powered on, the processing chip controls the general processor to be in a reset state, the switching circuit is controlled to enable the processing chip to be connected with the memory, data required when the controller is started and stored in the memory are read, a first check value of the data is calculated and obtained by utilizing the algorithm engine hard IP module, and if the first check value is consistent with a second check value in the processing chip, the switching circuit is controlled to enable the memory to be connected with the general processor, and the general processor is started based on the data. In the scheme, the processing chip directly calls the data stored in the memory through the bus to calculate the check value, so that the time for communication conversion through the interface in the prior art can be saved, the check speed is greatly increased, and the aim of accelerating the starting of the controller is fulfilled.
Description
Technical Field
The utility model relates to a computer technology field especially relates to a starting drive and controller of controller.
Background
With the development of scientific technology, industrial control systems and equipment on the internet are continuously increased, and security high-risk vulnerabilities of the industrial control systems are continuously emerged, so that the industrial information security situation becomes severe day by day.
In order to ensure the safety of industrial information, before the PLC main controller is started, whether the starting program code in the PLC main controller is tampered by an unauthorized mode needs to be checked, for example, the starting program code in the PLC main controller is tampered by a PLC worm virus mode. At present, a port of an algorithm chip is used for calculating a check value of code data corresponding to a starting program and an application program read by a memory and verifying the code data so that a PLC main controller can start the main controller according to a verification result. However, the port of the algorithm chip calculates the check value of the code data corresponding to the boot program and the application program read by the memory, and the check speed of the verification mode is slow, so that the check time is long, and the controller cannot be started quickly.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the present invention provides a starting apparatus for a controller and a controller, so as to solve the problem that the calibration time is long in the prior art, resulting in the controller being unable to be started quickly.
In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:
the embodiment of the utility model provides a first aspect discloses a starting drive of controller, include: a switching circuit and a processing chip;
the processing chip, the memory and the general processor in the controller are respectively connected with the switching circuit through buses;
an algorithm engine hard IP module is integrated in the processing chip;
after the processing chip is powered on, the processing chip controls the general processor to be in a reset state, controls the switching circuit to enable the processing chip to be connected with the memory, reads data stored in the memory and required when the controller is started, calculates and obtains a first check value of the data by using the algorithm engine hard IP module, and controls the switching circuit to enable the memory to be connected with the general processor if the first check value is consistent with a second check value in the processing chip, so that the general processor is started based on the data.
Optionally, the switching circuit includes a first bus switching gate circuit and a second bus switching gate circuit;
the first end of the first bus switching gate circuit is connected with the GPIO interface of the processing chip through a bus, the second end of the first bus switching gate circuit is connected with the memory through the bus, and the third end of the first bus switching gate circuit is connected with the SPI interface of the processing chip through the bus;
the first bus switching gate circuit is used for receiving conduction control information sent by the processing chip through a GPIO (general purpose input/output) interface, enabling a second end of the first bus switching gate circuit and the memory to be in a conduction state based on the conduction control information, enabling a third end of the first bus switching gate circuit and a Serial Peripheral Interface (SPI) of the processing chip to be in a conduction state, and enabling the SPI of the processing chip to be connected with the memory;
the first end of the second bus switching gate circuit is connected with the GPIO interface of the processing chip through a bus, the second end of the second bus switching gate circuit is connected with the memory through the bus, and the third end of the second bus switching gate circuit is connected with the memory interface of the general processor through the bus;
the second bus switching gate circuit is used for receiving conduction control information sent by the processing chip through a GPIO interface, enabling a second end of the second bus switching gate circuit and the memory to be in a conduction state based on the conduction control information, enabling a third end of the second bus switching gate circuit and a memory interface of the general processor to be in a conduction state, and enabling the memory and the memory interface of the general processor to be connected.
Optionally, the memory comprises a non-volatile memory;
the general purpose processor includes a reduced instruction set processor ARM and a MIPS PowerPC.
Optionally, the switching circuit is a tri-state gate output circuit.
Optionally, the processing chip is further configured to control the switching circuit to be in a disconnected state if the first check value is inconsistent with the second check value in the processing chip, so that the memory and the general processor are in a disconnected state.
The embodiment of the utility model provides an aspect two discloses a controller, the controller includes: general processor, memory and the starting drive that the embodiment of the utility model discloses the first aspect.
Based on above-mentioned the embodiment of the utility model provides a starting drive and controller of controller, include: a processing chip and a switching circuit; the processing chip, the memory and the general processor in the controller are respectively connected with the switching circuit through buses; when the processing chip is powered on, the processing chip controls the general processor to be in a reset state, the switching circuit is controlled to enable the processing chip to be connected with the memory, data required when the controller is started and stored in the memory are read, the algorithm engine hard IP module is used for calculating and obtaining a first check value of the data, and if the first check value is consistent with a second check value in the processing chip, the switching circuit is controlled to enable the memory to be connected with the general processor, and the general processor is started based on the data. It can be seen that, in the scheme, the processing chip directly calls the data stored in the memory through the bus, and utilizes the internal integrated algorithm engine hard IP module to perform calculation, and judges the first check value obtained by calculation and the second check value of the processing chip, so as to determine the second check value consistent with the first check value, and when the second check value consistent with the first check value is determined, the switching circuit is controlled to connect the memory and the general processor, so that the general processor is started based on the data, the time for communication conversion through the interface in the prior art can be saved, the check speed is greatly increased, and the purpose of accelerating the starting controller is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a block diagram of a starting apparatus of a controller according to an embodiment of the present invention;
fig. 2 is a specific structural block diagram of a starting apparatus of a controller according to an embodiment of the present invention;
fig. 3 is a schematic flowchart of a starting method of a controller according to an embodiment of the present invention;
fig. 4 is a schematic flowchart of a starting method of a controller according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In this application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
As known from the background art, in order to ensure the safety of industrial information, it is necessary to check whether the start-up program code in the PLC main controller is tampered with in an unauthorized manner before the PLC main controller is started, for example, the start-up program code in the PLC main controller is tampered with in a manner of a PLC worm virus. At present, in a conventional method, a programmable device, such as an FPGA, and an algorithm chip are mostly used, wherein the algorithm chip is provided with an SPI interface or other slow interface mode, and a start program of a read memory of the programmable device and code data corresponding to an application program are used for performing check value calculation and verification, so that a PLC main controller starts the main controller according to a verification result. According to the principle that the port of the algorithm chip calculates the check value of the code data corresponding to the starting program and the application program read by the memory, the access speed of the SPI interface or other slow interfaces is low, and meanwhile, the algorithm chip is superposed to process the interfaces, so that the check speed of the whole verification mode is low, the check time is long, and the controller cannot be started quickly.
Therefore, the embodiment of the utility model discloses starting drive and controller of controller handles the data that the chip directly called storage in the memory through the bus and carries out the check-up value calculation, can save the time through interface communication conversion among the prior art, increases substantially the check-up speed, realizes accelerating starting drive's purpose.
Referring to fig. 1, in order to provide an actuating apparatus for a controller according to an embodiment of the present invention, the actuating apparatus 100 for a controller includes: a processing chip 200 and a switching circuit 300.
The processing chip 200 is connected to the controller and the memory through the switching circuit 300, respectively.
The processing chip 200 and the switching circuit 300 are connected by a bus, the switching circuit 300 and the controller are also connected by a bus, and the switching circuit 300 and the memory are also connected by a bus.
Optionally, the processing chip 200 may be a programmable secure cryptographic algorithm chip.
Optionally, the processing chip 200 may be designed based on a 32-bit CPU security kernel CS0, has the characteristics of low power consumption, high performance, multiple functions, high security, and the like, and may be widely applied to USB keys, smart cards, card readers, encryption boards, and the like.
The processing chip 200 is internally integrated with an algorithm engine hard IP block.
When the processing chip 200 is powered on, the processing chip 200 controls the general processor to be in a reset state, the switching circuit 300 is controlled to enable the processing chip to be connected with the memory, data required when the controller is started and stored in the memory is read, a first check value of the data is calculated and obtained by using an algorithm engine hard IP module, and if the first check value is consistent with a second check value in the processing chip, the switching circuit is controlled to enable the memory to be connected with the general processor, and the general processor is enabled to be started based on the data.
The switching circuit 300 switches the processing chip 200 to be connected with the memory or switches the memory to be connected with the general-purpose processor by the control of the processing chip 200.
Specifically, after the processing chip 200 detects that the power supply of the industrial control system is turned on, that is, after the industrial control system is powered on, it determines that the current switching circuit 300, the general-purpose processor in the controller, and the memory are all in the off state, and after the processing chip 200 is started, the general-purpose processor in the controller is controlled to be restored to the initial state.
The processing chip 200 sends switching control information to the switching circuit 300, and the switching circuit 300 is controlled to connect the processing chip 200 with the memory based on the control information; code data of the BOOT, an Operating System (OS) and an application program, which are required when the controller is started and stored in the memory, are acquired, and a first check value of the code data of the BOOT, the OS and the application program, which correspond to each other, is calculated by using an algorithm engine hard IP module integrated in the memory, so that an internal bus of the processing chip 200 efficiently and quickly calculates the first check value of the code data of the BOOT, the OS and the application program; when the first check value is consistent with the second check value pre-stored in the processing chip, the processing chip 200 sends switching control information to the switching circuit 300, controls the switching circuit 300 to connect the memory with the general-purpose processor based on the control information, and releases the reset state to the general-purpose processor, so that the general-purpose processor can normally start the controller based on the code data of the BOOT, the OS and the application program.
In the embodiment of the present invention, the processing chip 200 has a safety protection function, and can perform physical damage such as reverse analysis on the chip.
Optionally, the processing chip 200 is configured to read data stored in the memory, calculate and obtain a first check value of the data, and specifically, to read the data stored in the memory, calculate a check value of the data based on the internal integration algorithm engine hard IP module, and obtain a first check value of the corresponding data.
Optionally, the processing chip 200 is further configured to control the switching circuit to be in a disconnected state if the first check value is inconsistent with the second check value in the processing chip, so that the memory and the general processor are in a disconnected state.
Specifically, if the first check value is not consistent with the second check value in the processing chip 200, the processing chip 200 sends the switching circuit 300 the cut-off control information, so that the level state of the second bus switching gate circuit 302 is converted from the low level state to the high impedance state, and the memory and the general-purpose processor are in the cut-off state.
It should be noted that the memory may be a nonvolatile memory FLASH or other memory capable of storing data.
Optionally, the general-purpose processor is a Central Processing Unit (CPU) in the controller, and the specific structure of the general-purpose processor includes: a memory interface connected with the switching circuit 200, a BOOT static random access memory BOOT SRAM, a core processor and a BOOT memory BOOT ROM.
It should be noted that, the general processor in the controller may be an risc processor (ARM), or may be an MIPS PowerPC, etc., and the embodiment of the present invention is not limited thereto.
The memory Interface can be Serial Peripheral Interface (SPI), or queue Serial Peripheral Interface protocol (Queued SPI, QSPI), etc., to this can set for according to actual conditions, the embodiment of the utility model provides a do not put the restriction.
Optionally, the memory is a FLASH memory in a non-volatile memory, which can still store data quickly after the industrial control system is powered down.
Optionally, the processing chip 200 further has a safety monitoring and protection module, which is mainly used for voltage anomaly detection, illumination anomaly detection, power glitch detection, temperature anomaly detection, frequency anomaly detection, metal shielding protection, clock and reset pulse filtering, and safety optimization wiring.
The embodiment of the utility model provides an in, including handling chip and switching circuit, handle the data that the chip directly called storage in the memory through the bus, and utilize the hard IP module of algorithm engine of internal integration to calculate, and judge the first check-up value that obtains and the second check-up value of handling the chip of calculation, thereby confirm the second check-up value unanimous with first check-up value, when confirming the second check-up value unanimous with first check-up value, control switching circuit makes memory and general purpose processor switch-on, make general purpose processor based on data start, can save the time through interface communication conversion among the prior art, increase substantially the check-up speed, realize accelerating the purpose of start control ware.
Further, based on the safety monitoring and protection module in the processing chip 200, the safety of starting the controller is improved at the same time.
Based on the starting drive of the above-mentioned controller that fig. 1 shows, the embodiment of the utility model discloses in concrete realization, still disclose the specific structure of the switching circuit that fig. 1 shows, as shown in fig. 2, for the embodiment of the utility model provides a specific structure block diagram of the starting drive of controller.
The switching circuit 300 includes a first bus switching gate 301 and a second bus switching gate 302.
Optionally, the specific structure of the processing chip 200 includes: general-purpose input and output (GPIO) interface, code check module, algorithm engine hard IP module and SPI interface.
It should be noted that the algorithm engine hard IP block is a comprehensive functional block, and the structure of the algorithm engine hard IP block is a fixed topology layout and a specific process, which can ensure the performance of the processing chip 200.
The first end of the first bus switching gate 301 is connected to the GPIO interface of the processing chip 200 through a bus, the second end of the first bus switching gate 301 is connected to the memory through a bus, and the third end of the first bus switching gate 301 is connected to the SPI interface of the processing chip through a bus.
The first bus switching gate 301 is configured to receive conduction control information sent by the processing chip 200 through the GPIO interface, enable a second end of the first bus switching gate 301 and the memory to be in a conduction state based on the conduction control information, and enable a third end of the first bus switching gate 301 and the SPI interface of the processing chip to be in a conduction state, so that the SPI interface of the processing chip 200 and the memory are connected.
The first end of the second bus switching gate 302 is connected to the GPIO interface of the processing chip 200 through a bus, the second end of the second bus switching gate 302 is connected to the memory through a bus, and the third end of the second bus switching gate 302 is connected to the memory interface of the general-purpose processor through a bus.
And the second bus switching gate circuit 302 is configured to receive conduction control information sent by the processing chip 200 through the GPIO interface, enable a second end of the second bus switching gate circuit 302 and the memory to be in a conduction state based on the conduction control information, enable a third end of the second bus switching gate circuit 302 and the memory interface of the general-purpose processor to be in a conduction state, and enable the memory and the memory interface of the general-purpose processor to be connected.
It should be noted that the first bus switching gate circuit 301 and the second bus switching gate circuit 302 are tri-state gate output circuits, and the level states of the tri-state gate output circuits include a high level state, a low level state, and a high resistance state.
The high impedance state is used to indicate that the memory and the processing chip connected to the first bus switching gate 301 are in an off state.
And a low state for indicating that the memory and the processing chip connected to the first bus switching gate circuit 301 are in a conducting state.
Optionally, the processing chip 200 receives conduction control information sent by the GPIO interface, so that the level state of the first bus switching gate 301 is converted from the high-impedance state to the low-impedance state, the second terminal of the first bus switching gate is in a conduction state with the memory based on the low-impedance level, and the third terminal of the first bus switching gate is in a conduction state with the SPI interface of the processing chip 200 based on the low-impedance level, so that the SPI interface of the processing chip 200 is connected to the memory.
Optionally, the receiving processing chip 200 receives conduction control information sent by the GPIO interface, so that the level state of the second bus switching gate 302 is converted from the high-impedance state to the low-impedance state, and the second terminal of the second bus switching gate is in a conduction state with the memory based on the low-impedance level, and the third terminal of the second bus switching gate is in a conduction state with the memory interface of the general-purpose processor based on the low-impedance level, so that the general-purpose processor is connected with the memory.
The embodiment of the utility model provides an in, when receiving the on-state control information who handles the chip, first bus switching gate circuit is based on-state control information, makes processing chip and memory switch-on, and second bus switching gate circuit is based on-state control information, makes memory and general purpose processor switch-on to the general purpose processor of follow-up safe cipher algorithm information control can be saved the time through interface communication conversion among the prior art based on data start, increases substantially the check-up speed, realizes accelerating the purpose of start control ware.
Optionally, in addition to the structure of the switching circuit shown in fig. 2, the switching circuit may also be a third bus switching gate circuit.
The first end of the third bus switching gate circuit is connected with the GPIO interface of the processing chip 200 through a bus, the second end of the third bus switching gate circuit is connected with the memory through a bus, and the third end of the third bus switching gate circuit is connected with the SPI interface of the processing chip 200 through a bus.
It should be noted that the third bus switching gate circuit may be a bidirectional tri-state gate output circuit, and the level states of the bidirectional tri-state gate output circuit include a high level state, a low level state and a high impedance state.
And the high-resistance state is used for indicating that the memory and the processing chip connected with the third bus switching gate circuit are in a disconnected state.
And the low level state is used for indicating that the memory and the processing chip which are connected with the third bus switching gate circuit are in a conducting state.
And a high state for indicating that the memory and the general-purpose processor connected with the third bus switching gate circuit are in a conducting state.
Specifically, the conduction control information sent by the processing chip 200 is received, and the level state of the third bus switching gate circuit is converted from the high-impedance state to the low-level state, so that the processing chip 200 is connected with the memory through the SPI interface of the processing chip 200; and receiving the conduction control information sent by the processing chip 200, and converting the level state of the third bus switching gate circuit from the high-impedance state to the high-level state, so that the memory and the general-purpose processor are switched on.
Optionally, the third bus switching gate circuit may be not only a bidirectional tri-state gate output circuit, but also two tri-state gate output circuits connected in parallel, which is not limited by the embodiment of the present invention.
The embodiment of the utility model provides an in, when receiving the on-state control information who handles the chip, third bus switching gate circuit is based on low level state, makes handle chip and memory switch-on, makes memory and general purpose processor switch-on based on high level state to follow-up safe cipher algorithm information control general purpose processor able to programme can save the time through interface communication conversion among the prior art based on data start, increases substantially the check-up speed, realizes accelerating the purpose of start control ware.
Optionally, an embodiment of the present invention provides a controller, which includes: general processor, memory and the starting drive of the controller that any embodiment of the utility model provides above-mentioned.
In conclusion, this control includes general purpose processor, memory and the aforesaid the utility model discloses the starting drive of controller that any embodiment provided, handle the chip and directly call the data of storage in the memory and utilize the hard IP module of internal integration's algorithm engine to calculate through the bus, and judge the first check-up value that obtains and the second check-up value of handling the chip to confirm the second check-up value unanimous with first check-up value, when confirming the second check-up value unanimous with first check-up value, control switching circuit makes memory and general purpose processor switch-on, make general purpose processor start based on data, can save the time through interface communication conversion among the prior art, increase substantially the check-up speed, realize accelerating the purpose of start control ware.
Based on the starting drive of the controller that is shown by fig. 1 to fig. 2 and comprises switching circuit and processing chip, the utility model discloses still correspond and disclose a starting method of controller, as shown in fig. 3, for the embodiment of the utility model provides a flow chart diagram of a starting method of controller, this method includes:
step S301: after power-on, the processing chip controls the general-purpose processor in the controller to be in a reset state.
Note that the circuit is restored to the initial state.
In the process of implementing step S301 specifically, when it is detected that the power supply of the industrial control system is turned on, that is, the controller is powered on, the processing chip sends out control information, and the general purpose processor in the controller is controlled to prepare to start the reset program, so that the general purpose processor of the controller is in a reset state.
It should be noted that the reset program refers to an algorithm that can restore the general-purpose processor in the controller to the initial state.
Step S302: the processing chip controls the switching circuit to enable the processing chip to be communicated with the memory.
In step S302, data necessary when the controller is started is stored in the memory.
In the process of implementing step S302, the processing chip sends control information to the switching circuit, and controls the processing chip to be connected to the memory.
In an embodiment of the present invention, the data required when starting the controller stored in the memory includes code data of the BOOT, the OS, and the application program in the controller.
Step S303: the processing chip reads the data stored in the memory, and calculates and obtains a first check value of the data by utilizing an internal integrated algorithm engine hard IP module.
In the process of implementing step S303 specifically, the processing chip reads code data of the BOOT, the OS, and the application program in the controller stored in the memory, and calculates check values of the code data of the BOOT, the OS, and the application program in the controller based on an internal integration algorithm, that is, an algorithm engine hard IP module, to obtain first check values corresponding to the code data of the BOOT, the OS, and the application program in the controller.
Step S304: and judging whether the first check value is consistent with the second check value in the processing chip, if so, executing the step S305, and if not, executing the step S306.
In the specific implementation step S304, all the second check values stored in the processing chip are traversed, the second check value consistent with the first check value is searched, if the second check value consistent with the first check value is found, step S305 is executed, and if the second check value consistent with the first check value is not found, step S306 is executed.
It should be noted that the second check value is preset to be stored.
Optionally, the pre-storing process of the second check value is as follows:
code data of BOOT, OS and application programs required for each controller to start up in a history period are acquired based on the processing chip.
The historical time period is set according to the experience of the technician, and may be set to 6 months, for example.
And calculating code data of BOOT, OS and application programs required by the startup of each controller in a historical time period based on an internal integration algorithm, namely an algorithm engine hard IP module, obtaining second check values of the code data of the BOOT, the OS and the application programs required by the startup of each controller, and storing the second check values.
Step S305: the processing chip controls the switching circuit to enable the memory to be connected with the general-purpose processor, and the general-purpose processor is enabled based on the data.
In the process of implementing step S305 specifically, the processing chip sends close control information to the switching circuit, controls the switching circuit to close, connects the memory with the general-purpose processor, and releases the reset state of the general-purpose processor, so that the general-purpose processor is started normally based on the BOOT code data of the BOOT, the OS, and the application program in the controller.
Step S306: the processing chip controls the switching circuit to enable the memory and the general-purpose processor to be in a disconnected state.
In the process of implementing step S306 specifically, the processing chip sends cut-off control information to the switching circuit, controls the switching circuit to be turned off, and makes the memory and the general-purpose processor in a disconnected state, and sends reset control information to the general-purpose processor, so as to reset the general-purpose processor based on the reset control information.
It should be noted that, the above-mentioned concrete principle and the implementation process of the starting method of the controller disclosed in the embodiment of the present invention are the same as the above-mentioned principle and implementation process shown by each unit of the starting device of the controller implemented in the present invention, and refer to the above-mentioned corresponding part in the starting device of the controller disclosed in the embodiment of the present invention, which is not described herein again.
The embodiment of the utility model provides an in, handle the chip and directly call the data of storage in the memory through the bus and calculate, and judge the first check-up value that obtains and the second check-up value of handling the chip to the calculation, thereby confirm the second check-up value unanimous with first check-up value, when confirming the second check-up value unanimous with first check-up value, control switching circuit makes memory and general purpose processor switch-on, make general purpose processor start based on data, can save the time through interface communication conversion among the prior art, increase substantially the check-up speed, realize accelerating the purpose of start control ware.
Optionally, based on the above the utility model discloses a switching circuit, switching circuit include first bus switching gate circuit and second bus switching gate circuit, explain first bus switching gate circuit and second bus switching gate circuit's concrete realization process, as shown in fig. 4, do the utility model discloses the implementation provides a starting method of controller.
Step S401: after power-on, the processing chip controls the general-purpose processor in the controller to be in a reset state.
It should be noted that the specific implementation process of step S401 is the same as the specific implementation process of step S301, and reference may be made to each other.
Step S402: and the processing chip sends conduction control information to the first bus switching gate circuit through the GPIO interface.
In the process of implementing step S402, the processing chip sends conduction control information to the first bus switching gate circuit through the GPIO interface to control the level state of the first bus switching gate circuit to change from the high-impedance state to the low-level state.
Step S403: the first bus switching gate circuit connects the SPI interface of the processing chip to the memory based on the conduction control information.
In the process of implementing step S403, the first bus switching gate circuit makes the processing chip connect to the memory through its SPI interface based on the low level state.
Step S404: the processing chip reads the data stored in the memory, and calculates and obtains a first check value of the data by utilizing an internal integrated algorithm engine hard IP module.
Step S405: and judging whether the first check value is consistent with the second check value in the processing chip, if so, executing the step S406 to the step S407, and if not, executing the step S408.
It should be noted that the specific implementation process of step S404 to step S405 is the same as the specific implementation process of step S303 to step S304.
Step S406: and the processing chip sends conduction control information to the second bus switching gate circuit through the GPIO interface.
In the process of implementing step S406 specifically, the processing chip sends conduction control information to the first bus switching gate circuit through the GPIO interface to control the level state of the second bus switching gate circuit to be converted from the high-impedance state to the low-level state.
Step S407: the second bus switching gate circuit turns on the memory and the memory interface of the general-purpose processor based on the conduction control information, so that the general-purpose processor is started based on the data.
In the process of implementing step S407, the second bus switching gate circuit turns on the memory interface between the memory and the general-purpose processor based on the low state, so that the general-purpose processor is started based on the data.
Step S408: the processing chip controls the switching circuit to enable the memory and the general-purpose processor to be in a disconnected state.
In the process of implementing step S408 specifically, the processing chip sends the cut-off control information to the second bus switching gate circuit through the GPIO interface, so that the level state of the second bus switching gate circuit is the high-impedance state, and the memory and the general-purpose processor are in the off state based on the high-impedance state of the second bus switching gate circuit.
In the embodiment of the utility model, when receiving the control information that switches on of handling the chip, first bus switching gate circuit makes and handles chip and memory switch-on based on the control information that switches on, and second bus switching gate circuit makes memory and general purpose processor switch-on based on the control information that switches on to follow-up safe cipher algorithm information control general purpose processor can save the time through interface communication conversion among the prior art based on data start, increases substantially the check-up speed, realizes accelerating the purpose of start control ware.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the system or system embodiments are substantially similar to the method embodiments and therefore are described in a relatively simple manner, and reference may be made to some of the descriptions of the method embodiments for related points. The above-described system and system embodiments are only illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. An actuator for a controller, comprising: a switching circuit and a processing chip;
the processing chip, the memory and the general processor in the controller are respectively connected with the switching circuit through buses;
an algorithm engine hard IP module is integrated in the processing chip;
after the processing chip is powered on, the processing chip controls the general processor to be in a reset state, controls the switching circuit to enable the processing chip to be connected with the memory, reads data stored in the memory and required when the controller is started, calculates and obtains a first check value of the data by using the algorithm engine hard IP module, and controls the switching circuit to enable the memory to be connected with the general processor if the first check value is consistent with a second check value in the processing chip, so that the general processor is started based on the data.
2. The apparatus of claim 1, wherein the switching circuit comprises a first bus switching gate and a second bus switching gate;
the first end of the first bus switching gate circuit is connected with the GPIO interface of the processing chip through a bus, the second end of the first bus switching gate circuit is connected with the memory through the bus, and the third end of the first bus switching gate circuit is connected with the SPI interface of the processing chip through the bus;
the first bus switching gate circuit is used for receiving conduction control information sent by the processing chip through a GPIO (general purpose input/output) interface, enabling a second end of the first bus switching gate circuit and the memory to be in a conduction state based on the conduction control information, enabling a third end of the first bus switching gate circuit and a Serial Peripheral Interface (SPI) of the processing chip to be in a conduction state, and enabling the SPI of the processing chip to be connected with the memory;
the first end of the second bus switching gate circuit is connected with the GPIO interface of the processing chip through a bus, the second end of the second bus switching gate circuit is connected with the memory through the bus, and the third end of the second bus switching gate circuit is connected with the memory interface of the general processor through the bus;
the second bus switching gate circuit is used for receiving conduction control information sent by the processing chip through a GPIO interface, enabling a second end of the second bus switching gate circuit and the memory to be in a conduction state based on the conduction control information, enabling a third end of the second bus switching gate circuit and a memory interface of the general processor to be in a conduction state, and enabling the memory and the memory interface of the general processor to be connected.
3. The apparatus of claim 1, wherein the memory comprises a non-volatile memory;
the general purpose processor includes a reduced instruction set processor ARM and a MIPS PowerPC.
4. The apparatus of claim 1, wherein the switching circuit is a tri-state gate output circuit.
5. The apparatus of claim 1, wherein the processing chip is further configured to control the switching circuit to be in an off state if the first check value is inconsistent with the second check value in the processing chip, so that the memory is in an off state with the general purpose processor.
6. A controller, characterized in that the controller comprises: a general purpose processor, memory and the activation device of any one of claims 1 to 5.
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|---|---|---|---|
| CN201922337878.5U CN210691297U (en) | 2019-12-23 | 2019-12-23 | Starting device of controller and controller |
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| CN201922337878.5U CN210691297U (en) | 2019-12-23 | 2019-12-23 | Starting device of controller and controller |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110888691A (en) * | 2019-12-23 | 2020-03-17 | 宁波和利时信息安全研究院有限公司 | Controller starting method and device |
| CN116719583A (en) * | 2023-08-08 | 2023-09-08 | 飞腾信息技术有限公司 | Starting method, programmable logic device, computing equipment and storage medium |
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2019
- 2019-12-23 CN CN201922337878.5U patent/CN210691297U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110888691A (en) * | 2019-12-23 | 2020-03-17 | 宁波和利时信息安全研究院有限公司 | Controller starting method and device |
| CN116719583A (en) * | 2023-08-08 | 2023-09-08 | 飞腾信息技术有限公司 | Starting method, programmable logic device, computing equipment and storage medium |
| CN116719583B (en) * | 2023-08-08 | 2023-11-10 | 飞腾信息技术有限公司 | Starting method, programmable logic device, computing equipment and storage medium |
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