CN210691255U

CN210691255U - Synchronous awakening device

Info

Publication number: CN210691255U
Application number: CN201922029186.4U
Authority: CN
Inventors: 刘群; 林冲
Original assignee: Armorlink SH Corp
Current assignee: Armorlink SH Corp
Priority date: 2019-11-21
Filing date: 2019-11-21
Publication date: 2020-06-05
Anticipated expiration: 2029-11-21

Abstract

The utility model discloses a synchronous awakening device for awaken up at least one host computer or awaken up simultaneously and be more than a host computer, including main control unit, network connection unit, memory cell, input/output unit, main control unit is used for according to network connection unit's instruction, and the corresponding control signal of output passes through the action of network connection unit control host computer, and memory cell is used for saving main control unit's operational data, and network connection unit, memory cell, input/output unit are connected with main control unit respectively. According to the method and the device, under the condition that the host is shut down, the host is awakened through the network, and a plurality of hosts can be awakened simultaneously, so that the remote control under the condition that the host is shut down is realized, and the time and the electric energy are saved.

Description

Synchronous awakening device

Technical Field

The utility model belongs to the technical field of the computer technology and specifically relates to a synchronous awakening device is related to.

Background

At present, the remote control of a host is realized through remote operation software on the host under the condition that the host is powered on, and the remote control cannot be realized under the condition that the host is powered off, but the situation also occurs, people are not in front of the host, but need to complete the processing of some things through a plurality of hosts, and cannot return to the hosts at once, which becomes a defect of the remote control.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a synchronous awakening device is in under the condition of shutting down at the host computer, realizes awakening up to the host computer through the network, and can awaken up many host computers simultaneously, has realized the remote control under the host computer shutdown condition, saves time and electric energy.

The above technical scheme of the utility model can be realized through following technical scheme to the purpose:

a synchronous awakening device is used for awakening at least one host or simultaneously awakening more than one host and comprises a main control unit, a network connection unit, a storage unit and an input/output unit, wherein the main control unit is used for outputting corresponding control signals according to instructions of the network connection unit and controlling the host to act through the network connection unit, the storage unit is used for storing operation data of the main control unit, and the network connection unit, the storage unit and the input/output unit are respectively connected with the main control unit.

The utility model discloses further set up to: the main control unit comprises a main control chip used for operating and processing data in computer software, wherein the main control chip comprises a memory controller, a storage controller, a display controller, a network controller, a serial camera interface controller, a universal input/output controller, a serial port controller, a time schedule controller and a power-on configuration controller, and the main control chip is respectively used for communicating with external equipment.

The utility model discloses further set up to: the storage unit comprises memory particles and is used for temporarily storing operation data in the main control chip and data exchanged with the memory particles, and the main control unit is connected with the memory particles through memory control.

The utility model discloses further set up to: the memory unit also comprises memory particles for storing an operating system, programs and data, and the main control chip is connected with the memory particles (eMMC) through an SDIO protocol.

The utility model discloses further set up to: the storage unit also comprises a charged erasable programmable read-only memory used for storing startup configuration information, and the main control chip is connected with the EEPROM through an SPI protocol.

The utility model discloses further set up to: the network connection unit comprises a port physical layer, a network interface and a WIFI module, the port physical layer and the WIFI module are respectively connected with the main control unit, and the port physical layer is connected with the network interface.

The utility model discloses further set up to: the port physical layer comprises at least one network physical layer chip, and each network physical layer chip is correspondingly connected with one network interface.

The utility model discloses further set up to: the input and output unit comprises a debugging interface, a UART display interface and a USB interface, which are respectively connected with the main control unit and used for realizing different interface communication.

The utility model discloses further set up to: the USB interface comprises a TYPE-C logic chip, and the TYPE-C interface supplies power for the synchronous awakening device.

The utility model discloses further set up to: and a POE mode is adopted to supply power to the synchronous awakening device.

Compared with the prior art, the utility model has the beneficial technical effects that:

1. the main control unit is arranged, so that data processing and calculation are realized, and the purpose of synchronous awakening is achieved;

2. furthermore, the remote connection with the host is realized through the network connection unit, and a basis is provided for remote awakening;

3. furthermore, the data storage space of the main control operation is increased and the operation speed is improved by arranging the storage unit.

4. Furthermore, the system and the method have the advantages that the cost is reduced and the energy consumption is reduced by synchronously waking up the plurality of hosts.

Drawings

Fig. 1 is a schematic circuit diagram of a synchronous wake-up device according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a memory controller according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a memory pellet circuit configuration according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a memory control circuit according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a memory chip (eMMC) circuit structure according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a network controller circuit according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a port physical layer circuit structure according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

The utility model discloses a synchronous awakening device for awaken up at least one host computer or awaken up simultaneously and be more than a host computer, including main control unit, network connection unit, memory cell, input/output unit, main control unit is used for according to network connection unit's instruction, and the corresponding control signal of output passes through the action of network connection unit control host computer, and memory cell is used for saving main control unit's operational data, and network connection unit, memory cell, input/output unit are connected with main control unit respectively.

In a specific embodiment of the present application, the main control unit includes a main control chip for computing and processing data in computer software, and the main control chip includes a memory controller, a storage controller, a display controller, a network controller, a serial camera interface controller, a general input/output controller, a serial controller, a timing controller, and a power-on configuration controller, which are respectively used for communicating with an external device.

Specifically, as shown in fig. 2 and 3, fig. 2 shows a memory controller of the main control chip, and fig. 3 shows a memory granule.

Specifically, the main control chip reads instructions and data from the memory, and performs arithmetic processing on the data according to the specification of the instruction operation code to realize the operation of a program or the processing of the data. The memory granule can load program codes in the eMMC to be used by the main control chip, and can also store some temporary data required by the main control chip to be used next time or stored in the eMMC.

As shown in fig. 4 and 5, fig. 4 shows a memory controller of a main control chip, and fig. 5 shows a memory device eMMC.

The memory controller is used for exchanging data with the memory unit, comprises 8 lines of data lines and adopts a NAND (instead: Emmc) memory.

The main control chip can operate and process data, but has no way of permanently storing data, when executing an instruction, the main control chip reads the data from the memory first, if the memory does not have the desired data, the corresponding program instruction in the eMMC can be directly loaded in the memory, and at the moment, the main control chip performs addressing operation on the memory and then operates.

Fig. 6 and 7 show an ethernet MAC of the host chip in fig. 6, and fig. 7 shows a PHY interface in fig. 7.

In the application, two-way network interfaces are adopted, and each network controller transmits signals through a serial port (instead: through an RMII protocol), wherein the signals comprise 8-line transmission and respectively comprise ENET1_ TXD0, ENET1_ TXD1, ENET1_ TXEN, ENET _ REF _ CLK1, ENET2_ TXD0, ENET1_ RXD0, ENET1_ RXD1, ENET1_ RXRE and ENET1_ CRS _ DV signal lines.

The general purpose input and output controller transmission signal comprises 6 paths of GPIO control signals.

The serial port controller transmits UART signals, is respectively used for serial port communication with external equipment, and is mainly used for connecting and connecting a debugging interface and UART display.

The time sequence controller is used for connecting the crystal oscillator and providing time sequence for the main control unit. The time sequence control is strictly in accordance with the specifications of the main control chip, and the stable operation of the product is ensured.

The starting configuration controller is used for setting an initial state after starting and is respectively externally connected with a pull-up resistor and a pull-down resistor for setting.

In an embodiment of the present application, the memory unit includes a memory granule and a memory granule, the memory granule is used for temporarily storing the operation data in the main control chip and the data exchanged with the memory granule, and the main control unit is connected with the memory granule through a memory controller. The memory particles are used for storing an operating system, programs and data, and the main control chip is connected with the memory particles through an SDIO protocol.

Specifically, as the memory particles shown in fig. 6, DDR3L particles are used. The memory grain adopts an eMMC memory.

In a specific embodiment of the present application, the storage unit further includes a charged erasable programmable read only memory for storing the boot configuration information, and the main control chip is connected to the EEPROM through the SPI protocol.

In a specific embodiment of the present application, the network connection unit includes a port physical layer, a network interface, and a WIFI module, the port physical layer and the WIFI module are respectively connected to the main control unit, and the port physical layer is connected to the network interface.

The port physical layer comprises at least one network physical layer chip, and each network physical layer chip is correspondingly connected with one network interface.

The WIFI module is mainly used for connecting an external network, when the synchronous awakening device and more than one host are connected to the same local area network through network cables, a user can not lose packets for multiple hosts through webpage operation before the host, and awakening more than one host to achieve the purpose of remote control.

Specifically, the present application includes two port physical layers and two network interfaces.

In an embodiment of the present application, the main control unit further includes a USB controller, a secure digital input/output card controller, and a digital conversion controller, respectively configured to control the USB interface, the secure digital input/output card, and the digital conversion.

In an embodiment of the present application, the input/output unit includes a debugging interface, a UART display interface, and a USB interface, which are respectively connected to the main control unit for implementing different interface communications.

The USB interface comprises a TYPE-C logic chip, and the TYPE-C interface supplies power for the synchronous awakening device.

In a specific embodiment of the present application, a POE manner is adopted to supply power to the synchronous wake-up device.

In a specific embodiment of the present application, the main control unit further includes a reset circuit for synchronizing the reset of the wake-up unit.

In a specific embodiment of the present application, the synchronous wake-up apparatus further includes a power circuit chip for providing power required by the main control chip and each chip.

In a specific embodiment of the present application, the synchronous wake-up device is powered by USB TYPE-C. The method and the system for waking up more than one host synchronously save cost compared with the method of waking up more than one host by using the server.

The embodiment of this specific implementation mode is the preferred embodiment of the present invention, not limit according to this the utility model discloses a protection scope, so: all equivalent changes made according to the structure, shape and principle of the utility model are covered within the protection scope of the utility model.

Claims

1. A synchronous wake-up device for waking up at least one host or more than one host simultaneously, comprising: the network connection unit transmits a wake-up command to the main control unit, the main control unit outputs a corresponding control signal according to the wake-up command of the network connection unit, the control signal is transmitted to the host through the network connection unit to control the host to act, the storage unit is used for storing operation data of the main control unit, the network connection unit, the storage unit and the input/output unit are respectively connected with the main control unit, and the input/output unit is used for interface communication.

2. Synchronous wake-up device according to claim 1, characterized in that: the main control unit comprises a main control chip used for operating and processing data in computer software, wherein the main control chip comprises a memory controller, a storage controller, a display controller, a network controller, a serial camera interface controller, a universal input/output controller, a serial port controller, a time schedule controller and a power-on configuration controller, and the main control chip is respectively used for communicating with external equipment.

3. Synchronous wake-up device according to claim 1, characterized in that: the storage unit comprises memory particles and is used for temporarily storing operation data in the main control chip and data exchanged with the memory particles, and the main control unit is connected with the memory particles through memory control.

4. Synchronous wake-up device according to claim 1, characterized in that: the storage unit also comprises storage particles used for storing an operating system, programs and data, and the main control chip is connected with the storage particles through an SDIO protocol.

5. Synchronous wake-up device according to claim 1, characterized in that: the storage unit also comprises a charged erasable programmable read-only memory used for storing startup configuration information, and the main control chip is connected with the EEPROM through an SPI protocol.

6. Synchronous wake-up device according to claim 1, characterized in that: the network connection unit comprises a port physical layer, a network interface and a WIFI module, the port physical layer and the WIFI module are respectively connected with the main control unit, the port physical layer is connected with the network interface, and the WIFI module is used for simultaneously waking up more than one host.

7. Synchronous wake-up device according to claim 6, characterized in that: the port physical layer comprises at least one network physical layer chip, and each network physical layer chip is correspondingly connected with one network interface.

8. Synchronous wake-up device according to claim 1, characterized in that: the input and output unit comprises a debugging interface, a UART display interface and a USB interface, which are respectively connected with the main control unit and used for realizing different interface communication.

9. Synchronous wake-up device according to claim 8, characterized in that: the USB interface comprises a TYPE-C logic chip, and the TYPE-C interface supplies power for the synchronous awakening device.

10. Synchronous wake-up device according to claim 1, characterized in that: and a POE mode is adopted to supply power to the synchronous awakening device.