CN210689411U - LDO optimization circuit based on digital detonator application - Google Patents
LDO optimization circuit based on digital detonator application Download PDFInfo
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- CN210689411U CN210689411U CN201921190897.3U CN201921190897U CN210689411U CN 210689411 U CN210689411 U CN 210689411U CN 201921190897 U CN201921190897 U CN 201921190897U CN 210689411 U CN210689411 U CN 210689411U
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Abstract
The utility model relates to a LDO optimization circuit based on digital detonator is used, including polarity electric capacity C1, electric capacity C2, electric capacity C3, resistance R1, stabiliser U1 and transient diode TVS, stabiliser U1's input is connected with resistance R1 and power respectively, it is parallelly connected with polarity electric capacity C1's positive pole and transient diode TVS's negative pole respectively between stabiliser U1's input and resistance R1, stabiliser U1's output is parallelly connected with electric capacity C2 and electric capacity C3 respectively, the other end of polarity electric capacity C1's negative pole, electric capacity C2, electric capacity C3 and transient diode TVS positive pole all with stabiliser U1's earthing terminal ground connection. The utility model discloses a parallelly connected 24V transient diode TVS in the input of LDO circuit, close and seal together, carry out the surge protection to the LDO circuit to impact when avoiding the blasting leads to the LDO circuit to have the excessive pressure influence.
Description
Technical Field
The utility model relates to a LDO circuit technical field especially relates to an LDO optimizing circuit based on digital detonator is used.
Background
With the development of electronic technology, in the metal mine blasting operation, the traditional blasting mode of detonating the detonator by using a fuse is not adopted any more, and at present, the digital detonator is widely used for controlling the blasting time of the detonator at regular time. Generally, equipment close to the interior of the mine explodes first, and equipment close to the exterior of the mine explodes later, however, in the use process of the digital detonator, after the equipment close to the interior of the mine explodes, a plurality of equipment close to the exterior of the mine do not explode. After the analysis of the circuit mainboard fragments after the collection and the detonation, the discovery is as follows: the MCU is not damaged, and the LDO at the front end of the MCU is damaged. The detection finds that the LDO is qualified, namely, the signal is received when the LDO is not blasted, but the LDO is damaged after other detonators are blasted. And the VIN pin and the GND pin of the integrated circuit board chip and the surface metal of the routing Pad are melted, and the VIN-GND end of the LDO has burning traces, so that the impact during blasting is presumed to have overvoltage influence. Because the LDO damage does not work when being used in a special environment, the circuit and the LDO capability are improved according to the problem so as to solve the practical problem.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an LDO optimizing circuit based on digital detonator is used, through parallelly connected 24V transient diode TVS in the input of LDO circuit, close and seal together, carry out the surge protection to the LDO circuit to impact when avoiding the blasting leads to the LDO circuit to have the excessive pressure influence.
In order to achieve the above purpose, the technical scheme of the utility model is as follows:
the utility model provides a LDO optimization circuit based on digital detonator uses, includes polarity electric capacity C1, electric capacity C2, electric capacity C3, resistance R1, stabiliser U1 and transient state diode TVS, the input of stabiliser U1 is connected with resistance R1 and power respectively, connect in parallel with polarity electric capacity C1's positive pole and transient state diode TVS's negative pole respectively between stabiliser U1's the input and resistance R1, stabiliser U1's output is connected in parallel with electric capacity C2 and electric capacity C3 respectively, polarity electric capacity C1's negative pole, electric capacity C2, electric capacity C3 and the other end of transient state diode TVS positive pole all with stabiliser U1's earthing terminal.
In the above scheme, at least one transient diode TVS is provided.
In the above scheme, the breakdown voltage of the transient diode TVS is 24V.
In the above scheme, a current limiting element is connected in series in the circuit of the transient diode TVS.
In the above scheme, the model of the transient diode TVS is SMBJ24 CA.
Compared with the prior art, the beneficial effects of the utility model are that: at least one transient diode TVS is connected in parallel with the input end of the LDO circuit, one end of the transient diode TVS is connected with the input end 3 of the voltage stabilizer U1, and the other end of the transient diode TVS is grounded together with the output end 1 of the voltage stabilizer U1. Through parallelly connected 24V transient diode TVS in the input of LDO circuit, close and seal together, carry out the surge protection to the LDO circuit to impact when avoiding the blasting leads to the LDO circuit to have the overvoltage influence.
Drawings
FIG. 1 is a circuit diagram of an LDO circuit in a conventional digital detonator chip;
FIG. 2 is a circuit diagram of LDO circuit in the digital thunder chip of the present invention;
Detailed Description
The technical solution of the present invention will be further described in detail with reference to the accompanying drawings and embodiments.
As shown in fig. 1 and 2, an LDO optimization circuit based on digital detonator application includes a polar capacitor C1, a capacitor C2, a capacitor C3, a resistor R1, a voltage regulator U1 and a transient diode TVS, an input end 3 of the voltage regulator U1 is connected to a resistor R1 and a power supply, an input end 3 of the voltage regulator U1 and the resistor R1 are connected in parallel to an anode of a polar capacitor C1 and a cathode of the transient diode TVS, an output end 2 of the voltage regulator U1 is connected in parallel to a capacitor C2 and a capacitor C3, and the other ends of a cathode of the polar capacitor C1, the capacitor C2, the capacitor C3 and an anode of the transient diode TVS are all grounded to a ground terminal 3 of the voltage regulator U1. The breakdown voltage of the transient diode TVS is 24V, and the model of the transient diode TVS is SMBJ24 CA.
As a preferred solution, the transient diode TVS is provided with at least one diode, and is connected in parallel to the LDO circuit in fig. 1.
Preferably, in order to limit the current flowing through the transient diode TVS not to exceed the peak current IPP allowed by the tube, a current limiting element, such as a resistor, a self-healing fuse, an inductor, etc., is added in series to the circuit.
Transient diodes TVS are a new type of highly efficient circuit protection device in common use that has extremely fast response times (sub-nanosecond range) and relatively high surge absorption capability. When two ends of the TVS are subjected to transient high-energy impact, the TVS can change the impedance value between the two ends from high impedance to low impedance at a very high speed to absorb a transient large current, so that the voltage between the two ends of the TVS is clamped on a preset value, and the following circuit elements are protected from the impact of transient high-voltage spike pulse. As such, TVS can be used to protect devices or circuits from static electricity, transient voltages generated when inductive loads are switched, and overvoltages generated by inductive lightning.
The transient diode TVS has the characteristics of high reflecting speed (pS level), small volume, low clamping voltage and high reliability.
TVS is used for transient surge suppression, in parallel with the protected device. Under normal working condition, TVS presents high impedance state to the protected circuit, when the instantaneous voltage exceeds its breakdown voltage, TVS provides a low impedance path for instantaneous current. The transient current flowing to the protected device is shunted to the TVS diode, and the voltage across the protected device is limited to the clamped voltage across the TVS. When this overvoltage condition disappears, the TVS diode will again return to the high impedance state.
By means of technical analysis of detonator blasting, the outer ring is easy to damage, and the phenomenon that the electric network is unstable and surge impact is generated after vibration is performed for many times possibly, so that an LDO circuit chip is damaged. In the improvement measure, surge protection is carried out by adding a transient diode TVS at the front end of the LDO circuit. In order to ensure that the transient diode TVS has better effect, the 24V transient diode TVS is connected in parallel with the input end of the LDO circuit and sealed together. After the scheme is used, no detonation phenomenon occurs in actual test and use. Therefore, the scheme has an effective protection effect on surge impact generated by blasting, so that the LDO circuit is prevented from being influenced by overvoltage due to impact during blasting.
The above-mentioned embodiments further explain in detail the objects, technical solutions and advantages of the present invention, and it should be understood that the above-mentioned embodiments are only the embodiments of the present invention, and are not intended to limit the scope of the present invention, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the scope of the present invention.
Claims (5)
1. The utility model provides a LDO optimal circuit based on digital detonator is used which characterized in that: the transient diode TVS comprises a polar capacitor C1, a capacitor C2, a capacitor C3, a resistor R1, a voltage stabilizer U1 and a transient diode TVS, wherein the input end of the voltage stabilizer U1 is respectively connected with a resistor R1 and a power supply, the anode of a polar capacitor C1 and the cathode of the transient diode TVS are respectively connected in parallel between the input end of the voltage stabilizer U1 and the resistor R1, the output end of the voltage stabilizer U1 is respectively connected in parallel with a capacitor C2 and a capacitor C3, and the other ends of the cathode of a polar capacitor C1, the capacitor C2, a capacitor C3 and the anode of the transient diode TVS are grounded with the grounding end of a voltage stabilizer U1.
2. The LDO optimization circuit according to claim 1, based on digital detonator application, characterized in that: the transient diode TVS is provided with at least one.
3. The LDO optimization circuit according to claim 1, based on digital detonator application, characterized in that: the breakdown voltage of the transient diode TVS tube is 24V.
4. The LDO optimization circuit according to claim 1, based on digital detonator application, characterized in that: a current limiting element is connected in series in the circuit of the transient diode TVS.
5. The LDO optimization circuit according to claim 1, based on digital detonator application, characterized in that: the model of the transient diode TVS is SMBJ24 CA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921190897.3U CN210689411U (en) | 2019-07-26 | 2019-07-26 | LDO optimization circuit based on digital detonator application |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921190897.3U CN210689411U (en) | 2019-07-26 | 2019-07-26 | LDO optimization circuit based on digital detonator application |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210689411U true CN210689411U (en) | 2020-06-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921190897.3U Active CN210689411U (en) | 2019-07-26 | 2019-07-26 | LDO optimization circuit based on digital detonator application |
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| Country | Link |
|---|---|
| CN (1) | CN210689411U (en) |
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2019
- 2019-07-26 CN CN201921190897.3U patent/CN210689411U/en active Active
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Address after: 210000 floor 13, tower C, Tengfei building, research and Innovation Park, Nanjing area, China (Jiangsu) pilot Free Trade Zone, Nanjing, Jiangsu Patentee after: Jiangsu Changjing Technology Co.,Ltd. Address before: Room 1087, hatch Eagle building, No. 99, Tuanjie Road, yanchuang Park, Jiangbei new district, Nanjing, Jiangsu 211800 Patentee before: Jiangsu Changjing Technology Co.,Ltd. |