CN207732419U - A kind of protective device of chip I/O Interface - Google Patents
A kind of protective device of chip I/O Interface Download PDFInfo
- Publication number
- CN207732419U CN207732419U CN201721722500.1U CN201721722500U CN207732419U CN 207732419 U CN207732419 U CN 207732419U CN 201721722500 U CN201721722500 U CN 201721722500U CN 207732419 U CN207732419 U CN 207732419U
- Authority
- CN
- China
- Prior art keywords
- protection location
- voltage
- chip
- high voltage
- threshold value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Emergency Protection Circuit Devices (AREA)
Abstract
The utility model embodiment provides a kind of protective device of chip I/O Interface, which includes：One the first protection location and at least one second protection location；Wherein, the first protection location is high voltage transient protection location, and the second protection location is high direct voltage protection location.High voltage transient protection location is provided with the first activation threshold value, and when chip port input voltage is higher than the first activation threshold value of high voltage transient protection location, high voltage transient protection location forms discharge circuit over the ground, is protected to chip interior module.High direct voltage protection location is provided with the second activation threshold value, and the high-pressure detection unit in high direct voltage protection location is detected chip port input voltage, and the folding of input circuit is controlled by switch, is protected to chip interior module.
Description
Technical field
The utility model is related to electronic chip field more particularly to a kind of protective devices of chip I/O Interface.
Background technology
Type-C interfaces of new generation become increasingly popular, and the CC interfaces in Type-C interfaces with the bus of transferring high voltage close to can be supplied
Electric (Voltage Bus, VBUS) interface causes to exist in use certain in conjunction with the mechanical structure feature of interface itself
Probability there is the risk of CC interfaces and VBUS interface short circuits, if short circuit while VBUS power supply be normal voltage, the short circuit is only
Connecting detection is will result only in go wrong；If short circuit while VBUS interfaces be in high-voltage state, then be likely to occur due to
The consequence that the connect chip of CC interfaces is not high voltage withstanding and burns.
Utility model content
When being in high-voltage state to solve VBUS interfaces, if short-circuit, cause the connect chip of CC interfaces intolerant to high electricity
The problem of pressing and burning.
The utility model embodiment provides a kind of protective device of chip I/O Interface, which includes：：One
First protection location and at least one second protection location；Wherein, the first protection location is high voltage transient protection location, and second protects
Shield unit is high direct voltage protection location.
High voltage transient protection location is provided with the first activation threshold value, when chip port input voltage is protected higher than high voltage transient
When the first activation threshold value of unit, high voltage transient protection location forms discharge circuit over the ground, is protected to chip interior module.
High direct voltage protection location is provided with the second activation threshold value, the high-pressure detection unit pair in high direct voltage protection location
Chip port input voltage is detected, and the folding of input circuit is controlled by switch, is protected to chip interior module.
High voltage transient protection location individually protects chip interior module with high direct voltage protection location.
High voltage transient protection location protects chip interior module with the cooperation of high direct voltage protection location.
First activation threshold value of high voltage transient protection location is higher than the second activation threshold value of high direct voltage protection location.
High voltage transient protection location handles high voltage overshoot concussion waveform.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram for chip I/O Interface protective device that the utility model embodiment provides；
Fig. 2 is a kind of structural schematic diagram for chip I/O Interface protective device that the utility model embodiment provides；
Fig. 3 is the high voltage transient protection location electrical block diagram that the utility model embodiment provides；
Fig. 4 is the high direct voltage protection location electrical block diagram that the utility model embodiment provides；
Fig. 5 is that the I/O interface high pressure overvoltages that the utility model embodiment provides are originally inputted waveform schematic diagram；
Fig. 6 is the I/O interfaces that provide of the utility model embodiment output waveform diagram after protective device.
Specific implementation mode
Below by attached drawing, the technical solution provided the utility model embodiment is described in further detail.
Fig. 1 is a kind of structural schematic diagram for chip I/O Interface protective device that the utility model embodiment provides.Such as Fig. 1
It is shown, it is provided with multiple protective unit in chip I/O Interface to the protected module access of chip interior, is followed successively by the first protection list
Member, the second protection location to N protect protection location, altogether N number of protection location, N >=2.Wherein, the first protection location is that transient state is high
It is high direct voltage protection location, the quantity of high direct voltage protection location to press protection location, the second protection location to N protection locations
It is configured according to the voltage condition in chip and physical circuit.
High voltage transient protection location can be provided with the first activation threshold value, when chip port input voltage is higher than high voltage transient
When the first activation threshold value of protection location, high voltage transient protection location forms discharge circuit over the ground, is carried out to chip interior module
Protection.
High direct voltage protection location can be provided with the second activation threshold value, and the high pressure detection in high direct voltage protection location is single
Member is detected chip port input voltage, and the folding of input circuit is controlled by switch, is protected to chip interior module
Shield.First activation threshold value of high voltage transient protection location is higher than the second activation threshold value of high direct voltage protection location.
Multiple protection locations both can respectively independently be protected chip interior by protection module, can also be according to high pressure
The feature of impact cooperates between each protection location, is protected to chip interior low-voltage module.
Fig. 2 is a kind of structural schematic diagram for chip I/O Interface protective device that the utility model embodiment provides.At one
In specific example, as shown in Fig. 2, the first protection location for including in the device is high voltage transient protection location, the second protection
Unit is high direct voltage protection location, by a high voltage transient protection location and a high direct voltage protection location in chip
The shielded module in portion is protected.
When chip port input voltage be higher than predetermined threshold value after, high voltage transient protection location formed over the ground discharge path with
Implement protection, the response time of protection is exceedingly fast, and primarily serves too high voltages overshoot concussion when contacting initial for high pressure
Internal protective effect, to ensure that the input voltage of high direct voltage protection location is limited in the voltage range that it can bear.
The voltage that high-pressure detection unit in high direct voltage protection location inputs chip port is detected and identifies.Directly
The triggering for flowing high voltage protective unit needs certain response time, can not be as high voltage transient protection location immediately to chip
Internal module is protected, but can implement the protection of long period.If the input electricity after high voltage transient protection location
Pressure higher than its first activation threshold value be then detected as high voltage input, then control switch disconnect, blocking high direct voltage to inside by
The input of protection module, and to implementing to protect for a long time to chip interior low-voltage module under duration high voltage input condition.If
Input voltage after high voltage transient protection location is then controlled not higher than the second activation threshold value of high direct voltage protection location to be opened
It closes and closes, high direct voltage protection location is in circuit without work.High voltage transient protection location is realized to protect with high direct voltage
The cooperation of shield unit both ensure that by the cooperation of high voltage transient protection location and high direct voltage protection location when chip I/O connects
Mouthful instantaneous short circuit arrives the high voltage overshoot concussion that the voltage step can be timely responded to when high pressure, it is ensured that when high voltage overshoot concussion
Very fast decaying to high direct voltage value later can still carry out being effectively protected for a long time.
Fig. 3 is the high voltage transient protection location electrical block diagram that the utility model embodiment provides, as shown in figure 3,
High voltage transient protection unit includes that NMOS tube N1 connect composition Electro-static Driven Comb (Electro-Static with first resistor R1
Discharge, ESD) structure, the first diode D1, the second diode D2, third diode D3, the 4th diode D4, the five or two
Pole pipe D5 series connection, ESD structures are in parallel with the 5th diode D5.
In a specific example, it is based on ESD structure NMOS tube N1 and resistance R1, passes through additional series diode
The voltage clamping of D1-D5 and output, to increase the control to NMOS tube N1.So that the high voltage transient protection location is in addition to can be real
Now outside the ESD functions of script, when high input voltage is higher than the clamp voltage of series diode, triggering NMOS tube N1 is quickly opened,
High input voltage is formed to the discharge path on ground, ensures the voltage of high input voltage being timely limited in preset voltage range,
Realize the functional requirement of high voltage transient protection.
Meanwhile the first activation threshold value to high voltage transient protection location may be implemented by adjusting the number of series diode
Adjustment.
In addition it is also possible to using selected threshold Transient Suppression Diode appropriate (Transient Voltage
Suppressor, TVS) etc. devices realize high voltage transient protection location device function.
Fig. 4 is the high direct voltage protection location electrical block diagram that the utility model embodiment provides, as shown in figure 4,
High direct voltage protection location includes high-pressure detection unit and switch S1.Switch S1 is set to the input terminal of high direct voltage protection location
Between the output end of high direct voltage protection location.
In a specific example, high-pressure detection unit detects the input terminal of high direct voltage protection location, input terminal electricity
Pressure is not less than predetermined threshold value, then is detected as high input voltage, at this point, high-pressure detection unit output control disconnects high direct voltage protection
The switch S1 being series in unit between input and output end, plays the work of isolating chip internal low-voltage module and high input voltage
With.
Input terminal voltage is less than predetermined threshold value, then is detected as normal voltage input, at this point, high-pressure detection unit output enables
Switch S1 conductings so that chip interior low-voltage module is directly connected to protected port.
Fig. 5 is that a kind of chip I/O Interface high pressure overvoltage that the utility model embodiment provides is originally inputted waveform.Such as Fig. 5
It is shown, (start short circuit at 1us in figure) when chip I/O Interface instantaneous short circuit is to high pressure, in interface end by voltage step institute
Stable high direct voltage value is decayed to after the high voltage overshoot concussion of formation is originally inputted waveform figure.
Fig. 6 is a kind of chip I/O Interface output waveform signal after protective device that the utility model embodiment provides
Figure, for based on Fig. 5 institutes high input voltage waveform after protection module to the voltage oscillogram of chip interior.In a specific example
In son, the first activation threshold value of high voltage transient protection location is 32 volts (V), the second activation threshold value of high direct voltage protection location
For 8V.In 1us, there is short circuit in chip interface, and input voltage becomes concussion as shown in Figure 5 from original stable DC voltage
High pressure, before I/O interfaces input high pressure is not below the first activation threshold value of high voltage transient protection location, high voltage transient protection is single
First response time is extremely short, and high voltage transient protection location is triggered work immediately, and high voltage transient protection location shakes high voltage overshoot
Waveform is handled, and is decayed to stable high direct voltage through overshoot concussion, is protected to circuit.In the 1.0us-1.5us times
In section, by concussion high pressure clamper in 5V or so.Within the 1..5us-3.0us periods, since high voltage transient protection location cannot carry out
Prolonged protection high voltage transient protects circuit, in first triggering of the I/O interfaces input high pressure less than high voltage transient protection location
After threshold value, and when not falling below the second activation threshold value of high direct voltage protection location, high direct voltage protection location will be touched
Work is sent out, high voltage transient protection location is worked at the same time with high direct voltage protection location, and voltage is maintained the low electricity of stable direct current
Pressure value.After 3us, high direct voltage protection location for a long time protects chip interior.It will will appear in complete procedure
Whithin a period of time, the case where high voltage transient protection location is triggered with high direct voltage protection location, forms each protection module
Between cooperate, realize protection to chip interior low-voltage module.
Above-described specific implementation mode, to the purpose of this utility model, technical solution and advantageous effect carried out into
One step is described in detail, it should be understood that the foregoing is merely specific embodiment of the present utility model, is not used to limit
Determine the scope of protection of the utility model, within the spirit and principle of the utility model, any modification for being made equally is replaced
It changes, improve, should be included within the scope of protection of this utility model.
Claims (7)
1. a kind of protective device of chip I/O Interface, which is characterized in that the protective device includes：One the first protection location
With at least one second protection location；Wherein, first protection location is high voltage transient protection location, and second protection is single
Member is high direct voltage protection location.
2. the apparatus according to claim 1, which is characterized in that the high voltage transient protection location is provided with the first firing level
Value, when chip port input voltage is higher than the first activation threshold value of the high voltage transient protection location, the high voltage transient is protected
It protects unit and forms discharge circuit over the ground, chip interior module is protected.
3. the apparatus according to claim 1, which is characterized in that the high direct voltage protection location is provided with the second firing level
It is worth, the high-pressure detection unit in the high direct voltage protection location is detected chip port input voltage, passes through to switch and control
Chip interior module is protected in the folding of input circuit processed.
4. according to the device described in claim 1-3 any claims, which is characterized in that the high voltage transient protection location with
The high direct voltage protection location individually protects chip interior module.
5. according to the device described in claim 1-3 any claims, which is characterized in that the high voltage transient protection location with
Chip interior module is protected in the high direct voltage protection location cooperation.
6. according to the device described in claim 1-3 any claims, which is characterized in that the high voltage transient protection location
First activation threshold value is higher than the second activation threshold value of the high direct voltage protection location.
7. according to the device described in claim 1-3 any claims, the high voltage transient protection location shakes high voltage overshoot
Waveform is swung to be handled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721722500.1U CN207732419U (en) | 2017-12-12 | 2017-12-12 | A kind of protective device of chip I/O Interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721722500.1U CN207732419U (en) | 2017-12-12 | 2017-12-12 | A kind of protective device of chip I/O Interface |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207732419U true CN207732419U (en) | 2018-08-14 |
Family
ID=63098198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721722500.1U Active CN207732419U (en) | 2017-12-12 | 2017-12-12 | A kind of protective device of chip I/O Interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207732419U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107834531A (en) * | 2017-12-12 | 2018-03-23 | 英特格灵芯片(天津)有限公司 | A kind of protection device of chip I/O Interface |
-
2017
- 2017-12-12 CN CN201721722500.1U patent/CN207732419U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107834531A (en) * | 2017-12-12 | 2018-03-23 | 英特格灵芯片(天津)有限公司 | A kind of protection device of chip I/O Interface |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104577993B (en) | Input voltage protection circuit of switching power supply | |
| CN107834531A (en) | A kind of protection device of chip I/O Interface | |
| CN102684656B (en) | Gate circuit | |
| CN206117141U (en) | Circuit of striking sparks is prevented in transposition of preventing that possesses overcurrent protection | |
| CN106300314A (en) | The high voltage protective system and method for Type C interface chip CC pin | |
| CN101943148B (en) | Circuit for pulse plasma thruster | |
| CN103166444B (en) | Remote turn-off control signal receiving circuit | |
| CN109728631A (en) | A kind of charging circuit and electronic equipment | |
| CN104768258B (en) | Constant-current driving LED overcurrent-overvoltage protecting circuit | |
| CN107947557B (en) | Soft start circuit for resisting overvoltage and undervoltage surges | |
| CN207732419U (en) | A kind of protective device of chip I/O Interface | |
| CN101615779A (en) | A kind of have error-polarity connection of power supply and charge into the circuit of voltage protection | |
| CN201398073Y (en) | Novel power supply safety protection system | |
| EP3579497B1 (en) | Power sourcing equipment and power over ethernet system | |
| AU2015201523A1 (en) | Residual current protection device | |
| CN204179654U (en) | A kind of lightning protection circuit bearing 6kV thunderbolt by ± 40V signal | |
| CN105336540B (en) | shunt protection circuit for protecting relay contact | |
| CN109449910A (en) | A kind of protection circuit | |
| CN208720450U (en) | A kind of guard time adjusts circuit, PFC current foldback circuit and controller | |
| CN107465173A (en) | A kind of space power system accessory power supply protection circuit | |
| CN209104802U (en) | A kind of protection circuit | |
| CN110190480B (en) | USB data line | |
| CN209282830U (en) | Surge current suppression circuit | |
| CN209748404U (en) | Three-phase rectification protection circuit with input surge current suppression function | |
| CN209217706U (en) | Surge current suppression circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210427 Address after: No.1, floor 4, building 10, No.303, group 3, liangfengding village, Zhengxing Town, Tianfu New District, Chengdu, Sichuan 610000 Patentee after: Sichuan Yichong Technology Co.,Ltd. Address before: Room 2701-1, room 2, No. 19, Xin Huan West Road, Tianjin Development Zone, Binhai New Area, Tianjin Patentee before: INTERNATIONAL GREEN CHIP (TIANJIN) Co.,Ltd. |