CN210668371U

CN210668371U - Semiconductor structure

Info

Publication number: CN210668371U
Application number: CN201921701069.1U
Authority: CN
Inventors: 白杰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-10-11
Filing date: 2019-10-11
Publication date: 2020-06-02
Anticipated expiration: 2029-10-11

Abstract

The embodiment of the utility model provides a relate to memory field of making, disclose a semiconductor structure, include: the array substrate comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises an array area and a peripheral area; the first grid structure is positioned in the substrate of the array region; the second grid structure is positioned on the substrate of the peripheral area and comprises a high-dielectric-constant grid dielectric layer and a metal grid layer which are sequentially stacked; and the capacitor structure is positioned on the first grid structure. By replacing the peripheral region transistor with a metal gate structure with a high dielectric constant, the power consumption of the peripheral region of the DRAM can be reduced; meanwhile, in the manufacturing process, the gate electrode of the peripheral area is replaced by the metal gate electrode structure after the capacitor structure is formed, so that the influence of a high-temperature forming process which can exist when the capacitor structure is formed on the electrical performance of the transistor in the peripheral area can be effectively prevented.

Description

Semiconductor structure

Technical Field

The embodiment of the utility model provides a relate to memory field of making, in particular to semiconductor structure.

Background

Dram (dynamic Random Access memory), which is a dynamic Random Access memory, is the most common system memory. With the continuous development of semiconductor technology, the performance requirements of DRAM are higher and higher.

However, the inventors of the present invention found that: the gate structure of the transistor in the peripheral area in the current DRAM structure adopts a polysilicon gate structure, which has the problems of excessive power consumption in the peripheral area and excessive area in the peripheral area.

SUMMERY OF THE UTILITY MODEL

An object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, in which the gate structure of the transistor in the peripheral region is replaced by a polysilicon gate structure with a metal gate structure having a high dielectric constant in the current DRAM structure, so as to reduce the power consumption of the DRAM peripheral region.

In order to solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the array substrate comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises an array area and a peripheral area; the first grid structure is positioned in the substrate of the array region; the second grid structure is positioned on the substrate of the peripheral area and comprises a high-dielectric-constant grid dielectric layer and a metal grid layer which are sequentially stacked; and the capacitor structure is positioned on the first grid structure.

Compared with the prior art, the embodiment of the invention replaces the polysilicon gate structure of the transistor in the peripheral area in the current DRAM structure with the metal gate structure with high dielectric constant. The power consumption of the peripheral area of the DRAM can be reduced by replacing the polycrystalline silicon grid structure of the transistor in the peripheral area with a metal grid structure with high dielectric constant; meanwhile, in the manufacturing process, the polycrystalline silicon gate structure in the peripheral area is replaced by the metal gate structure with high dielectric constant after the capacitor structure is formed, so that the influence of high-temperature forming process on the electrical performance of the transistor in the peripheral area during the formation of the capacitor structure can be effectively prevented.

In addition, the first gate structure includes a polysilicon gate structure.

In addition, the first gate structure includes a metal gate structure.

In addition, still include: bit line structures located on the substrate between adjacent first gate structures.

In addition, still include: a first interlayer dielectric layer covering the peripheral region and the bit line structure; the first interlayer layer is provided with a capacitor contact window, and the capacitor structure is connected with the first grid structure through the capacitor contact window.

In addition, still include: a third interlayer dielectric layer located on the first interlayer dielectric layer; the third interlayer dielectric layer is provided with a capacitor groove, and the capacitor structure is positioned on the capacitor groove and the top surface of the third interlayer dielectric layer.

In addition, the metal gate layer includes: the first metal gate layer is positioned on the top surface of the high-dielectric-constant gate dielectric layer; the second metal gate layer is positioned on the top surface of the first metal gate layer; and the resistivity of the second metal gate layer is smaller than that of the first metal gate layer.

In addition, the capacitor structure comprises a first electrode plate, a capacitor dielectric layer and a second electrode plate which are sequentially stacked.

In addition, the capacitor structure further comprises a conductive layer, and the conductive layer is located on the top surface of the second electrode plate.

In addition, still include: and the second interlayer dielectric layer covers the peripheral region and the capacitor structure positioned in the array region.

Compared with the prior art, the embodiment of the utility model provides a technical scheme has following advantage: reducing the power consumption of the DRAM peripheral area; the problem that the area of the peripheral area of the DRAM is too large at present is solved; meanwhile, the influence of the high-temperature forming process on the electric performance of the transistor in the peripheral area during the formation of the capacitor structure can be effectively prevented in the manufacturing process.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1-8 are schematic cross-sectional views of steps in a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

fig. 9 is a detailed process of forming a second gate structure in a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

fig. 10 is a schematic view of a semiconductor structure according to an embodiment of the present invention.

Detailed Description

The grid structure of the transistor in the peripheral area in the current DRAM structure adopts a polysilicon grid structure, so that the problem of overlarge power consumption of the peripheral area exists.

If the grid structure of the transistor in the peripheral area in the DRAM structure is improved, the grid structure of the transistor in the peripheral area in the current DRAM structure is replaced by a metal grid structure with high dielectric constant from a polysilicon grid structure, so that the power consumption of the peripheral area of the DRAM can be reduced; meanwhile, in the manufacturing process, the polycrystalline silicon gate structure in the peripheral area is replaced by the metal gate structure with high dielectric constant after the capacitor structure is formed, so that the influence of a high-temperature forming process on the electrical performance of the transistor in the peripheral area during the formation of the capacitor structure can be effectively prevented.

In order to solve the above problem, an embodiment of the present invention provides a semiconductor structure manufacturing method, including: providing a substrate, wherein the substrate comprises an array area and a peripheral area; forming a first gate structure in the substrate of the array region; forming a pseudo gate structure on the surface of the substrate in the peripheral region; forming a capacitor structure on the first gate structure; after the capacitor structure is formed, removing the pseudo gate structure in the peripheral area to form a groove; forming a second gate structure in the groove; the second gate structure comprises a high-dielectric-constant gate dielectric layer and a metal gate layer which are sequentially stacked. Thus, the power consumption of the DRAM peripheral area can be reduced; meanwhile, the influence of the high-temperature forming process which can exist when the capacitor structure is formed on the electrical performance of the transistor in the peripheral area can be effectively prevented in the manufacturing process.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following will explain in detail each embodiment of the present invention with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present invention, and the embodiments may be combined with each other and cited without contradiction.

The first embodiment of the present invention relates to a method for manufacturing a semiconductor structure, and the core of this embodiment lies in improving the gate structure of the transistor in the peripheral region in the DRAM structure, and replacing the gate structure of the transistor in the peripheral region with a metal gate structure having a high dielectric constant by a polysilicon gate structure in the current DRAM structure.

Implementation details of the method for manufacturing a semiconductor structure according to the present embodiment are specifically described below, and the following description is only provided for the sake of understanding, and is not necessary for implementing the present embodiment.

Referring to fig. 1, a substrate 101 is provided, the substrate 101 including an array region 110 and a peripheral region 100.

Wherein the array region 110 is used to fabricate a capacitor structure and includes an array transistor having a first gate structure; the peripheral region 100 is used for manufacturing control circuitry including peripheral transistors having a second gate structure.

Isolation structures are formed in the substrate in the array region 110 and the peripheral region 100, and the isolation structures perform an isolation function. Specifically, in the present embodiment, the isolation structure is a shallow trench isolation trench. It should be noted that the isolation structure is a shallow trench isolation trench, which is only an example of the isolation structure of this embodiment, and is not limited to this, and in other embodiments, the isolation structure may also be flexibly used according to actual needs, which is not an example herein.

Well regions are formed in the substrate 101 adjacent to the isolation trenches 103, and include a first well region 102 and a second well region 112.

Wherein, the first well region 102 is located between the adjacent isolation trenches 103 of the peripheral region 100; the second well region 112 is located between the adjacent isolation trenches 103 of the array region 110. It should be noted that, when the peripheral transistor is an NMOS, the first well region 102 is a P-well; when the peripheral transistor is a PMOS, the first well region 102 is an N-well. Similarly, when the array transistor is an NMOS, the second well region 112 is a P-well; when the array transistor is PMOS, the second well 112 is N-well.

Referring to fig. 2, a dummy gate structure 201 is formed on a surface of the substrate 101 in the peripheral region 100, and a first gate structure 300 is formed in the substrate 101 in the array region 110.

In this embodiment, the dummy gate structures 201 of the peripheral region 100 and the first gate structures 300 of the array region 110 are formed in different process steps.

A dummy Gate structure 201 is formed on the first well region 102 in the peripheral region 100, specifically, the dummy Gate structure 201 is formed by a Gate-first process (Gate-first), after the dummy Gate structure 201 is manufactured, a sidewall 204 is formed on a sidewall of the dummy Gate 201, and doped regions are formed in the substrate 101 at two sides of the dummy Gate structure 201, and are respectively used as a source 202 and a drain 203 of the peripheral transistor.

A first gate structure 300 is formed in the array region 110 over the second well region 112. Specifically, the first gate structure 300 is formed by a buried gate process, and after the first gate structure 300 is manufactured, the source and the drain of the array transistor are formed in the second well region 112.

It should be noted that, in the present embodiment, the dummy gate structure 201 is a polysilicon gate structure, and the first gate structure 300 is a metal gate structure. In other embodiments, the first gate structure may also be a polysilicon gate structure, and accordingly, the dummy gate structure in the peripheral region and the first gate structure in the array region may be formed in the same process step.

The dummy gate structure 201 on the peripheral transistor in the peripheral region 100 is replaced with a second gate structure after a capacitor structure is formed subsequently, so that the width of the dummy gate structure 201 can be determined according to a preset width of the second gate structure to be formed, and the width of the dummy gate structure is the same as the preset width. In the case of implementing the same electrical function, a metal gate structure with a high dielectric constant, i.e., the second gate structure, is used, and the width of the gate structure required is smaller than that of the gate structure when a polysilicon gate structure is used.

As the width of the second gate structure of the peripheral transistor is smaller, the size of the peripheral region 100 thereof may be correspondingly smaller; the area of the array region 110 will be enlarged correspondingly, and the area ratio of the array region 110 to the peripheral region 100 will be larger, so as to improve the utilization rate of the DRAM array region and solve the problem of the overlarge area of the peripheral region in the current DRAM structure.

Referring to fig. 3, a first interlayer dielectric layer 401 is formed on the top surfaces of the peripheral region 100 and the array region 110. In this figure and the subsequent cross-sectional views, the source and drain of the array transistor are not shown. Also, it should be apparent to those skilled in the art that the accompanying drawings merely illustrate structural fabrication of the corresponding parts and are not limiting on the scale of the parts illustrated in the drawings.

In this embodiment, the first interlayer dielectric layer 401 has a single-layer structure. It should be noted that the single-layer structure adopted by the first interlayer dielectric layer 401 in this embodiment is only an example of this embodiment, and is not limited to this embodiment, and in other embodiments, the first interlayer dielectric layer may be set to be a multi-layer structure, and may be flexibly set according to a specific application.

Further comprising: a capacitor contact 307 located within the first interlayer dielectric layer 401. In this embodiment, the capacitor contact 307 may be formed first after the first interlayer dielectric layer 401 is formed, as follows: the first interlayer dielectric layer 401 is disposed at the height of the capacitor contact 307, covering the entire array region 110 and the top surface of the peripheral region 100.

In other embodiments, the capacitor contact window 307 may also be formed after forming the first interlayer dielectric layer 401, by etching the first interlayer dielectric layer 401 to form a capacitor contact via, then filling the capacitor contact via with a conductive material, and then etching the conductive material in the capacitor contact via to make the top surface of the capacitor contact via flush with the top surface of the first interlayer dielectric layer 401, so as to form the capacitor contact window 307.

The bit line structure 301 and the word line structure may also be formed prior to forming the first interlayer dielectric layer 401. Two first gate structures 300 are formed between two adjacent isolation trenches 103 of the second well region 112 as buried word line structures, i.e., gate structures of array transistors, and corresponding sources and drains are formed in the second well region 112; the bit line structure 301 is formed on the second well region 112 between the two buried word line structures, and the capacitor contact window 307 is formed on the second well region 112 between the buried word line structure and the isolation trench 103.

Referring to fig. 4, after forming the first interlayer dielectric layer 401, a third interlayer dielectric layer 402 is also required to be formed on the first interlayer dielectric layer 401 for the subsequent fabrication of the capacitor structure.

Specifically, a third interlayer dielectric layer 402 covering the capacitor contact window 307 and the top surface of the first interlayer dielectric layer 401 is formed on the first interlayer dielectric layer 401, and then the third interlayer dielectric layer 402 is etched to form a capacitor groove, so that the top surface of the capacitor contact window 307 is exposed.

The first interlayer dielectric layer 401 and the third interlayer dielectric layer 402 may be made of the same material or different materials. Referring to fig. 5, after the third interlayer dielectric layer 402 is formed, a capacitor structure 500 is formed in a capacitor recess in the third interlayer dielectric layer 402.

Referring to fig. 5, the capacitor structure 500 is located on the top surface of the capacitor contact window 307, and the capacitor structure 500 is connected to one of the source and the drain of the array transistor through the capacitor contact window 307.

The capacitor structure includes: the capacitor comprises a first electrode plate 501, a capacitor dielectric layer 502 and a second electrode plate 503 which are sequentially stacked.

A first electrode plate 501 is formed on the top surface of the capacitor contact window 307 and the sidewall of the third interlayer dielectric layer 402.

In this embodiment, the material of the first electrode plate 501 is a metal type nitride. It should be understood that the material of the first electrode plate 501 is a metal type nitride, which is only a specific example in this embodiment, and is not limited to this, and any other material that can be used as a capacitor electrode plate can be used as the first electrode in the present invention, such as metals like silver and copper, which are not listed here.

Specifically, in this embodiment, the material of the first electrode plate 501 is titanium nitride. Because titanium nitride has good conductivity and chemical stability, the use of titanium nitride as the first electrode plate 501 can ensure both good electrical properties and stability of the capacitor structure. It should be understood that the material of the first electrode plate 501 is titanium nitride only for illustration of the material of the first electrode plate 501 in this embodiment, and is not limited thereto, and in other embodiments of the present invention, the first electrode plate 501 may be made of other materials such as zirconium nitride, which are not illustrated herein, and may be used flexibly according to actual needs.

A capacitance dielectric layer 502 is formed on the surface of the first electrode plate 501 and the surface of the third interlayer dielectric layer 402.

In this embodiment, the material of the capacitor dielectric layer 502 is an oxide. It should be noted that the material of the capacitor dielectric layer 502 is an oxide, which is merely an example of the material of the capacitor dielectric layer 502 in this embodiment, and is not limited thereto, and in other embodiments of the present invention, the capacitor dielectric layer 502 may be made of other materials, such as silicon nitride, boron nitride, and the like, which are not listed here.

Specifically, in this embodiment, the material of the capacitor dielectric layer 502 is zirconium dioxide. Because zirconium dioxide has a high dielectric constant and good insulation, the capacitance can be increased by using zirconium dioxide as the capacitor dielectric layer 502. In addition, the chemical property of the zirconium dioxide is stable, so that the stability of the capacitor structure can be effectively improved.

A second electrode plate 503 is formed on the surface of the capacitor dielectric layer 502.

The material of the second electrode plate 503 is the same as that of the first electrode plate 501, and is not described one by one here, specifically, in this embodiment, the material of the second electrode plate 503 is titanium nitride.

With continued reference to fig. 5, after capacitor structure 500 is formed, a conductive layer 504 is fabricated over the capacitor structure, conductive layer 504 being used to fabricate electrodes connected to capacitor structure 500.

It should be noted that the capacitor structure 500 is connected to the source or the drain of the array transistor through the capacitor contact window 307, and accordingly, if the capacitor structure 500 is connected to the source of the array transistor, the drain of the array transistor is connected to the bit line structure 301 to form a DRAM structure in which a capacitor is connected to a transistor; if the capacitor structure 500 is connected to the drain of an array transistor, the source of the array transistor is connected to the bit line structure 301 to form a DRAM structure with one transistor connected to a capacitor.

After the capacitor structure 500 is formed, before the dummy gate structure in the peripheral region is removed, a second interlayer dielectric layer 403 covering the capacitor structure 500 is further formed on the peripheral region 100 and the array region 110 to protect the capacitor structure 500. The material of the second interlayer dielectric layer 403 includes borophosphosilicate glass (BPSG).

Referring to fig. 6, the dummy gate structure 201 in the peripheral region 100 is removed to form a groove 601; the method specifically comprises the following steps: and etching to remove the first interlayer dielectric layer 401 positioned at the top of the dummy gate structure 201 and etching to remove the dummy gate structure 201.

Specifically, referring to fig. 6, the second interlayer dielectric layer 403, the third interlayer dielectric layer 402 and the first interlayer dielectric layer on the top of the dummy gate structure 201 are etched away.

And etching to remove the second interlayer dielectric layer 403, the third interlayer dielectric layer 402 and the first interlayer dielectric layer 401 which are positioned at the top of the dummy gate structure 201, wherein the height of the etched interlayer dielectric layer is consistent with that of the dummy gate structure 201.

Referring to fig. 7, the dummy gate structure 201 is etched away to form a recess 601.

Specifically, the method for forming the groove 601 by etching includes: forming a patterned photoresist layer, wherein the patterned photoresist layer covers the second interlayer dielectric layer 403 in the array region 110 and is also located on a part of the substrate in the peripheral region 100; and taking the patterned photoresist layer as a mask, etching and removing the pseudo gate structure 201 in the peripheral region 100 to form a groove 601, and removing the patterned photoresist layer.

Referring to fig. 8, a second gate structure 602 is formed in the recess 601.

Specifically, referring to fig. 9, the process steps of forming the second gate structure 602 in the recess 601 include: forming a high-dielectric-constant gate dielectric layer 801 at the bottom and the side wall of the groove; and forming a metal gate layer on the gate dielectric layer, wherein the metal gate layer fills the groove, and the second gate structure 602 is formed in the groove 601.

In this embodiment, the high-k gate dielectric layer 801 is made of a high-k material, such as Hf, La, Ti, Zr, and other high-k elements or oxides thereof, or Si and N dopants may be used.

Forming a metal gate layer on the high-k gate dielectric layer 801, filling the groove with the metal gate layer, and completing forming the second gate structure 602 in the groove 601, specifically including:

a first metal gate layer 802 is formed on the high-k gate dielectric layer 801.

It should be noted that, if the material is applied to an NMOS transistor, the material of the first metal gate layer 802 is a low work function material; if applied to a PMOS transistor, the material of the first metal gate layer 802 is a high work function material. In this embodiment, taking the PMOS transistor as an example, the material of the first metal gate layer 802 is a high work function material, and in other embodiments, the material may also be applied to an NMOS transistor, and may be flexibly used according to actual needs. The high work function material includes an element having a high work function such as Ti or Ta, or a nitride thereof, and an alloy of Ti, Al, or another element may be used.

A second metal gate layer 803 is formed on the first metal gate layer 802, and the second metal gate layer 803 fills the remaining recess after the first metal gate layer 802 is formed, thereby completing the formation of the second gate structure 602 in the recess 601. The resistivity of the second metal gate layer 803 is smaller than that of the first metal gate layer 801, which is used to reduce the resistance of the entire second gate structure 602, thereby reducing the power consumption of the DRAM peripheral transistors by reducing the resistance.

After the second gate structure is formed, the high-k gate dielectric layer and the metal gate layer on the top of the sidewall spacers 204 and the grooves 601 are etched away.

Specifically, after the second metal gate layer 803 is manufactured, the high-k gate dielectric layer 801, the first metal gate layer 802 and the second metal gate layer 803 on the top surface of the first interlayer dielectric layer 401 are etched away. I.e., replacement of the gate structure of the peripheral transistors in the peripheral region 100 is completed.

Referring to fig. 10, after the replacement of the gate structure of the peripheral transistor in the peripheral region 100 is completed, a second interlayer dielectric layer 403 is formed on the substrate 101 in the peripheral region 100, and the height of the second interlayer dielectric layer 403 formed in the peripheral region is the same as the height of the interlayer dielectric layer 403 formed in the array region 110.

After the second interlayer dielectric layer 403 is formed in the peripheral region 100, the second interlayer dielectric layer 403 and the first interlayer dielectric layer 401 in the peripheral region 100 are etched to form a through hole 901, and the through hole 901 exposes the source 202 and the drain 203 of the peripheral transistor and the second metal gate layer in the second gate structure 602, respectively.

Compared with the prior art, the peripheral transistor applied to the DRAM adopts the second gate structure (i.e., the metal gate structure with a high dielectric constant) and has a lower EOT value compared with the polysilicon gate structure, i.e., the equivalent oxide thickness is thinner, so that the gate capacitance of the transistor can be effectively reduced, and thus a larger state current can be obtained.

Meanwhile, the threshold voltage Vt of the transistor can be improved by the low EOT value, the size of the peripheral transistor is smaller due to the fact that the width of the second grid structure of the peripheral transistor is smaller than that of the polycrystalline silicon grid structure, the area of the array region is larger on the same substrate, the area ratio of the array region to the peripheral region is high, the occupation ratio of the array region in the DRAM is improved, and therefore the using efficiency of the array region of the DRAM is improved.

In addition, compared with the polysilicon gate structure, the gate oxide of the second gate structure is thicker in physical sense, and the leakage current of a gate channel can be effectively reduced.

In addition, the metal gate material of the second gate structure adopts a material with lower resistivity, so that the resistance of the metal gate can be effectively lowered, and the power consumption of the DRAM peripheral transistor is reduced.

The utility model discloses the second Gate structure of first embodiment, after the electric capacity structure is made and is accomplished, etches the polycrystalline silicon Gate structure of peripheral region, and the back Gate technology (Gate-last) that adopts again forms, and the high temperature formation process that can prevent to have when forming the electric capacity structure effectively causes the influence to the electrical property of peripheral region transistor.

The above steps are divided for clarity, and the implementation may be combined into one step or split some steps, and the steps are divided into multiple steps, so long as the steps include the same logical relationship, which is within the protection scope of the present patent; it is within the scope of the patent to add insignificant modifications to the flow or to introduce insignificant design, but not to change the core design of the flow.

The second embodiment of the present invention relates to a semiconductor structure, referring to fig. 10, including:

a substrate 101 including an array region 110 and a peripheral region 100.

The first gate structure 300 is located in the substrate 101 of the array region 110.

And a second gate structure 602 on the substrate 101 in the peripheral region 100.

The capacitor structure 500 is located on the first gate structure 300.

Specifically, the substrate 101 further includes an isolation structure 103, and in this embodiment, the isolation structure 103 includes a shallow trench isolation groove; the substrate 101 further includes a first well region 102 and a second well region 112, the first well region 102 is located between two adjacent isolation structures 103 in the substrate 101 in the peripheral region 100; the second well region 112 is located between two adjacent isolation structures 103 in the substrate 101 of the array region 110.

The first gate structure 300 specifically includes a metal gate structure. It should be noted that, in other embodiments, the first gate structure 300 may adopt a polysilicon gate structure.

In this embodiment, the semiconductor structure further includes a bit line structure 301, and the bit line structure 301 is located on the substrate 101 between the adjacent first gate structures 300. Specifically, the bit line structure 301 is located on the second well region 112 between the adjacent first gate structures 300.

In this embodiment, the semiconductor structure further includes an interlayer dielectric layer. Specifically, the interlayer dielectric layers include a first interlayer dielectric layer 401, a second interlayer dielectric layer 403, and a third interlayer dielectric layer 402.

The first interlayer dielectric layer 401 is used to cover the word line and bit line structures on the array region 110 for forming a DRAM structure with a capacitor connected to an array transistor.

Specifically, a first interlayer dielectric layer 401 covers the peripheral region 100 and the bit line structure 301, a capacitor contact window 307 is formed in the first interlayer dielectric layer 401, the capacitor structure 500 is connected to the first gate structure 300 through the capacitor contact window 307, and specifically, the capacitor structure 500 is connected to a source or a drain of the array transistor formed by the first gate structure 300 through the capacitor contact window 307.

The third interlayer dielectric layer 402 is disposed on the first interlayer dielectric layer 401, a capacitor groove is formed in the third interlayer dielectric layer, and the capacitor structure 500 is disposed in the capacitor groove and on the top surface of the third interlayer dielectric layer 402.

Specifically, the capacitor structure 500 includes a first electrode plate 501, a capacitor dielectric layer 502, and a second electrode plate 503, which are stacked one on another.

There is also a conductive layer 504 on the capacitor structure 500, specifically, the conductive layer 504 is located on the top surface of the second electrode plate 503. For making electrodes connected to the capacitor structure 500.

The second interlayer dielectric layer 403 covers the entire substrate 101, and specifically, the second interlayer dielectric layer 403 covers the peripheral region 100 and the capacitor structure 500 located in the array region 100. For protecting the capacitor structure 500 and the array transistor in the array region 110, and etching vias 901, the vias 901 expose the source and drain of the peripheral transistor and the second metal gate layer 803 in the second gate structure 602, respectively. The material of the second interlayer dielectric layer comprises Boron Phosphorus Silicon Glass (BPSG).

The second gate structure 602 specifically includes: a high-k gate dielectric layer 801 and a metal gate layer.

The metal gate layer specifically includes a first metal gate layer 802 located on the top surface of the high-k gate dielectric layer 801.

A second metal gate layer 803 on the top surface of the first metal gate layer 802; and the resistivity of the second metal gate layer is smaller than that of the first metal gate layer.

The gate structure of the peripheral transistor is made using the second gate structure 602, i.e., a metal gate structure having a high dielectric constant. Compared with a polysilicon gate structure, the metal gate structure with high dielectric constant has a lower EOT value, namely the equivalent oxide thickness is thinner, so that the gate capacitance of the transistor can be effectively reduced, and a larger state current can be obtained. Meanwhile, the threshold voltage Vt of the transistor can be improved by the low EOT value, the size of the peripheral transistor can be made smaller, the area of the array region is larger on the same substrate, the area ratio of the array region to the peripheral region is high, the occupation ratio of the array region in the semiconductor structure is improved, and therefore the use efficiency of the array region of the semiconductor structure is improved.

The gate structure of the peripheral transistor is made using the second gate structure 602, i.e., a metal gate structure having a high dielectric constant. Compared with a polysilicon gate structure, the EOT value of the metal gate structure with the high dielectric constant is lower, namely the equivalent oxide thickness is thinner, so that the gate capacitance of the transistor can be effectively reduced, and larger state current can be obtained. Meanwhile, the threshold voltage Vt of the transistor can be improved by the low EOT value, the size of the peripheral transistor can be made smaller, the area of the array region is larger on the same substrate, the area ratio of the array region to the peripheral region is high, the occupation ratio of the array region in the semiconductor structure is improved, and therefore the use efficiency of the array region of the semiconductor structure is improved.

In addition, compared with the dummy gate structure, the second gate structure has a thicker gate oxide in a physical sense, and can effectively reduce the leakage current of a gate channel.

In addition, the metal gate material of the second gate structure adopts a material with lower resistivity, so that the resistance of the second gate structure can be effectively lowered, and the power consumption of the peripheral area is reduced.

In order to highlight the innovative part of the present invention, a structure that is not so closely related to the solution of the technical problem proposed by the present invention is not introduced in the present embodiment, but this does not indicate that there is no other structure in the present embodiment.

Since the first embodiment corresponds to the present embodiment, the present embodiment can be implemented in cooperation with the first embodiment. The related technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment, and are not described herein again in order to reduce the repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the first embodiment.

It will be understood by those skilled in the art that the foregoing embodiments are specific examples of the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in its practical application.

Claims

1. A semiconductor structure, comprising:

a substrate comprising an array region and a peripheral region;

a first gate structure in the substrate of the array region;

the second gate structure is positioned on the substrate in the peripheral area and comprises a high-dielectric-constant gate dielectric layer and a metal gate layer which are sequentially stacked;

and the capacitor structure is positioned on the first grid structure.

2. The semiconductor structure of claim 1, wherein the first gate structure comprises a polysilicon gate structure.

3. The semiconductor structure of claim 1, wherein the first gate structure comprises a metal gate structure.

4. The semiconductor structure of claim 1, further comprising: bit line structures on the substrate between adjacent first gate structures.

5. The semiconductor structure of claim 4, further comprising:

a first interlayer dielectric layer covering the peripheral region and the bit line structure;

the first interlayer dielectric layer is provided with a capacitor contact window, and the capacitor structure is connected with the first grid structure through the capacitor contact window.

6. The semiconductor structure of claim 5, further comprising:

a third interlayer dielectric layer located on the first interlayer dielectric layer;

the third interlayer dielectric layer is provided with a capacitor groove, and the capacitor structure is positioned in the capacitor groove and on the top surface of the third interlayer dielectric layer.

7. The semiconductor structure of claim 1, wherein the metal gate layer comprises:

the first metal gate layer is positioned on the top surface of the high-dielectric-constant gate dielectric layer;

a second metal gate layer on a top surface of the first metal gate layer;

wherein the resistivity of the second metal gate layer is less than the resistivity of the first metal gate layer.

8. The semiconductor structure of claim 1, wherein the capacitor structure comprises a first electrode plate, a capacitor dielectric layer and a second electrode plate stacked in sequence.

9. The semiconductor structure of claim 8, wherein the capacitor structure further comprises a conductive layer located on a top surface of the second electrode plate.

10. The semiconductor structure of claim 1, further comprising:

and the second interlayer dielectric layer covers the peripheral area and the capacitor structure positioned in the array area.