CN210667752U - Backlight driving circuit and display device - Google Patents
Backlight driving circuit and display device Download PDFInfo
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- CN210667752U CN210667752U CN201922056029.2U CN201922056029U CN210667752U CN 210667752 U CN210667752 U CN 210667752U CN 201922056029 U CN201922056029 U CN 201922056029U CN 210667752 U CN210667752 U CN 210667752U
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Abstract
The utility model discloses a drive circuit and liquid crystal display device are shaded, the drive circuit is shaded includes: the time sequence controller is used for compensating the first pulse width modulation signal input from the outside according to the compensation lookup table so as to generate a second pulse width modulation signal; and a backlight driver connected to the backlight unit and the timing controller, and supplying a driving current to the backlight unit according to the second pulse width modulation signal to control the brightness of the backlight unit, wherein the compensation look-up table includes a plurality of compensation coefficients, each of the plurality of compensation coefficients corresponds to compensation of the first pulse width modulation signal of a different first duty ratio. The dimming linearity of the display panel can be improved in a balanced manner when the duty ratio of the PWM signal is low, and the image display quality of the display panel is further enhanced.
Description
Technical Field
The utility model relates to a show technical field, concretely relates to drive circuit and display device are shaded.
Background
Liquid crystal display devices have the advantages of being light, thin, energy-saving, low in power consumption and the like, and have been widely used in electronic devices such as televisions, computers, mobile phones, digital cameras and the like.
The liquid crystal has anisotropic characteristics, and the liquid crystal display device displays an image through a pixel matrix using electrical and optical characteristics of the liquid crystal. Each pixel of the liquid crystal display device realizes gray scale display by adjusting an optical projection ratio with respect to a polarizing plate according to a change in a data signal using a liquid crystal alignment direction.
Referring to the following table 1, a relationship table between a duty ratio of a PWM (Pulse Width Modulation) signal and a theoretical value and an actual measured value of a panel luminance in a conventional display device is shown:
| theoretical duty cycle | Theoretical brightness | Measured brightness | Measured current | Actual duty cycle |
| 1.70％ | 5.61 | 2.93 | 1.2 | 1.60％ |
| 3.30％ | 10.89 | 9.66 | 2.4 | 3.20％ |
| 6.70％ | 22.11 | 19.55 | 5 | 6.70％ |
| 16.70％ | 55.11 | 55.04 | 12.6 | 16.80％ |
| 33.30％ | 109.89 | 113.2 | 25.1 | 33.50％ |
| 66.70％ | 220.11 | 222.6 | 50.2 | 66.90％ |
| 100.00％ | 330 | 330.3 | 75 | 100.00％ |
Referring to fig. 1, fig. 1 is a graph illustrating a driving current and a luminous intensity of a liquid crystal in a conventional liquid crystal display device. As can be understood from table 1 and fig. 1, in the DC dimming (i.e., current dimming) mode, when the duty ratio of the PWM signal is particularly low, although the dimming accuracy of the current and the duty ratio of the PWM signal are substantially linear, the duty ratio of the PWM signal and the panel brightness of the system are not linear when the duty ratio of the PWM signal is particularly low due to the non-linearity of the Light-to-electrical conversion efficiency of the LED (Light emitting diode) at low current.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a drive circuit and liquid crystal display device are shaded can improve display panel's the linearity of adjusting luminance when low PWM signal duty cycle balancedly, and then reinforcing display panel's picture display quality.
According to the utility model provides a pair of drive circuit is shaded, include: the time sequence controller is used for compensating the first pulse width modulation signal input from the outside according to the compensation lookup table so as to generate a second pulse width modulation signal; and a backlight driver connected to the backlight unit and the timing controller, and supplying a driving current to the backlight unit according to the second pulse width modulation signal to control the brightness of the backlight unit, wherein the compensation look-up table includes a plurality of compensation coefficients, each of the plurality of compensation coefficients corresponds to compensation of the first pulse width modulation signal of a different first duty ratio.
Preferably, the timing controller includes: a signal detector for detecting a first duty cycle of the first pulse width modulated signal; the coefficient register is connected with the signal detector and used for storing the compensation coefficient, receiving and identifying the first duty ratio and outputting different compensation coefficients according to the identification result; and the signal modulator is connected with the signal detector and the coefficient register, respectively receives the first duty ratio and the compensation coefficient, compensates the first duty ratio according to the compensation coefficient to generate a second duty ratio, and generates a second pulse width modulation signal according to the second duty ratio.
Preferably, the timing controller further includes: and the signal comparator is connected between the signal detector and the coefficient register and used for comparing the first duty ratio with a preset value and outputting one of a first control signal or a second control signal to the coefficient register according to a comparison result, wherein when the first duty ratio is smaller than or equal to the preset value, the first control signal is output, the first control signal controls the coefficient register to identify the first duty ratio and output different compensation coefficients according to the first duty ratio, when the first duty ratio is larger than the preset value, the second control signal controls the coefficient register to directly output the compensation coefficient with a fixed value.
Preferably, the timing controller includes a memory in which an encoding program for compensating the externally input first pulse width modulation signal according to the compensation look-up table is stored, and a processor which runs the encoding program to compensate the first pulse width modulation signal to generate the second pulse width modulation signal.
Preferably, the second duty cycle of the second pulse width modulated signal is equal to the first duty cycle of the first pulse width modulated signal multiplied by the compensation factor.
Preferably, when the first duty ratio of the first pwm signal is greater than a preset value, the compensation coefficients are all 1, and when the first duty ratio of the first pwm signal is less than or equal to the preset value, the compensation coefficients are greater than 1, and the compensation coefficients corresponding to different first duty ratios are different.
Preferably, the backlight driver includes: the backlight driving chip is used for receiving the compensated second pulse width modulation signal and the plurality of frequency band signals and generating a switching signal according to the second pulse width modulation signal and the plurality of frequency band signals; and the backlight driving circuit is connected with the backlight driving chip and used for receiving the driving voltage and the switching signal and generating a driving current according to the driving voltage and the switching signal so as to control the brightness of the backlight unit.
According to the utility model provides a pair of liquid crystal display device, include: a display panel and a backlight unit for providing backlight to the display panel; and the backlight driving circuit is connected with the backlight unit and provides driving current for the backlight unit so as to control the brightness of the backlight unit.
Preferably, the display device further comprises a driving circuit connected to the display panel for driving the display panel according to the timing signal and the gray scale driving signal.
Preferably, the display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of pixel units at intersections thereof, and the driving circuit includes: the grid driver is connected with the plurality of scanning lines and used for sequentially scanning the plurality of scanning lines according to the time sequence signal; and the source driver is connected with the data lines and used for providing gray scale voltages to the pixel units through the data lines according to the gray scale driving signals.
The utility model has the advantages that: the utility model discloses a compensation look-up table carries out the compensation of different compensation coefficients to the first pulse width modulation signal of different first duty cycles, can improve display panel's the linearity of adjusting luminance when low PWM signal duty cycle, reinforcing display panel's picture display quality.
The first duty ratio of each first pulse width modulation signal is identified one by one to obtain a corresponding compensation coefficient, so that the compensation process is organized, and the accuracy of the compensation result is improved.
Before the first duty ratio of the first pulse width modulation signal is identified, the first duty ratio is compared with a preset value, and only the first pulse width modulation signal with the first duty ratio smaller than or equal to the preset value is identified, so that the compensation speed is improved, and the power consumption is reduced to a certain extent.
The compensation of the first pulse width modulation signal is carried out through a coding program, so that unnecessary circuit design is avoided, and the design cost is saved.
And the first duty ratio of the first pulse width modulation signal is multiplied by the compensation coefficient to directly obtain the second duty ratio, so that the complexity of data processing in compensation is optimized, and the compensation efficiency is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a graph showing a driving current and a luminous intensity of liquid crystal in a conventional liquid crystal display device;
fig. 2 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first embodiment of the timing controller of fig. 2;
fig. 4 is a schematic structural diagram illustrating a second embodiment of the timing controller of fig. 2;
fig. 5 is a circuit diagram of a backlight driver according to an embodiment of the present invention;
fig. 6 shows a modulation schematic diagram of a pulse width modulation signal according to an embodiment of the present invention.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 2 shows a schematic structural diagram of a liquid crystal display device according to an embodiment of the present invention, fig. 3 shows a schematic structural diagram of a first implementation manner of the timing controller in fig. 2, fig. 4 shows a schematic structural diagram of a second implementation manner of the timing controller in fig. 2, and fig. 5 shows a circuit structure diagram of a backlight driver according to an embodiment of the present invention.
As shown in fig. 2, in the present embodiment, the liquid crystal display device 2000 includes a display panel 2100, a driving circuit 2200, a backlight unit 2400, and a backlight driving circuit 2300.
The display panel 2100 includes a plurality of scan lines and a plurality of data lines, and a plurality of pixel units at intersections thereof, each including a thin film transistor and a pixel electrode, respectively. The grid electrodes of the thin film transistors of the pixel units positioned on the same row are connected to the same scanning line, and the source electrodes of the thin film transistors of the pixel units positioned on the same column are connected to the same data line.
The driving circuit 2200 includes a source driver 2210 and a gate driver 2220.
The source driver 2210 is connected to a plurality of data lines for applying gray scale voltages corresponding to the gray scale driving signals to the corresponding thin film transistors via the data lines.
The gate driver 2220 is connected to the plurality of scan lines, and is configured to provide gate signals for sequentially scanning the plurality of scan lines in each frame period to gate the corresponding tfts.
The backlight driving circuit 2300 is connected to the backlight unit 2400, and is configured to supply a driving current to the backlight unit 2400 to control the luminance of the backlight unit 2400. The backlight driving circuit 2300 includes a timing controller 2310 and a backlight driver 2320.
In one aspect, the timing controller 2310 is configured to obtain timing signals and gray scale driving signals of each pixel unit according to received image data, and provide the timing signals and the gray scale driving signals to the driving circuit 2200.
Further, the timing controller 2310 is connected to an external host 3000, and the host 3000 scales image data input from an external data source according to the resolution of the display panel and supplies the image data to the timing controller 2310 together with a plurality of sync signals. The plurality of synchronization signals include at least a dot clock and a data enable signal, and further include a horizontal synchronization signal and a vertical synchronization signal.
The timing controller 2310 corrects image data input from the host 3000 using various data processing methods for improving image quality and reducing power consumption, and supplies gray scale driving signals to the source driver 2210.
In addition, the timing controller 2310 is also used to generate timing signals for controlling the timing of the source driver 2210 and the gate driver 2220 according to a plurality of synchronization signals input from the host 3000. The timing signals include, for example, a source start pulse and a source sampling pulse for controlling latching of data signals of the source driver 2210, a polarity control signal for controlling polarity of the data signals, an enable signal for controlling an output period of the data signals, and the like. The timing signals further include a start pulse signal and a shift clock for controlling gate signal scanning of the gate driver 2220, an enable signal for controlling a gate signal output period, and the like.
On the other hand, the main unit 3000 also supplies the timing controller 2310 with a first pulse width modulation signal PWM1 having a duty ratio that is previously set according to a design value or set according to user brightness adjustment. The timing controller 2310 derives the second pulse width modulation signal PWM2 in response to the first duty ratio D1 of the first pulse width modulation signal PWM1 and provides the second pulse width modulation signal PWM2 to the backlight driver 2320, and the backlight driver 2320 drives the backlight unit 2400 and controls the luminance of the backlight unit 2400 according to the second pulse width modulation signal PWM 2.
Further, in conjunction with fig. 3 and 4, the timing controller 2310 is configured to compensate the externally input first pwm signal according to a compensation lookup table to generate a second pwm signal, where the compensation lookup table includes a plurality of compensation coefficients, and each of the plurality of compensation coefficients corresponds to compensation of the first pwm signal with a different first duty ratio.
Specifically, the compensation look-up table may refer to the example shown in table 1, where table 1 shows compensation coefficients and compensation results corresponding to the first pwm signals with different duty ratios in this embodiment.
| Duty cycle D1 of PWM1 | Compensation factor a | Duty cycle D of PWM22 |
| 0.1％ | 1.3 | D1*1.3 |
| 0.4％ | 1.2 | D1*1.2 |
| ... | ... | ... |
| 3％ | 1.05 | D1*1.05 |
| >3％ | 1 | D1*1 |
As can be known from table 1, when the first duty ratio D1 of the first PWM signal PWM1 is greater than the predetermined value, for example, 3%, the compensation coefficient a is 1. When the first duty ratio D1 of the first PWM signal PWM1 is less than or equal to the preset value, such as 3%, the compensation coefficient a is greater than 1, and the compensation coefficients a corresponding to different first duty ratios D1 are different, and the closer the first duty ratio D1 is to the preset value, such as 3%, the smaller the corresponding compensation coefficient a is.
Further, the compensation coefficient a in table 1 may be debugged according to actual test brightness at a debugging stage of the product through a register, for example, theoretical backlight brightness in a nonlinear range is predicted according to backlight brightness in a linear range (that is, a linear relationship between a duty ratio/current and brightness), a theoretical duty ratio of a pulse width modulation signal required for realizing the theoretical backlight brightness is tested, and a multiple or difference between the theoretical duty ratio and the actual duty ratio is calculated, so as to obtain the compensation coefficient a.
Accordingly, the compensation coefficient a may also be obtained in other manners, which is not limited herein.
In the present invention, the timing controller 2310 can compensate the first duty ratio D1 of the first pulse width modulation signal PWM1 through hardware or software, and the following description is made through a specific embodiment.
Example one
As shown in fig. 3, the timing controller 2310 includes a signal detector 2311, a coefficient register 2312, and a signal modulator 2313.
Here, the signal detector 2311 samples and counts the first pulse width modulation signal PWM1 to detect the first duty ratio D1 of the first pulse width modulation signal PWM 1.
Further, the signal detector 2311 detects a first switching period and a first on time of the externally input first pulse width modulation signal PWM1, and then determines the first duty ratio D1 of the first pulse width modulation signal PWM1 according to the first switching period and the first on time.
Further, the signal detector 2311 detects a rising edge of the first PWM signal PWM1 and starts timing, a time from a first rising edge to a first falling edge is denoted as a first on time T1, a time from the first rising edge to a second rising edge is denoted as a first switching period T1, and then the first duty ratio D1 of the first PWM signal PWM1 is T1/T1.
The coefficient register 2312 is used for storing a compensation coefficient a, and the coefficient register 2312 is connected to the signal detector 2311, receives the first duty ratio D1 of the first pulse width modulation signal PWM1, and compares the first duty ratio D1 of the first pulse width modulation signal PWM1 with a preset duty ratio to output a different compensation coefficient a according to the comparison result.
In one possible embodiment, when the first duty ratio D1 of the first PWM signal PWM1 is less than or equal to a preset duty ratio, such as 3%, the coefficient register 2312 outputs different compensation coefficients a according to a specific value or range of values of the first duty ratio D1. For example, when the first duty ratio D1 is within 0.1% -0.3%, the coefficient register 2312 outputs the compensation coefficient a of 1.3; when the first duty ratio D1 is within 0.3% -0.5%, the coefficient register 2312 outputs a compensation coefficient a of 1.2; by analogy, when the first duty ratio D1 is within 0.3%, the coefficient register 2312 outputs the compensation coefficient a of 1.05.
When the first duty ratio D1 of the first pulse width modulation signal PWM1 is greater than the preset duty ratio, such as 3%, the coefficient register 2312 outputs the compensation coefficient a of 1, that is, when the first duty ratio D1 of the first pulse width modulation signal PWM1 is greater than the preset duty ratio, such as 3%, the duty ratio of the first pulse width modulation signal PWM1 at this time is not required to be adjusted.
It should be noted that the above-mentioned values are only exemplary, and the value of the compensation coefficient a stored and output by the coefficient register 2312 may be changed according to specific situations in practical design.
The signal modulator 2313 is respectively connected to the coefficient register 2312 and the signal detector 2311 to respectively receive the first duty ratio D1 and the compensation coefficient a, compensate the first duty ratio D1 according to the compensation coefficient a to generate a second duty ratio D2, and generate a second pulse width modulation signal PWM2 according to the second duty ratio D2.
Preferably, the compensation of the first duty ratio D1 according to the compensation coefficient a to generate the second duty ratio D2 is to multiply the first duty ratio D1 of the first pulse width modulation signal PWM1 by the compensation coefficient, and the product is used as the second duty ratio D2. The complexity of data processing during compensation is optimized, and the compensation efficiency is improved.
Further, the signal modulator 2313 determines a second switching period T2 and a second on-time T2 according to the second duty ratio D2, and finally generates the second pulse-width modulation signal PWM2 according to the second switching period T2 and the second on-time T2.
Preferably, the timing controller 2310 further includes a signal comparator 2314, and the signal comparator 2314 is connected between the signal detector 2311 and the coefficient register 2312, and is configured to compare the first duty ratio D1 of the first pulse width modulation signal PWM1 with a preset value, and output one of the first control signal and the second control signal to the coefficient register 2312 according to the comparison result. Before the first duty ratio of the first pulse width modulation signal is identified, the first duty ratio is compared with a preset value, and only the first pulse width modulation signal with the first duty ratio smaller than or equal to the preset value is identified, so that the compensation speed is improved, and the power consumption is reduced to a certain extent.
Further, when the first duty ratio is less than or equal to the preset value, a first control signal is output, and the first control signal controls the coefficient register 2312 to recognize the first duty ratio D1 and output a different compensation coefficient a according to the first duty ratio. And when the first duty ratio D1 is greater than the preset value, outputting a second control signal which controls the coefficient register to directly output the compensation coefficient a with a fixed value.
It should be noted that the structure of the timing controller 2310 is only a preferred embodiment of the present invention, and accordingly, those skilled in the art should be able to contact other structures having the same or similar principles as the above structure without creative efforts, and the present invention is also within the scope of the present invention.
Example two
As shown in fig. 4, in the present embodiment, the timing controller 2310 includes a memory 2315 and a processor 2316, the memory 2315 stores a coding program for compensating the externally input first PWM signal according to the compensation look-up table, the coding program is executed in the processor 2316 to perform identification, comparison and compensation (different assignments are performed in the program according to the comparison result) of the first PWM signal PWM1 at the first duty ratio D1, and finally output the second PWM signal PWM2 with the second duty ratio D2.
In this embodiment, the compensation of the first pwm signal is performed by the encoding program, so that unnecessary circuit design is avoided and design cost is saved.
In summary, by performing compensation of different values on different duty ratios of the first pulse width modulation signal PWM1 smaller than the preset duty ratio, the dimming linearity of the display panel at the time of low PWM signal duty ratio can be improved in a balanced manner, and the image display quality of the display panel can be enhanced.
As shown in fig. 5, in the present embodiment, the backlight driver 2320 includes a backlight driving chip 2321 and a backlight driving circuit 2322.
The backlight driving chip 2321 is configured to receive the compensated second pulse width modulation signal PWM2 and the plurality of frequency band signals FB (1-n), and further output a switching signal SW and an overvoltage protection signal OVP required for driving the backlight unit according to the second pulse width modulation signal PWM2 and the plurality of frequency band signals FB (1-n).
Further, the backlight driving chip 2321 is connected with a fourth resistor R4 and a ninth capacitor C9, and the backlight driving chip 2321 receives the second pulse width modulation signal PWM2 through the fourth resistor R4 to reduce the current; the ninth capacitor C9 is connected between the receiving end of the band signal and the reference ground for filtering.
Accordingly, a filter capacitor may be connected between each frequency band signal receiving end of the backlight driving chip 2321 and the reference ground.
It should be noted that the backlight driving chip 2321 depicted in fig. 5 is the simplest structure, and is only used to illustrate the function of the backlight driving chip 2321 in the backlight driver 2320, in an actual circuit design, a specific connection design of each pin of the backlight driving chip 2321 should be performed according to conventional knowledge and a circuit structure, and this embodiment is not limited in this embodiment.
Further, the backlight driving chip 2321 receives the compensated second pulse width modulation signal PWM2, and in an alternative embodiment, the second pulse width modulation signal PWM2 is outputted by the timing controller (i.e. the compensation for the first pulse width modulation signal PWM1 is located in the timing controller). In another alternative embodiment, the second PWM signal PWM2 is compensated by the PWM signal outputted from the timing controller (i.e. the compensation for the first PWM signal PWM1 is located outside the timing controller and in front of the LED driving terminal).
The backlight driving circuit 2322 is connected to the backlight driving chip 2321, receives the driving voltage V _ LED, the switching signal SW and the overvoltage protection signal OVP, and provides a driving current to the backlight unit 2400 according to the driving voltage V _ LED and the switching signal SW, so as to control the brightness of the backlight unit 2400.
In this embodiment, the backlight driving circuit 2322 includes a first resistor R1, a second resistor R2, a third resistor R3, a first inductor L1, a first diode D1, and a plurality of capacitors (e.g., C1 to C8). The first resistor R1, the first inductor L1, the first diode D1 and the second resistor R2 are sequentially connected in series between the receiving terminal of the driving voltage V _ LED and the output terminal VOUT, partial capacitors such as C1 to C4 are connected in parallel between a connection node of the first resistor R1 and the first inductor L1 and the ground, and partial capacitors such as C5 to C8 are connected in parallel between the cathode of the first diode D1 and the ground. The anode of the first diode D1 receives the switching signal SW, while the cathode of the first diode D1 receives the overvoltage protection signal OVP through the third resistor R3.
In this embodiment, the combination of a plurality of capacitors (e.g., C1 to C8) is used to filter the driving voltage V _ LED, but the number of capacitors connected in parallel is not limited.
In one possible embodiment, the anode of the first diode D1 is grounded via a switch tube, and the control terminal of the switch tube receives the switch signal SW.
The output path of the driving voltage V _ LED is controlled by the switching signal obtained according to the second pulse width modulation signal PWM2, so that the magnitude of the driving current output by the output end VOUT can be changed, and the adjustment of the light emitting brightness of the LED lamp string in the backlight unit is realized.
Further, the over-voltage protection signal OVP can provide over-voltage protection for the backlight driving circuit 2322.
It is understood that the above-mentioned pair of backlight driving circuits 2322 is only a preferred circuit structure of this embodiment, and in other possible embodiments of the present invention, the same functions can be realized by other circuit structures.
Referring to fig. 2, the backlight unit 2400 employs a plurality of LEDs as light sources.
In one embodiment, the backlight unit 2400 is a direct type backlight. The backlight unit 2400 is disposed opposite to the display panel 2100, and when the liquid crystal display device 2000 is used, the backlight sequentially passes through the display panel 2100 to reach the eyes of the viewer.
In another embodiment, the backlight unit 2400 is a side-in backlight. The backlight unit 2400 is positioned on the upper and lower sides or the left and right sides of the display panel 2100, and changes the optical path of the backlight through the light guide plate to sequentially pass through the display panel to the eyes of the viewer.
Fig. 6 shows a modulation schematic diagram of a pulse width modulation signal according to an embodiment of the present invention.
As shown in fig. 6, in the embodiment, when the duty ratio of the first PWM signal PWM1 is compensated, the upper computer generates the first PWM signal PWM1(S01), then identifies the first duty ratio D1 of the first PWM signal PWM1, compares the first duty ratio D1 with a preset value (S02), and generates the second PWM signal PWM2 with a different second duty ratio D2 according to the comparison result.
Further, when the first duty ratio D1 is greater than the preset value, the first duty ratio D1 of the first pulse width modulation signal PWM1 is not compensated, and the timing controller 2310 generates the second pulse width adjustment signal PWM2 having the same duty ratio as the first pulse width modulation signal PWM1 (S03).
When the first duty ratio D1 is less than or equal to the preset value, the timing controller 2310 compensates the first duty ratio D1 of the first pulse width modulation signal PWM1 according to the compensation look-up table to generate the second pulse width modulation signal PWM2 (S04).
The utility model discloses a compensation look-up table carries out the compensation of different compensation coefficients to the first pulse width modulation signal of different first duty cycles, can improve display panel's the linearity of adjusting luminance when low PWM signal duty cycle, reinforcing display panel's picture display quality.
The first duty ratio of each first pulse width modulation signal is identified one by one to obtain a corresponding compensation coefficient, so that the compensation process is organized, and the accuracy of the compensation result is improved.
Before the first duty ratio of the first pulse width modulation signal is identified, the first duty ratio is compared with a preset value, and only the first pulse width modulation signal with the first duty ratio smaller than or equal to the preset value is identified, so that the compensation speed is improved, and the power consumption is reduced to a certain extent.
The compensation of the first pulse width modulation signal is carried out through a coding program, so that unnecessary circuit design is avoided, and the design cost is saved.
And the first duty ratio of the first pulse width modulation signal is multiplied by the compensation coefficient to directly obtain the second duty ratio, so that the complexity of data processing in compensation is optimized, and the compensation efficiency is improved.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious changes and modifications may be made without departing from the scope of the present invention.
Claims (10)
1. A backlight driving circuit, comprising:
the time sequence controller is used for compensating the first pulse width modulation signal input from the outside according to the compensation lookup table so as to generate a second pulse width modulation signal; and
a backlight driver connected to the backlight unit and the timing controller, for supplying a driving current to the backlight unit according to the second pulse width modulation signal to control the brightness of the backlight unit,
wherein the compensation look-up table comprises a plurality of compensation coefficients, each compensation coefficient of the plurality of compensation coefficients corresponding to a compensation of the first pulse width modulated signal for a different first duty cycle.
2. The backlight driving circuit according to claim 1, wherein the timing controller comprises:
a signal detector for detecting a first duty cycle of the first pulse width modulated signal;
the coefficient register is connected with the signal detector and used for storing a compensation coefficient, receiving and identifying the first duty ratio and outputting different compensation coefficients according to an identification result;
and the signal modulator is connected with the signal detector and the coefficient register, respectively receives the first duty ratio and the compensation coefficient, compensates the first duty ratio according to the compensation coefficient to generate a second duty ratio, and generates the second pulse width modulation signal according to the second duty ratio.
3. The backlight driving circuit according to claim 2, wherein the timing controller further comprises:
a signal comparator connected between the signal detector and the coefficient register for comparing the first duty ratio with a preset value and outputting one of a first control signal or a second control signal to the coefficient register according to the comparison result,
wherein a first control signal is output when the first duty ratio is less than or equal to the preset value, the first control signal controls the coefficient register to identify the first duty ratio and output different compensation coefficients according to the first duty ratio,
and outputting a second control signal when the first duty ratio is larger than the preset value, wherein the second control signal controls the coefficient register to directly output a compensation coefficient with a fixed numerical value.
4. The backlight driving circuit according to claim 1, wherein the timing controller includes a memory and a processor,
the memory stores a coding program for compensating the externally input first pulse width modulation signal according to the compensation lookup table;
the processor runs the encoding program to compensate the first pulse width modulation signal to generate the second pulse width modulation signal.
5. The backlight driving circuit according to claim 3, wherein the second duty cycle of the second pulse width modulation signal is equal to the first duty cycle of the first pulse width modulation signal multiplied by the compensation factor.
6. The backlight driving circuit according to claim 5, wherein the compensation factors are all 1 when the first duty ratio of the first pulse width modulation signal is greater than the preset value,
when the first duty ratio of the first pulse width modulation signal is smaller than or equal to the preset value, the compensation coefficient is larger than 1, and the compensation coefficients corresponding to different first duty ratios are different.
7. The backlight driver circuit according to claim 1, wherein the backlight driver comprises:
the backlight driving chip is used for receiving the compensated second pulse width modulation signal and a plurality of frequency band signals and generating a switching signal according to the second pulse width modulation signal and the plurality of frequency band signals;
and the backlight driving circuit is connected with the backlight driving chip and used for receiving driving voltage and the switching signal and generating driving current according to the driving voltage and the switching signal so as to control the brightness of the backlight unit.
8. A display device, comprising:
a display panel and a backlight unit for providing backlight to the display panel; and
the backlight driving circuit of any of claims 1-7, connected to the backlight unit to provide a driving current to the backlight unit to control the brightness of the backlight unit.
9. The display device according to claim 8, further comprising a driving circuit connected to the display panel for driving the display panel according to a timing signal and a gray scale driving signal.
10. The display device according to claim 9, wherein the display panel includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixel units at intersections thereof, and wherein the driving circuit includes:
the grid driver is connected with the plurality of scanning lines and used for sequentially scanning the plurality of scanning lines according to the time sequence signals; and
and the source electrode driver is connected with the data lines and used for providing gray scale voltages to the pixel units through the data lines according to the gray scale driving signals.
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| CN201922056029.2U CN210667752U (en) | 2019-11-25 | 2019-11-25 | Backlight driving circuit and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112581916A (en) * | 2020-12-14 | 2021-03-30 | 京东方科技集团股份有限公司 | Dimming circuit of backlight module, dimming method of dimming circuit and display device |
| CN113539150A (en) * | 2021-06-09 | 2021-10-22 | 重庆两江联创电子有限公司 | Backlight brightness control circuit and liquid crystal display screen detection equipment |
| CN114120880A (en) * | 2021-12-10 | 2022-03-01 | 武汉华星光电半导体显示技术有限公司 | Display panel and control method thereof |
| CN114677981A (en) * | 2022-03-28 | 2022-06-28 | Tcl华星光电技术有限公司 | Charging compensation method and charging compensation device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112581916A (en) * | 2020-12-14 | 2021-03-30 | 京东方科技集团股份有限公司 | Dimming circuit of backlight module, dimming method of dimming circuit and display device |
| CN112581916B (en) * | 2020-12-14 | 2022-04-26 | 京东方科技集团股份有限公司 | Dimming circuit of backlight module, dimming method of dimming circuit and display device |
| CN113539150A (en) * | 2021-06-09 | 2021-10-22 | 重庆两江联创电子有限公司 | Backlight brightness control circuit and liquid crystal display screen detection equipment |
| CN114120880A (en) * | 2021-12-10 | 2022-03-01 | 武汉华星光电半导体显示技术有限公司 | Display panel and control method thereof |
| CN114120880B (en) * | 2021-12-10 | 2023-06-27 | 武汉华星光电半导体显示技术有限公司 | Display panel and control method thereof |
| CN114677981A (en) * | 2022-03-28 | 2022-06-28 | Tcl华星光电技术有限公司 | Charging compensation method and charging compensation device |
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