CN210666510U

CN210666510U - CMOS buffer for buffering voltage close to ground

Info

Publication number: CN210666510U
Application number: CN201922136819.1U
Authority: CN
Inventors: 白春风; 王洋; 汤雁婷; 乔东海
Original assignee: Suzhou University
Current assignee: Suzhou University
Priority date: 2019-12-03
Filing date: 2019-12-03
Publication date: 2020-06-02
Anticipated expiration: 2029-12-03

Abstract

The utility model discloses a buffer CMOS buffer of nearly ground voltage, it includes operation transconductance amplifier OTA to and the super source follower who comprises biasing constant current source IB1, biasing constant current source IB2, NMOS pipe N1, NMOS pipe N2, NMOS pipe N3. The utility model discloses a buffer CMOS buffer of nearly ground voltage because OTA and super source follower all are in closed loop, the grid source direct current voltage who has overcome the source follower shifts the shortcoming that changes along with PVT change, simultaneously, even if input voltage is very close to ground voltage, also can maintain higher loop gain. Sufficient loop gain ensures that the output voltage of the buffer is approximately equal to the input voltage, and has certain driving capability, namely, the buffer to the near-ground voltage is accurately realized.

Description

CMOS buffer for buffering voltage close to ground

Technical Field

The utility model relates to an integrated circuit technical field, in particular to CMOS buffer of buffering nearly ground voltage.

Background

As shown in fig. 1, in a voltage buffer structure (implemented based on an OTA) commonly used in an integrated circuit, a non-inverting input terminal of an Operational Transconductance Amplifier (OTA) is used as a voltage input terminal, and an inverting terminal of the OTA is connected with an output terminal to be used as a voltage output terminal. Since the voltage gain (a) of the OTA is very high, the output voltage versus input voltage is:

the relative error of its buffered output is equal to 1/(1+ a), so the higher the gain of the OTA, the smaller the error of the buffer. From the port impedance point of view, the input impedance of the voltage buffer shown in fig. 1 is equal to that of the OTA, which is very high in CMOS processes; its output impedance is equal to the OTA itself output impedance divided by (1+ a), a very low value. Therefore, the performance of such a voltage buffer depends on the gain (a) of the OTA.

As shown in fig. 2, which is a circuit structure diagram of a common OTA in a CMOS process, an input stage of the PMOS folded cascode structure has good adaptability to a case of inputting a lower voltage, but when the input voltage is a lower voltage close to ground, an NMOS transistor (N6) of an output terminal connected to an inverting input terminal of the OTA is in a linear region, so that a transconductance value thereof is very low, and further, a voltage gain (a) of the OTA becomes very low, and thus, voltage buffering can not be accurately implemented.

As shown in fig. 3, another commonly used voltage buffer structure (implemented based on super source follower) has very high input impedance and very low output impedance. Such a voltage buffer can output a voltage close to the ground because, even if the NMOS transistor N2 enters the linear region, the output voltage can normally follow the input voltage as long as the constant bias current source IB normally operates. However, the super source follower can only realize small signal following, a voltage difference of a gate source Voltage (VGS) exists between an input voltage and an output voltage, and the voltage difference varies with process, voltage and temperature (PVT) variations in the integrated circuit. Therefore, the voltage buffer based on the source follower cannot accurately buffer the dc voltage because of poor PVT stability of its gate-source voltage.

SUMMERY OF THE UTILITY MODEL

To overcome the disadvantages of the prior art, the present invention provides a CMOS buffer capable of buffering a voltage near ground. The technical scheme is as follows:

a CMOS buffer that buffers a voltage near ground, comprising: the operational transconductance amplifier OTA and the super source follower are composed of a bias constant current source IB1, a bias constant current source IB2, an NMOS tube N1, an NMOS tube N2 and an NMOS tube N3;

the same-direction input end of the operational transconductance amplifier OTA is connected with a voltage input end, the voltage output end, the source electrode of the NMOS tube N1 and the drain electrode of the NMOS tube N2 are connected with the reverse input end of the operational transconductance amplifier OTA, the output end of the operational transconductance amplifier OTA is connected with the grid electrode of the NMOS tube N1, the input end of the bias constant current source IB1 is connected with a power supply, the output end of the bias constant current source IB1 and the grid electrode of the NMOS tube N3 are connected with the drain electrode of the NMOS tube N1, the input end of the bias constant current source IB2 and the source electrode of the NMOS tube N3 are connected with the grid electrode of the NMOS tube N2, the source electrode of the NMOS tube N2 is grounded, the output end of the bias constant current source IB2 is grounded, and the drain electrode of the NMOS tube N3.

As a further improvement of the utility model, NMOS pipe N2 is biased in subthreshold region, NMOS pipe N1 and NMOS pipe N3 work in saturation region.

As a further improvement of the present invention, the operational transconductance amplifier OTA adopts a folded cascode structure with a PMOS source coupled differential pair as an input stage.

The utility model has the advantages that:

the utility model discloses a buffer CMOS buffer of nearly ground voltage because OTA and super source follower all are in closed loop, the grid source direct current voltage who has overcome the source follower shifts the shortcoming that changes along with PVT change, simultaneously, even if input voltage is very close to ground voltage, also can maintain higher loop gain. Sufficient loop gain ensures that the output voltage of the buffer is approximately equal to the input voltage, and has certain driving capability, namely, the buffer to the near-ground voltage is accurately realized.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following preferred embodiments are described in detail with reference to the accompanying drawings.

Drawings

FIG. 1 is a voltage buffer circuit structure (OTA-based implementation) commonly used in integrated circuits;

fig. 2 is a circuit diagram of a common OTA in CMOS process;

FIG. 3 is another conventional voltage buffer circuit structure (based on super source follower implementation);

FIG. 4 is a circuit diagram of a CMOS buffer for buffering the voltage near ground in a preferred embodiment of the present invention;

fig. 5 shows the relationship between the gain mode value and the input common mode voltage at 100kHz for the CMOS buffer for buffering the voltage near ground and the conventional voltage buffer based on the operational transconductance amplifier.

Detailed Description

The present invention is further described with reference to the following drawings and specific embodiments so that those skilled in the art can better understand the present invention and can implement the present invention, but the embodiments are not to be construed as limiting the present invention.

Referring to fig. 4, a CMOS buffer for buffering a voltage near ground according to an embodiment of the present invention includes: the operational transconductance amplifier OTA and the super source follower are composed of a bias constant current source IB1, a bias constant current source IB2, an NMOS tube N1, an NMOS tube N2 and an NMOS tube N3.

The same-direction input end of the operational transconductance amplifier OTA is connected with the voltage input end, the voltage output end, the source electrode of the NMOS tube N1 and the drain electrode of the NMOS tube N2 are connected with the reverse input end of the operational transconductance amplifier OTA, the output end of the operational transconductance amplifier OTA is connected with the grid electrode of the NMOS tube N1, the input end of the bias constant current source IB1 is connected with the power supply, the output end of the bias constant current source IB1 and the grid electrode of the NMOS tube N3 are connected with the drain electrode of the NMOS tube N1, the input end of the bias constant current source IB2 and the source electrode of the NMOS tube N3 are connected with the grid electrode of the NMOS tube N2, the source electrode of the NMOS tube N2 is grounded, the output end of the bias constant current source IB 2.

The NMOS transistor N2 is biased in a subthreshold region by selecting a larger width-length ratio, and the NMOS transistor N1 and the NMOS transistor N3 work in a saturation region.

The OTA structure of the operational transconductance amplifier in the present embodiment is shown in fig. 2, and adopts a folded cascode structure with a PMOS differential pair as an input stage, and includes PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, NMOS transistors N1, N2, N3, N4, N5, and N6, specifically, referring to fig. 2, the gate of P1 is connected to the inverting input terminal, the gate of P2 is connected to the inverting input terminal, the source of P2 is connected to the inverting input terminal, the sources of P2 and P2 are connected to the drain of P2, the sources of N2 are connected to the ground, the sources of N2 and N2 are connected to the gate of N2, the gates of N36yaias 2 and P2 are connected to the drain of vbiaas well as the source of vbiaas 72, the source 2, the source of vbp 2 and source 2 are connected to the source 2, the source 2 is connected to the source 2, the source 2 and the source of the source 2, the source, the drain of P5 is connected with the source of P7, the gate of P6 and the gate of P7 are connected with Vbias2, the gate of N1 and the gate of N2 are connected with Vbias3, the drain of P7 and the drain of N2 are connected with the gate of N6, the source of N6 is grounded, the drain of N6 and the drain of P8 are connected with the output end, and the gate of P8 is connected with Vbias 1.

Referring to fig. 4, the utility model discloses utilizing transconductance enhancement source follower to realize maintaining the higher loop gain of closed loop circuit, the normal key that realizes voltage following under the extreme condition (output voltage is close to 0V) of NMOS pipe N1 pipe is that biasing constant current source IB1 normally works (keeps high output impedance promptly), and NMOS pipe N2 pipe channel length takes the less value, the width is as big as possible in order to guarantee that NMOS pipe N2's grid voltage can not sharply decline (leads to biasing constant current source IB1 can not normally work) when higher output voltage.

When the input voltage is close to the ground, the NMOS transistor N2 is in the linear region at this time, but as long as the gate voltage of the NMOS transistor N2 does not rise to force the bias constant current source IB1 into the linear region, the NMOS transistor N1 still has the characteristic that the source voltage follows the gate voltage. Because the width and length of the NMOS tube N2 are large, the grid voltage of the NMOS tube N2 cannot change greatly, and meanwhile, the NMOS tube N2 selects a short channel length, so that the size of a small device can be ensured.

In fact, in an environment where the power supply voltage is low (below 1.2V), the source follower formed by the NMOS transistor N3 and the bias constant current source IB2 can be omitted. Thus, in the structure of the buffer, the voltage of the output end of the OTA is higher than the buffer output voltage close to the ground by one grid source voltage (VGSP1), so that the MOS tube (N6 in FIG. 2) of the output stage can be ensured to work in a saturation region, and therefore, the OTA can maintain high voltage gain; meanwhile, the super source follower ensures a small signal following effect between the output terminal of the OTA and the buffer output terminal (i.e., the loop gain is not reduced because the NMOS transistor N2 is in the linear region). Since both the OTA and the super source follower are in a closed loop, sufficient loop gain ensures that the buffer output voltage is approximately equal to the input voltage, enabling accurate voltage buffering even when the input voltage is very close to ground (e.g., 50 mV).

Referring to fig. 5, the present invention is a relation between gain mode value and input common mode voltage at 100kHz for a CMOS buffer for buffering a voltage near ground and a conventional voltage buffer based on an operational transconductance amplifier. Wherein, the utility model discloses with traditional voltage buffer based on operational transconductance amplifier all build the circuit and carried out the frequency response emulation of voltage gain under 65nmCMOS technology and 1.2V mains voltage. The closer the voltage gain is to 0dB (i.e., 1 time the voltage gain), the smaller the error of the voltage buffer. The common mode input voltage is swept at a frequency of 100kHz, resulting in fig. 5. A voltage buffer error of less than 0.1% means a voltage gain of greater than 0.999, i.e., greater than-8.69 mdB; a voltage buffer error of less than 1% means that the voltage gain is greater than 0.99, i.e., greater than-87.3 mdB.

As can be seen from fig. 5, if the buffer error of 0.1% is taken as a standard, the result shows that the lowest input common mode voltage of the conventional structure (solid line) is approximately 141mV, while the lowest input common mode voltage of the present invention (dotted line) is approximately 8mV, which is 133mV higher than that of the conventional structure; if regard as the standard with 1% buffering error, the simulation result shows, the minimum input common mode voltage of traditional structure equals about 63mV, and the utility model discloses a minimum input common mode voltage is about 4mV, has expanded 59mV for traditional structure. Therefore, the CMOS buffer for buffering the voltage near ground of the utility model has the function of buffering the voltage near ground.

The above embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. Equivalent substitutes or changes made by the technical personnel in the technical field on the basis of the utility model are all within the protection scope of the utility model. The protection scope of the present invention is subject to the claims.

Claims

1. A CMOS buffer for buffering a voltage near ground, comprising: the operational transconductance amplifier OTA and the super source follower are composed of a bias constant current source IB1, a bias constant current source IB2, an NMOS tube N1, an NMOS tube N2 and an NMOS tube N3;

2. The CMOS buffer of claim 1, wherein the NMOS transistor N2 is biased in a sub-threshold region, and the NMOS transistor N1 and the NMOS transistor N3 operate in a saturation region.

3. The CMOS buffer buffering a near-ground voltage of claim 1, wherein the Operational Transconductance Amplifier (OTA) employs a folded cascode structure with a PMOS source-coupled differential pair as an input stage.