CN210640244U - Chip combination and chip - Google Patents
Chip combination and chip Download PDFInfo
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- CN210640244U CN210640244U CN201922088063.8U CN201922088063U CN210640244U CN 210640244 U CN210640244 U CN 210640244U CN 201922088063 U CN201922088063 U CN 201922088063U CN 210640244 U CN210640244 U CN 210640244U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The embodiment of the utility model provides a chip combination and chip, include: the chip comprises a substrate, and a first chip and a second chip which are arranged on the upper surface of the substrate in a stacking manner, wherein the first chip is positioned above the second chip; the edge of the first side of the first chip and the edge of the second side of the second chip are provided with a first bonding pad pair, the edge of the second side of the first chip and the second chip is provided with a second bonding pad pair, the second bonding pad pair is positioned between two adjacent functional units on the outermost side of the second side edge of the first chip or the second chip, and the lower edge of the second bonding pad pair is not lower than the lower edges of the two adjacent functional units; the difference between the orientation of the first side of the first chip and the orientation of the first side of the second chip is 180 degrees, and the first bonding pad pair of the first chip corresponds to the second bonding pad pair of the second chip in position. The technical scheme of the utility model can reduce chip size and pad number under the limited condition in chip package inside cavity space, increase the number of piles of chip.
Description
Technical Field
The utility model relates to the field of semiconductor technology, particularly, relate to a chip combination and chip.
Background
With the current low power DRAM (Dynamic Random-Access Memory), there are typically hundreds or even more PADs, including data input/output ports, command address ports, clock ports, and multiple sets of power/ground ports. The ports of the multiple groups of power sources/grounds are used as the components of distributed power supply, so that the power supply balance and consistency of the power sources/grounds can be increased. The pad layout of a chip generally includes the following:
as shown in fig. 1, the PAD and peripheral control logic 103 are disposed in the middle of the chip, i.e. between the memory cell arrays 104, so that the distance from the PAD of power/ground to both edges of the chip is only half of the height of the chip, the parasitic resistance is reduced by half, and the voltage drop on the power/ground is reduced by half under the condition of power/ground cables with the same width and the same current, thereby reducing noise, increasing the driving capability, and being particularly beneficial to the high-frequency operation mode of the chip. However, this approach is not good for large-capacity stacked package, and if the package is to be stacked, RDL (Re-Distribution Layer) is required to be introduced to introduce the middle PAD to one side of the chip, which increases the complexity of the process and the cost of manufacturing, and the parasitic resistance caused by the introduction of RDL also reduces the benefit of low resistance obtained by placing the PAD in the middle.
As shown in fig. 2, when the PAD and the peripheral control logic are placed on one side of the chip, especially on the short side, the power/ground bus is the longest, the parasitic resistance is the largest, and the voltage drop is the largest at the far end of the chip far from the PAD, which causes the far end performance of the chip to be much worse than the near end performance, especially in the high frequency operation mode. In order to enable the far end to work normally, the required power/ground flat cable has to be widened, and the space of other signal lines is occupied, so that the layout design is difficult.
As shown in fig. 3, the peripheral control logic and a part of PAD are disposed on one side of the chip, and a part of PAD is disposed on the other side of the chip, where the PAD includes distributed power/ground PADs 102 and other signal PADs 101, which can also reduce the equivalent resistance of the power/ground cable and the cable area, but directly results in increased chip cost due to the increased area of the row of PADs, and the PAD layout on both sides can adversely affect the large-capacity and small-scale packaging of the chip.
At present, the packaging trend of low-power-consumption DRAM is large capacity and miniaturization, that is, it is desirable to package multiple particles of low-power-consumption DRAM in one packaging cavity to improve capacity and reduce power consumption. This requires that the DRAM chips be packaged in stacks. Without considering the expensive TSV (Through Silicon Via) technology, as in the stacked package shown in fig. 4 and 5, the chip 401 is disposed on the substrate 402, and the stacked package is convenient only by placing the PAD at the edge of the chip.
The more the number of stacked layers of chips, the longer the connecting wire (bonding wire) from the chip to the substrate, and the larger the occupied space, under the condition that the space of the cavity inside the package is limited, the size of the chip, the number of bonding pads connected on the substrate, and the number of stacked layers are in a mutual restriction relationship, the size of the chip is smaller, the number of bonding pads is smaller, and more layers can be stacked. The chip shown in fig. 5 is smaller than the chip shown in fig. 6, so that a larger number of layers can be stacked; the number of pads shown in fig. 7 is greater than that shown in fig. 8, so that the chip-to-substrate connection is longer, the angle is larger, and the occupied space is larger.
The technical problems that the number of bonding pads is large and the number of stacked layers is small in chip assembly are needed to be solved at present.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present invention and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
SUMMERY OF THE UTILITY MODEL
An object of the embodiment of the utility model is to provide a chip combination and chip, and then solve the problem that the pad is more, pile up the number of piles less in the chip combination to a certain extent at least.
Other features and advantages of the invention will be apparent from the following detailed description, or may be learned by practice of the invention.
According to the utility model discloses a first aspect provides a chip combination, include: the chip assembly comprises a substrate, a first chip and a second chip which are arranged on the upper surface of the substrate in a stacked mode, wherein the first chip is positioned above the second chip; a first pad pair comprising a first reference potential pad and a second reference potential pad is arranged on the edge of the first side of the first chip and the edge of the second side of the second chip, a second pad pair comprising a first reference potential pad and a second reference potential pad is arranged on the edge of the second side of the first chip and the second chip, the second pad pair is positioned between two adjacent function units on the outermost side of the second side edge of the first chip or the second chip, and the lower edge of the second pad pair is not lower than the lower edges of the two adjacent function units; the difference between the orientation of the first side of the first chip and the orientation of the first side of the second chip is 180 degrees, and the first bonding pad pair of the first chip corresponds to the second bonding pad pair of the second chip in position.
In some embodiments, the first reference potential is a positive power supply and the second reference potential is a ground potential.
In some embodiments, the chip assembly further includes a third chip and a fourth chip arranged in a stack, and the third chip and the fourth chip arranged in the stack are arranged on the substrate side by side with the first chip and the second chip arranged in the stack.
In some embodiments, the upper surface of the edge of the substrate corresponding to the first side and the second side of the first chip is provided with gold fingers.
In some embodiments, the pair of pads is disposed on an upper surface of the first chip and the second chip.
In some embodiments, the pair of pads on the first chip and the second chip are coupled with the gold fingers by bonding wires.
In some embodiments, the pair of pads on the first side of the first chip are connected to the pair of pads on the second side of the first chip by a power bus cable.
In some embodiments, each of the chip combinations includes a first chip and a second chip arranged in a stack, and a third chip and a fourth chip arranged in a stack.
In some embodiments, the first chip includes a peripheral logic control circuit and an array of memory cells, the peripheral logic control circuit being located on a first side of the first chip.
In some embodiments, other signal pads of the first chip than the first and second reference potential pads are disposed at an edge of the first side of the first chip.
In some embodiments, a first reference potential pad of a first pad pair of the first chip corresponds in position to a first reference potential pad of a second pad pair of the second chip; and the second reference potential bonding pad of the first bonding pad pair of the first chip corresponds to the second reference potential bonding pad of the second bonding pad pair of the second chip in position.
According to a second aspect of the embodiments of the present invention, there is provided a chip, wherein a first pad pair including a first reference potential pad and a second reference potential pad is disposed on an edge of a first side of the chip, a second pad pair including a first reference potential pad and a second reference potential pad is disposed on an edge of a second side of the chip, the second pad pair is located between two adjacent function units on an outermost side of a second side edge of the chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent function units; after the chip rotates 180 degrees in the plane where the chip is located, the bonding pad pair on the first side of the chip after rotation corresponds to the bonding pad pair on the second side of the chip before rotation.
In some embodiments, the first reference potential pad of the first pad pair of the chip after the rotation corresponds to the first reference potential pad of the second pad pair of the chip before the rotation; and the second reference potential bonding pad of the first bonding pad pair of the chip after rotation corresponds to the second reference potential bonding pad of the second bonding pad pair of the chip before rotation.
In some embodiments, the chip comprises a dynamic random access memory chip, and the functional unit of the chip comprises an array of memory cells.
The embodiment of the utility model provides a technical scheme can include following beneficial effect:
in the technical solutions provided in some embodiments of the present invention, the first side and the second side of the first chip and the second chip are respectively provided with the pad pair, and the first pad pair of the first chip corresponds to the second pad pair of the second chip in position, so that the number of pads of the chip can be reduced, the number of solder joints corresponding to the pad pairs on the substrate can be reduced, and the number of stackable layers can be increased in the fixed packaging space; in addition, the second bonding pad pair is positioned between two adjacent functional units on the outermost side of the second side edge of the first chip or the second chip, so that the space of the chip can be further saved, and the effect that the bonding pads are arranged on the second side of the chip but do not occupy the space of the second side edge is achieved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram schematically illustrating a chip layout in the related art;
fig. 2 is a schematic diagram schematically showing another chip layout in the related art;
FIG. 3 is a schematic diagram schematically illustrating yet another chip layout in the related art;
FIG. 4 is a top view schematically illustrating yet another chip layout in the related art;
fig. 5 schematically shows a cross-sectional view of still another chip layout in the related art;
fig. 6 schematically shows a cross-sectional view of still another chip layout in the related art;
FIG. 7 is a schematic view showing a chip and substrate connection in the related art;
fig. 8 is a schematic view schematically showing another chip-to-substrate connection in the related art;
fig. 9 schematically shows a schematic structural diagram of a chip according to an embodiment of the present invention;
fig. 10 is a schematic diagram illustrating a pad pin variation according to an embodiment of the present invention;
fig. 11 schematically shows a schematic structural diagram of a chip assembly according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments will now be described more fully with reference to the accompanying drawings. The exemplary embodiments, however, may be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the module of the icon is turned upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
In the related art, in the same package internal cavity space, the more the number of pads of the chips of the chip assembly is, the fewer the number of layers that the chips can be stacked on, thereby affecting the function of the chip assembly.
In order to solve the above problem, an embodiment of the present invention provides a chip assembly to reduce the number of pads of a chip, so as to increase the number of stackable layers in a fixed package space.
Fig. 9 schematically shows a schematic structural diagram of a chip according to an embodiment of the present invention.
As shown in fig. 9, a first pad pair 901 including a first reference potential pad and a second reference potential pad is disposed on an edge of a first side of a chip, a second pad pair 902 including a first reference potential pad and a second reference potential pad is disposed on an edge of a second side of the chip, the second pad pair 902 is located between two adjacent function units on an outermost side of a second side edge of the chip, and a lower edge of the second pad pair 902 is not lower than lower edges of the two adjacent function units; after the chip rotates 180 degrees in the plane where the chip is located, the bonding pad pair on the first side of the chip after rotation corresponds to the bonding pad pair on the second side of the chip before rotation.
In this way, the first reference potential bonding pad of the first bonding pad pair of the chip after rotation corresponds to the first reference potential bonding pad of the second bonding pad pair of the chip before rotation; and the second reference potential bonding pad of the first bonding pad pair of the chip after rotation corresponds to the second reference potential bonding pad of the second bonding pad pair of the chip before rotation.
Here, the chip may be a dynamic random access memory chip, and the functional unit may be the memory cell array 104. The first reference potential may be a positive power supply and the second reference potential may be a ground potential. As shown in fig. 10, according to a pad order recommended by JEDEC (joint electron Device Engineering Council State Technology Association), appropriate VSSQ (digital I/O port ground) and VQQ (digital ground), such as pad 19, pad 39, and pad 60, are selected according to the arrangement position of the memory cell array 104, and power supply positive electrode (VDD2) pads, such as pad 18A, pad 38A, and pad 60B, are added beside these VSSQ and VQQ. The added positive power supply (VDD2) PAD forms a PAD pair, i.e., a power/ground pair, with an adjacent ground PAD to facilitate remote PAD distribution design. Here, VSSQ and VSS are actually short-circuited, i.e., are the same node.
The chip combination provided by the exemplary embodiment of the disclosure comprises: the chip comprises a substrate, and a first chip and a second chip which are arranged on the upper surface of the substrate in a stacking mode, wherein the first chip is positioned above the second chip. Here, the first chip is the chip shown in fig. 9.
As shown in fig. 11, a first pad pair 901 including a first reference potential pad and a second reference potential pad is provided on an edge of the first side of the first chip. A second pad pair 902 including a first reference potential pad and a second reference potential pad is disposed on an edge of the second side of the first chip, the second pad pair 902 is located between two outermost adjacent functional units of the second side edge of the first chip, and a lower edge of the second pad pair 902 is not lower than lower edges of the two adjacent functional units. The edge of the first side of the second chip is provided with a first pad pair comprising a first reference potential pad and a second reference potential pad, the edge of the second side of the second chip is provided with a second pad pair comprising a first reference potential pad and a second reference potential pad, the second pad pair is positioned between two adjacent functional units on the outermost side of the second side edge of the second chip, and the lower edge of the second pad pair is not lower than the lower edges of the two adjacent functional units. The difference between the orientation of the first side of the first chip and the orientation of the first side of the second chip is 180 degrees, and the first bonding pad pair of the first chip corresponds to the second bonding pad pair of the second chip in position.
The utility model discloses technical scheme sets up the pad pair at the edge of the first side of first chip and second side, and the first pad of first chip is to the second pad corresponding to the position with the second chip, like this, when with the pad to with the golden finger welding on the base plate, can correspond same golden finger with a pad of the first side of first chip and a pad of the second side of second chip and connect to reduce the quantity of golden finger.
In addition, the second PAD pair is positioned between two adjacent functional units on the outermost side of the second side edge of the first chip or the second chip, so that the space of the second side edge of the chip is saved, all factors such as packaging feasibility, power/ground PAD layout, wiring resource and utilization rate, distribution of modules in the chip, chip area and manufacturing cost are comprehensively considered, the second PAD pair is a novel power/ground PAD arrangement mode, and the purposes of reducing equivalent resistance of a power/ground wiring and improving high-frequency performance of the chip can be achieved under the condition of not increasing the area.
In the embodiment of the present invention, the first reference potential pad of the first pad pair of the first chip corresponds to the first reference potential pad of the second pad pair of the second chip in position; the second reference potential pad of the first pad pair of the first chip corresponds in position to the second reference potential pad of the second pad pair of the second chip.
As shown in fig. 9, the first side of the first chip is provided with 3 sets of pad pairs. The left bonding pad of the first bonding pad pair from left to right is a power supply positive bonding pad, and the right bonding pad is a ground potential bonding pad; the left pad of the second pad pair and the third pad pair from left to right is a ground potential pad, and the right pad is a power supply positive pad. The second side of the first chip is provided with 3 groups of bonding pad pairs, wherein the left bonding pad of the first bonding pad pair and the second bonding pad pair from left to right is a power supply anode bonding pad, and the right bonding pad is a ground potential bonding pad; and the left pad of the third pad pair from left to right is a ground potential pad, and the right pad is a power supply positive pad. The second chip may have the same structure as the first chip.
Thus, when the first PAD pair of the first chip and the second PAD pair of the second chip are arranged correspondingly, 3 groups of power/ground PADs on the first side of the first chip above are superposed with the power/ground PAD positions on the second side of the second chip below, no extra area is needed for placing the PADs, and no extra golden finger is needed to be added on the substrate for connection during packaging.
In addition, some logics such as decoding logics among the memory cell arrays 104 are connected up and down, and the memory cell array at the bottommost part has no connecting line because of the lower part, some logics can be simplified, deleted, and a PAD of a power supply/ground is placed at an empty position, so that the second PAD pair can be arranged between two adjacent outermost functional units at the second side edge of the first chip or the second chip to reduce the area of the chip.
As shown in fig. 9, the pair of pads on the first side of the first chip are connected to the pair of pads on the second side by a power bus line 903. The first chip comprises a peripheral logic control circuit 103 and a memory cell array 104, wherein the peripheral logic control circuit 103 is positioned on a first side of the first chip. The signal pads of the first chip except the first reference potential pad and the second reference potential pad are arranged at the edge of the first side of the first chip. Here, the other signal pads include a data input output port pad, a command address port pad, and a clock port pad.
The embodiment of the present invention provides a chip assembly, which further includes a third chip and a fourth chip stacked together, wherein the stacked assembly formed by the first chip and the second chip and the stacked assembly formed by the third chip and the fourth chip are disposed side by side on the substrate.
The number of chips in the stacked combination formed by the first chip and the second chip on the substrate as shown in fig. 11 is two, but the number of chips in the stacked combination formed by the first chip and the second chip is not limited thereto in practical application. Likewise, the number of chips combined by the stack formed by the third chip and the fourth chip may be two or more. For example, in one embodiment, each chip combination includes a first chip and a second chip arranged in a stack, and a third chip and a fourth chip arranged in a stack.
As shown in fig. 11, a first chip 1101 and a second chip 1102 are stacked on a substrate 402. The power supply positive electrode pad 1105 and the ground potential pad 1106 are coupled with the gold finger 1103 and the gold finger 1104 by bonding wires 1107. In an embodiment of the present invention, the edge of the substrate corresponding to the first side and the second side of the first chip is provided with a golden finger. The golden fingers are arranged on the upper surface of the substrate, and the bonding pad pairs can also be arranged on the upper surfaces of the first side edge and the second side edge of the first chip and the second chip.
Also, the pad pair may be disposed on the upper surfaces of the third chip and the fourth chip. The pad pairs on the third and fourth chips may also be coupled to the gold fingers by bonding wires. Here, the pad pair may include a power supply positive pad 1105 and a ground potential pad 1106.
In the chip assembly of the embodiment of the present invention, the first side and the second side of the first chip and the second chip are respectively provided with the pad pair, and the first pad pair of the first chip corresponds to the second pad pair of the second chip in position, so that the number of pads of the chip can be reduced, the number of solder joints corresponding to the pad pairs on the substrate can be reduced, and the number of stackable layers can be increased in the fixed packaging space; in addition, the second bonding pad pair is positioned between two adjacent functional units on the outermost side of the second side edge of the first chip or the second chip, so that the space of the chip can be further saved, and the effect that the bonding pads are arranged on the second side of the chip but do not occupy the space of the second side edge is achieved.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.
Claims (14)
1. A chip assembly, comprising: the chip packaging structure comprises a substrate, and a first chip and a second chip which are arranged on the upper surface of the substrate in a stacked mode, wherein the first chip is positioned above the second chip;
a first pad pair comprising a first reference potential pad and a second reference potential pad is arranged on the edge of the first side of the first chip and the edge of the second side of the second chip, a second pad pair comprising a first reference potential pad and a second reference potential pad is arranged on the edge of the second side of the first chip and the second chip, the second pad pair is positioned between two adjacent function units on the outermost side of the second side edge of the first chip or the second chip, and the lower edge of the second pad pair is not lower than the lower edges of the two adjacent function units;
the difference between the orientation of the first side of the first chip and the orientation of the first side of the second chip is 180 degrees, and the first bonding pad pair of the first chip corresponds to the second bonding pad pair of the second chip in position.
2. The chip assembly of claim 1, wherein the first reference potential is a positive power supply and the second reference potential is a ground potential.
3. The die combination of claim 1, further comprising third and fourth dies arranged in a stack, the third and fourth dies arranged in the stack being arranged on the substrate alongside the first and second dies arranged in the stack.
4. The chip combination of claim 3, wherein the upper surface of the edge of the substrate corresponding to the first side and the second side of the first chip is provided with gold fingers.
5. The die combination of claim 4, wherein the pair of bonding pads are disposed on the upper surfaces of the first die and the second die.
6. The chip assembly of claim 4, wherein the pair of pads on the first chip and the second chip are coupled to the gold finger by a bonding wire.
7. The chip assembly of claim 1, wherein the pair of pads on the first side of the first chip are connected to the pair of pads on the second side of the first chip by a power bus.
8. The chip assembly of claim 1, wherein each of the chip assemblies includes a first chip and a second chip arranged in a stack, and a third chip and a fourth chip arranged in a stack.
9. The chip combination of claim 1, wherein the first chip comprises a peripheral logic control circuit and an array of memory cells, the peripheral logic control circuit being located on a first side of the first chip.
10. The chip assembly of claim 1, wherein signal pads of the first chip other than the first and second reference potential pads are disposed at an edge of the first side of the first chip.
11. The die combination of claim 1, wherein the first reference potential pad of the first pad pair of the first die corresponds in position to the first reference potential pad of the second pad pair of the second die; and the second reference potential bonding pad of the first bonding pad pair of the first chip corresponds to the second reference potential bonding pad of the second bonding pad pair of the second chip in position.
12. A chip is characterized in that a first pad pair comprising a first reference potential pad and a second reference potential pad is arranged on the edge of a first side of the chip, a second pad pair comprising a first reference potential pad and a second reference potential pad is arranged on the edge of a second side of the chip, the second pad pair is positioned between two adjacent functional units on the outermost side of the second side edge of the chip, and the lower edge of the second pad pair is not lower than the lower edges of the two adjacent functional units;
after the chip rotates 180 degrees in the plane where the chip is located, the bonding pad pair on the first side of the chip after rotation corresponds to the bonding pad pair on the second side of the chip before rotation.
13. The chip of claim 12, wherein the first reference potential pad of the first pad pair of the chip after rotation corresponds in position to the first reference potential pad of the second pad pair of the chip before rotation; and the second reference potential bonding pad of the first bonding pad pair of the chip after rotation corresponds to the second reference potential bonding pad of the second bonding pad pair of the chip before rotation.
14. The chip of claim 12, wherein the chip comprises a dynamic random access memory chip, and wherein the functional unit of the chip comprises an array of memory cells.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922088063.8U CN210640244U (en) | 2019-11-26 | 2019-11-26 | Chip combination and chip |
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| CN201922088063.8U CN210640244U (en) | 2019-11-26 | 2019-11-26 | Chip combination and chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021103642A1 (en) * | 2019-11-26 | 2021-06-03 | 长鑫存储技术有限公司 | Chip combination and chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021103642A1 (en) * | 2019-11-26 | 2021-06-03 | 长鑫存储技术有限公司 | Chip combination and chip |
| US11164849B2 (en) | 2019-11-26 | 2021-11-02 | Changxin Memory Technologies, Inc. | Chip assembly and chip |
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