CN210640233U

CN210640233U - Semiconductor structure

Info

Publication number: CN210640233U
Application number: CN201922109340.9U
Authority: CN
Inventors: 庄凌艺
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2020-05-29
Anticipated expiration: 2029-11-29

Abstract

The disclosure relates to the technical field of semiconductors, and provides a semiconductor structure, which comprises a semiconductor substrate, a metal bonding pad, a bump, a first solder layer, a metal blocking layer and a second solder layer, wherein the metal bonding pad is arranged on the semiconductor substrate; the lug is arranged on the metal bonding pad; the first solder layer is arranged on one side of the lug, which is far away from the metal pad; the metal blocking layer is arranged on one side of the first solder layer, which is far away from the bump, and is provided with a first accommodating groove and a second accommodating groove which are separated from each other; the second solder layer is arranged in the first accommodating groove, and part of the second solder layer protrudes out of the notch of the first accommodating groove. Since the first solder layer and the second solder layer have the property of being stretchable by reflow high-temperature melting, the height adjustment is automatically performed, so that the problem of non-wetting caused by deformation of the packaged substrate after reflow can be reduced.

Description

Semiconductor structure

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure.

Background

With the increasing functionality, performance and integration level of integrated circuits, and the emergence of new types of integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and accounts for an increasing proportion of the value of the entire electronic system. The bump interconnection technology is becoming a key technology for narrow-pitch interconnection of next-generation chips due to its good electrical performance and electromigration resistance.

In the prior art, in the flip chip welding process of a chip, a packaging substrate is heated to warp, the height difference between the chip and the substrate occurs, the solder quantity is insufficient due to tin climbing to cause the non-wetting problem, and the solder quantity is too much to cause the problem of solder bridging between bumps.

SUMMERY OF THE UTILITY MODEL

It is a primary object of the present disclosure to overcome at least one of the above-mentioned deficiencies of the prior art and to provide a semiconductor structure and a method for fabricating the same.

The utility model provides a semiconductor structure, include:

a semiconductor substrate;

the metal bonding pad is arranged on the semiconductor substrate;

the bump is arranged on the metal bonding pad;

the first welding flux layer is arranged on one side of the lug, which is far away from the metal pad;

the metal blocking layer is arranged on one side of the first solder layer, which is far away from the bump, and is provided with a first accommodating groove and a second accommodating groove which are separated from each other, the notch of the first accommodating groove faces the direction far away from the first solder layer, and the first solder layer is arranged in the second accommodating groove;

the second solder layer is arranged in the first accommodating groove, and part of the second solder layer protrudes out of the notch of the first accommodating groove.

In one embodiment of the present invention, the cross-section of the metal barrier layer is H-shaped.

In an embodiment of the present invention, the metal blocking layer is spaced from the bump, and the first solder layer is disposed between the metal blocking layer and the bump.

The utility model discloses an in the embodiment, all be provided with second solder layer in the first holding tank, all be provided with first solder layer in the second holding tank.

In an embodiment of the present invention, the bump is a copper pillar, and the semiconductor structure further includes:

and at least part of the under bump metal layer is clamped between the metal pad and the bump.

In an embodiment of the present invention, the semiconductor structure further includes:

the first protective layer is arranged on the semiconductor substrate and provided with a first opening, and a part of the metal bonding pad is exposed by the first opening.

In one embodiment of the present invention, the bump has a rectangular cross section, the under bump metal layer is located in the first opening, and a portion of the bump is located in the first opening.

the second protective layer is arranged on the first protective layer and provided with a second opening, and the caliber of the second opening is smaller than or equal to that of the first opening;

the under bump metal layer at least covers the bottom surface and the side wall surface of the second opening, and at least part of the under bump metal layer is arranged in the second opening.

In one embodiment of the present invention, the bump has a T-shaped cross section, the small end of the bump is located inside the under bump metal layer, and the large end of the bump is located outside the under bump metal layer.

In an embodiment of the present invention, the portion of the under bump metal layer is located outside the second opening, and the projection of the circumferential outer edge of the under bump metal layer and the projection of the circumferential outer edge of the big end of the under bump metal layer on the same plane coincide with each other.

The utility model discloses a semiconductor structure comprises semiconductor substrate, metal pad, lug, first solder layer, metal barrier layer and second solder layer, is provided with second solder layer and first solder layer in the first holding tank on metal barrier layer and the second holding tank respectively. Because the second solder layer and the first solder layer are wrapped in the metal barrier layer, the problems of non-wetting caused by insufficient solder amount and solder bridging caused by too much solder amount during the soldering process of the flip chip can be improved.

Drawings

Various objects, features and advantages of the present disclosure will become more apparent from the following detailed description of preferred embodiments thereof, when considered in conjunction with the accompanying drawings. The drawings are merely exemplary illustrations of the disclosure and are not necessarily drawn to scale. In the drawings, like reference characters designate the same or similar parts throughout the different views. Wherein:

FIG. 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

FIG. 2 is a schematic diagram of a semiconductor structure according to another exemplary embodiment;

FIG. 3 is a schematic diagram illustrating an assembly of a semiconductor structure and a package substrate according to an exemplary embodiment;

FIG. 4 is a schematic diagram illustrating a semiconductor structure after an under bump metallurgy layer is formed using a method for fabricating the semiconductor structure, in accordance with one exemplary embodiment;

FIG. 5 is a schematic diagram illustrating a structure after a first solder layer is formed using a method of fabricating a semiconductor structure according to an exemplary embodiment;

FIG. 6 is a schematic diagram illustrating a method of fabricating a semiconductor structure after removing a first layer of photoresist, according to an exemplary embodiment;

FIG. 7 is a schematic diagram illustrating a structure after a first mask layer is formed using a method of fabricating a semiconductor structure, according to an exemplary embodiment;

FIG. 8 is a schematic diagram illustrating a structure after photolithography of a first mask layer using a method of fabricating a semiconductor structure, according to an exemplary embodiment;

FIG. 9 is a schematic diagram illustrating a structure after acid etching of a first mask layer using a method for fabricating a semiconductor structure, in accordance with one illustrative embodiment;

FIG. 10 is a schematic diagram illustrating a structure after removal of a first masking layer using a method for fabricating a semiconductor structure, in accordance with one exemplary embodiment;

FIG. 11 is a schematic diagram illustrating a structure after a metal barrier layer is formed using a method of fabricating a semiconductor structure, according to an exemplary embodiment;

FIG. 12 is a schematic diagram illustrating a second photoresist layer formed by a method for forming a semiconductor structure in accordance with one exemplary embodiment;

FIG. 13 is a schematic diagram illustrating a structure after etching a metal barrier layer using a method of fabricating a semiconductor structure in accordance with one exemplary embodiment;

FIG. 14 is a schematic diagram illustrating a method of fabricating a semiconductor structure after removing a second layer of photoresist, in accordance with one illustrative embodiment;

fig. 15 is a schematic structural view after a second solder layer is formed by a method of manufacturing a semiconductor structure according to an exemplary embodiment;

fig. 16 is a schematic diagram illustrating a structure after etching the second mask layer using a method for fabricating a semiconductor structure, according to an example embodiment.

The reference numerals are explained below:

1. a package substrate; 10. a metal pad; 11. a first photoresist layer; 12. a first mask layer; 13. a second mask layer; 14. a second photoresist layer; 20. a semiconductor substrate; 30. a bump; 40. a first solder layer; 41. removing the space; 50. a metal barrier layer; 51. a first accommodating groove; 52. a second accommodating groove; 60. a second solder layer; 70. a metal layer under the bump; 80. a first protective layer; 90. and a second protective layer.

Detailed Description

Exemplary embodiments that embody features and advantages of the present disclosure are described in detail below in the specification. It is to be understood that the disclosure is capable of various modifications in various embodiments without departing from the scope of the disclosure, and that the description and drawings are to be regarded as illustrative in nature, and not as restrictive.

In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary structures, systems, and steps in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various example features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples in the figures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of this disclosure.

An embodiment of the present invention provides a semiconductor structure, please refer to fig. 1 and fig. 2, the semiconductor structure includes: a semiconductor substrate 20; a metal pad 10 disposed on the semiconductor substrate 20; a bump 30 disposed on the metal pad 10; a first solder layer 40 disposed on a side of the bump 30 away from the metal pad 10; the metal blocking layer 50 is arranged on one side of the first solder layer 40 far away from the bump 30, the metal blocking layer 50 is provided with a first accommodating groove 51 and a second accommodating groove 52 which are separated, the notch of the first accommodating groove 51 faces the direction far away from the first solder layer 40, and the first solder layer 40 is arranged in the second accommodating groove 52; the second solder layer 60 is disposed in the first receiving groove 51, and a portion of the second solder layer 60 protrudes out of the notch of the first receiving groove 51.

The utility model discloses a semiconductor structure of an embodiment comprises semiconductor substrate 20, metal pad 10, lug 30, first solder layer 40, metal barrier layer 50 and second solder layer 60, and metal pad 10 sets up the upper surface at semiconductor substrate 20, then upwards has set gradually lug 30, first solder layer 40, metal barrier layer 50 and second solder layer 60. Since the second solder layer 60 and the first solder layer 40 are wrapped in the metal barrier layer 50, the non-wetting problem caused by insufficient solder amount during tin climbing and the solder bridging problem caused by too much solder amount during the flip chip soldering process can be improved.

In one embodiment, as shown in fig. 3, the semiconductor structure is a stretchable metal, and the package substrate 1 is warped by heating during the flip chip bonding process, and the first solder layer 40 has the property of being stretchable by reflowing and melting at high temperature, so that the height adjustment is automatically performed, and the non-wetting problem caused by the deformation of the package substrate 1 after reflow can be reduced.

In one embodiment, the first receiving groove 51 and the second receiving groove 52 of the metal blocking layer 50 both have only one opening, that is, the first receiving groove 51 and the second receiving groove 52 are both semi-closed grooves, and in the process of flip-chip reflow, the metal blocking layer 50 can block the flow of solder and play a role in drainage, so that the second solder layer 60 is not diffused in a large amount, the problem of solder bridging is avoided, and the goal of improving the yield is achieved.

In one embodiment, first solder layer 40 and second solder layer 60 may be one of lead, tin, and silver or an alloy containing any of the solder metals described above. For example, the material of first solder layer 40, and/or second solder layer 60 may be an alloy containing 91.5% to 98.5% tin and 8.5% to 1.5% silver. Alternatively, the material of first solder layer 40, and/or second solder layer 60 may be an alloy containing 93.2% to 96.5% tin and 6.8% to 3.5% silver, and the material of first solder layer 40, and/or second solder layer 60 may be an alloy containing 98.2% to 98.5% tin and 1.8% to 1.5% silver.

In one embodiment, the semiconductor base 20 includes a semiconductor substrate and a number of IC lines and insulating layers. The material of the metal pad 10 may be, but is not limited to, aluminum or copper.

In one embodiment, the cross-section of the metal barrier layer 50 is H-shaped. The cross section of the metal blocking layer 50 may be understood as a longitudinal cross section of the metal blocking layer 50 with reference to fig. 1 and 2. The metal barrier layer 50 is a barrel-shaped structure spaced apart from each other, and the second solder layer 60 and the first solder layer 40 do not contact each other.

In one embodiment, the metal barrier layer 50 is disposed at a distance from the bump 30, and the first solder layer 40 is disposed between the metal barrier layer 50 and the bump 30. The first solder layer 40 has a T-shaped cross section, i.e. the small end is located inside the second receiving groove 52, and the large end is located outside the second receiving groove 52.

In one embodiment, the first receiving grooves 51 are provided with the second solder layers 60, and the second receiving grooves 52 are provided with the first solder layers 40. The portion of the second solder layer 60 protruding the first receiving groove 51 may cover a partial upper surface of the metal blocking layer 50, or completely cover the upper surface of the metal blocking layer 50, and it is not excluded that the upper surface of the metal blocking layer 50 is not completely covered.

In one embodiment, the material of the metal barrier layer 50 may include nickel.

In one embodiment, the bump 30 is a copper pillar, and the semiconductor structure further includes: and an under bump metal layer 70, at least a part of the under bump metal layer 70 being sandwiched between the metal pad 10 and the bump 30. The metal material layer of the under bump metallurgy 70 may include a Ti layer, a TiW layer, and a Cu layer. The under bump metallurgy 70 is electrically connected to the metal pad 10. The under bump metallurgy 70 makes the bump 30 not directly contact with the metal pad 10.

In one embodiment, the semiconductor structure further comprises: the first protection layer 80 is disposed on the semiconductor substrate 20, the first protection layer 80 has a first opening, and a portion of the metal pad 10 is exposed by the first opening, that is, the first protection layer 80 covers a circumferential outer edge of the metal pad 10. The material of the first protection layer 80 may be one or a combination of silicon dioxide and silicon nitride.

In one embodiment, the first protective layer 80 covers a portion of the metal pad 10 and a region of the semiconductor substrate 20 outside the metal pad 10.

In one embodiment, the semiconductor structure further comprises: a second passivation layer 90 disposed on the first passivation layer 80, the second passivation layer 90 having a second opening, wherein the aperture of the second opening is smaller than or equal to the aperture of the first opening; the under bump metal layer 70 at least covers the bottom surface and the sidewall surface of the second opening, and at least a portion of the under bump metal layer 70 is disposed in the second opening. The material of the second protective layer 90 may be polyimide.

In one embodiment, the bump 30 has a T-shaped cross section, the small end of the bump 30 is located inside the under bump metallurgy 70, and the large end of the bump 30 is located outside the under bump metallurgy 70. The portion of the under bump metal layer 70 is located outside the second opening, and a projection of a circumferential outer edge of the under bump metal layer 70 and a projection of a circumferential outer edge of the large end of the under bump metal layer 70 on the same plane coincide, that is, a projection on the second protective layer 90 coincides.

In one embodiment, the under bump metallurgy 70 is disposed on a portion of the second protective layer 90 and the exposed metal pad 10. In one embodiment, the under bump metallurgy 70 may wrap the bumps 30, that is, the bumps 30 are all located in the open cavities formed by the under bump metallurgy 70, and the plane of the notches of the under bump metallurgy 70 is on the same plane as the bottom surface of the first solder layer 40.

In one embodiment, as shown in fig. 1, the semiconductor structure is composed of a semiconductor substrate 20, a metal pad 10, a bump 30, a first solder layer 40, a metal blocking layer 50, a second solder layer 60, an under bump metal layer 70, a first protection layer 80 and a second protection layer 90, wherein the first protection layer 80 covers the metal pad 10 and blocks a portion of the metal pad 10, the second protection layer 90 is disposed on the first protection layer 80 and covers a portion of the metal pad 10, and the second protection layer 90 and the first protection layer 80 cover the metal pad 10 in opposite positions, i.e., the first protection layer 80 is disposed under the second protection layer 90. The second protective layer 90 does not cover the middle of the metal pad 10, and the under bump metallurgy 70 arranges metal material layers such as a Ti layer, a TiW layer, and a Cu layer on the second protective layer 90 and the metal pad 10 by physical vapor deposition, and the Ti layer can adhere and block metal copper from entering the semiconductor substrate 20, and the Cu layer can form an electroplated electrode. The bump 30 has a T-shaped cross section, i.e., the small end is located inside the under bump metallurgy 70, and the large end is located outside the under bump metallurgy 70.

In another embodiment, as shown in fig. 2, the semiconductor structure is composed of a semiconductor substrate 20, a metal pad 10, a bump 30, a first solder layer 40, a metal blocking layer 50, a second solder layer 60, an under bump metal layer 70, and a first protection layer 80, wherein the first protection layer 80 covers the metal pad 10 and shields a portion of the metal pad 10. The under bump metallurgy 70 is formed by disposing metal material layers such as Ti layer, TiW layer, and Cu layer on the metal pad 10 by physical vapor deposition, and the Ti layer can adhere and block metal copper from entering the semiconductor substrate 20, and the Cu layer can form an electroplated electrode. The bump 30 has a rectangular cross section, and the bump 30 is located between the under bump metallurgy 70 and the first solder layer 40.

In one embodiment, the bumps 30 have a rectangular cross-section, the underbump metallurgy 70 is located in the first opening, and a portion of the bump 30 is located in the first opening. The bump 30 is located in the middle of the first opening and spaced apart from the first passivation 80. The projection of the circumferential outer edge of the bump 30 and the projection of the circumferential outer edge of the under bump metal layer 70 on the same plane coincide, that is, the projection on the metal pad 10 coincides, and the under bump metal layer 70 covers a part of the metal pad 10, so that a part of the metal pad 10 is exposed.

An embodiment of the present invention further provides a method for manufacturing a semiconductor structure, including: providing a semiconductor substrate 20, and forming a metal pad 10 on the semiconductor substrate 20; forming a bump 30 on the metal pad 10; forming a first solder layer 40 on a side of the bump 30 away from the metal pad 10; forming a metal barrier layer 50 on a side of the first solder layer 40 away from the bump 30, wherein the metal barrier layer 50 has a first receiving groove 51 and a second receiving groove 52 which are separated from each other, a notch of the first receiving groove 51 faces a direction away from the first solder layer 40, and the first solder layer 40 is disposed in the second receiving groove 52; the second solder layer 60 is formed in the first receiving groove 51, and a portion of the second solder layer 60 is made to protrude from the notch of the first receiving groove 51.

In one embodiment, prior to forming the bump 30, the manufacturing method further includes: forming an under bump metallurgy layer 70 on the metal pad 10; at least a portion of the under bump metal layer 70 is sandwiched between the metal pad 10 and the bump 30.

In one embodiment, prior to forming the bump 30, the manufacturing method further includes: forming a first protective layer 80 on the semiconductor substrate 20; the first protection layer 80 has a first opening, and the first opening exposes a portion of the metal pad 10.

In one embodiment, after forming the first protection layer 80, the manufacturing method further includes: forming a second protective layer 90 on the upper surfaces of the first protective layer 80 and the metal pad 10; after forming the second protective layer 90, forming an under bump metallurgy layer 70 on the metal pad 10 and the second protective layer 90; the second passivation layer 90 has a second opening, the aperture of the second opening is smaller than or equal to the aperture of the first opening, the under bump metallurgy 70 covers at least the bottom surface and the sidewall surface of the second opening, and at least a portion of the under bump metallurgy 70 is disposed in the second opening.

In one embodiment, prior to forming the bump 30, the manufacturing method further includes: forming a first photoresist layer 11 on the semiconductor substrate 20 except for the positions corresponding to the bumps 30 and the first solder layers 40; after forming the bump 30 and the first solder layer 40, the first photoresist layer 11 is removed.

In one embodiment, before forming the metal barrier layer 50, the manufacturing method further includes: forming a first mask layer 12 on the semiconductor substrate 20 on which the first solder layer 40 is formed; photolithography of the first mask layer 12 using a photolithography process to expose portions of the first solder layer 40; etching a portion of the first solder layer 40 using a chemical acid etch process, and then removing the first mask layer 12; forming a second mask layer 13; the second mask layer 13 is etched by photolithography to expose the first solder layer 40, and a metal isolation layer 50 is formed on the first solder layer 40 and the second mask layer 13, wherein the first solder layer 40 is disposed between the metal isolation layer 50 and the bump 30.

In one embodiment, after forming the metal barrier layer 50, the manufacturing method further includes: forming a second photoresist layer 14 on the metal blocking layer 50 at a position corresponding to the first solder layer 40; etching the metal barrier layer 50 at the position not covered by the second photoresist layer 14; removing the second photoresist layer 14; filling the first receiving groove 51 with solder to form a second solder layer 60; the second mask layer 13 is removed.

In one embodiment, after forming the metal barrier layer 50, the manufacturing method further includes: forming a third photoresist layer on the metal blocking layer 50 except the position corresponding to the first solder layer 40; filling the first receiving groove 51 with solder to form a second solder layer 60; removing the third photoresist layer; etching the metal barrier layer 50 at locations not covered by the solder; the second mask layer 13 is removed.

In one embodiment, the method for manufacturing the semiconductor structure comprises the following specific steps:

as shown in fig. 4, a first protection layer 80 is formed on the metal pad 10, a second protection layer 90 is formed on the first protection layer 80 and the upper surface of the metal pad 10 by using a deposition process, an opening is formed in the second protection layer 90 at a position where the bump 30 is prepared in advance by using a photolithography process, and a metal material is deposited on the metal pad 10 and the second protection layer 90 to form an under bump metal layer 70, wherein the under bump metal layer 70 covers the entire second protection layer 90 and covers the opening of the second protection layer 90. The material of the first protection layer 80 may be one or a combination of silicon dioxide and silicon nitride, and the material of the second protection layer 90 may be polyimide. The metal material layer of the under bump metal layer 70 may include a Ti layer, a TiW layer, and a Cu layer, the under bump metal layer 70 is formed on the metal pad 10 and the second passivation layer 90 by Physical Vapor Deposition (PVD), the Ti layer of the under bump metal layer 70 may be used to adhere and block metal copper from entering the semiconductor substrate 20 and the metal pad 10, and the Cu layer of the under bump metal layer 70 may be used as an electrode for forming an electroplated copper pillar (bump 30).

As shown in fig. 5, a first photoresist layer 11 is formed on the second passivation layer 90 except for the positions corresponding to the bumps 30 and the first solder layers 40, i.e., a space for forming the bumps 30 and the first solder layers 40 is reserved in the middle of the first photoresist layer 11, and then the bumps 30 and the first solder layers 40 are electroplated. The first photoresist layer 11 may be a photoresist layer, and after the photoresist layer is coated, the photoresist layer is exposed and developed to form a space for disposing the bump 30 and the first solder layer 40. The material of the first solder layer 40 may be one of lead, tin, and silver or an alloy containing any one of the above solder metals. For example, the material of the first solder layer 40 may be an alloy containing 91.5% to 98.5% of tin and 8.5% to 1.5% of silver. Alternatively, the material of the first solder layer 40 may be an alloy with a tin content of 93.2% to 96.5% and a silver content of 6.8% to 3.5%, the material of the first solder layer 40 may be an alloy with a tin content of 98.2% to 98.5% and a silver content of 1.8% to 1.5%, and the bump 30 is a copper pillar.

As shown in fig. 6, the first photoresist layer 11 is removed after the electroplated bump 30 and the first solder layer 40 are formed.

As shown in fig. 7, a first mask layer 12 is formed on the semiconductor substrate 20 formed with the first solder layer 40, and the first mask layer 12 covers the first solder layer 40 and the under bump metal layer 70. The first mask layer 12 may be a polyimide layer.

As shown in fig. 8, the first mask layer 12 is photolithographically etched to expose portions of the top surface of the first solder layer 40.

As shown in fig. 9, a portion of the first solder layer 40 is etched by chemical acid etching to form a removal space 41.

As shown in fig. 10, the first mask layer 12 is removed.

As shown in fig. 11, a second mask layer 13 is formed, the second mask layer 13 covers the first solder layer 40 and the under bump metal layer 70, the second mask layer 13 is patterned to expose the first solder layer 40, and a metal barrier layer 50 is deposited over the second mask layer 13 and the first solder layer 40 by Physical Vapor Deposition (PVD) technique. The metal barrier layer 50 may be a nickel layer, and an electroplating process is used to increase the thickness of the nickel layer when the metal barrier layer 50 needs to be thickened. Wherein the second mask layer 13 may be a polyimide layer.

As shown in fig. 12, a second photoresist layer 14 is formed on the metal blocking layer 50 at a position corresponding to the first solder layer 40. The second photoresist layer 14 covers the first solder layer 40 and is used as a mask for photolithography of the metal barrier layer 50, and the second photoresist layer 14 can be a photoresist layer.

As shown in fig. 13, the metal material of the metal barrier layer 50 at the position not covered by the second photoresist layer 14 is etched.

As shown in fig. 14, the second photoresist layer 14 is removed to expose the first receiving groove 51 on the metal blocking layer 50.

As shown in fig. 15, the first receiving groove 51 is filled with solder to form a second solder layer 60, and the second solder layer 60 is higher than the metal barrier layer 50. The material of the second solder layer 60 may be one of lead, tin and silver or an alloy containing any one of the above solder metals. For example, the material of the second solder layer 60 may be an alloy containing 91.5% to 98.5% tin and 8.5% to 1.5% silver. Alternatively, the material of the second solder layer 60 may be an alloy containing 93.2% to 96.5% of tin and 6.8% to 3.5% of silver, and the material of the second solder layer 60 may be an alloy containing 98.2% to 98.5% of tin and 1.8% to 1.5% of silver.

As shown in fig. 16, the second mask layer 13 is etched. Then, the under bump metallurgy 70 is etched, and finally, a high temperature reflow process is performed to form a solder bump on the surface of the metal blocking layer 50, so as to form the semiconductor structure shown in fig. 1.

In another embodiment, a method for manufacturing a semiconductor structure includes:

after the fabrication process of fig. 4 to 11 is completed, the metal barrier layer 50 is deposited on the second mask layer 13 and the first solder layer 40 by Physical Vapor Deposition (PVD).

A third photoresist layer is formed on the metal material of the metal blocking layer 50 except for the position corresponding to the first solder layer 40. The third photoresist layer may be a photoresist layer.

The first receiving groove 51 is filled with solder to form a second solder layer 60, and the height of the second solder layer 60 is higher than the metal isolation layer 50 but lower than the third photoresist layer. The material of the solder layer may be one of lead, tin and silver or an alloy containing any one of the above solder metals. For example, the material of the second solder layer 60 may be an alloy containing 91.5% to 98.5% tin and 8.5% to 1.5% silver. Alternatively, the material of the second solder layer 60 may be an alloy containing 93.2% to 96.5% of tin and 6.8% to 3.5% of silver, and the material of the second solder layer 60 may be an alloy containing 98.2% to 98.5% of tin and 1.8% to 1.5% of silver.

Removing the third photoresist layer.

The second mask layer 13 is etched. Then, the under bump metallurgy 70 is etched, and finally, a high temperature reflow process is performed to form a solder bump on the surface of the metal blocking layer 50, so as to form the semiconductor structure shown in fig. 1.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and exemplary embodiments be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate;

the metal bonding pad is arranged on the semiconductor substrate;

the bump is arranged on the metal bonding pad;

the first solder layer is arranged on one side of the bump, which is far away from the metal bonding pad;

the metal blocking layer is arranged on one side, far away from the bump, of the first solder layer, the metal blocking layer is provided with a first accommodating groove and a second accommodating groove which are separated, the notch of the first accommodating groove faces the direction far away from the first solder layer, and the first solder layer is arranged in the second accommodating groove;

the second welding material layer is arranged in the first accommodating groove, and part of the second welding material layer protrudes out of the notch of the first accommodating groove.

2. The semiconductor structure of claim 1, wherein the cross-section of the metal blocking layer is H-shaped.

3. The semiconductor structure of claim 1, wherein the metal stop layer is spaced apart from the bump, and the first solder layer is disposed between the metal stop layer and the bump.

4. The semiconductor structure of claim 1, wherein the first receiving slots each have the second solder layer disposed therein, and wherein the second receiving slots each have the first solder layer disposed therein.

5. The semiconductor structure of any one of claims 1 to 4, wherein the bump is a copper pillar, the semiconductor structure further comprising:

6. The semiconductor structure of claim 5, further comprising:

the first protection layer is arranged on the semiconductor substrate and provided with a first opening, and the first opening exposes part of the metal bonding pad.

7. The semiconductor structure of claim 6, wherein the bumps have a rectangular cross-section, the under-bump metal layers are all located within the first openings, and portions of the bumps are located within the first openings.

8. The semiconductor structure of claim 6, further comprising:

9. The semiconductor structure of claim 8, wherein the bump has a T-shaped cross-section, a small end of the bump being located inside the under-bump metal layer, and a large end of the bump being located outside the under-bump metal layer.

10. The semiconductor structure of claim 9, wherein a portion of the under bump metal layer is located outside the second opening, and a projection of a circumferential outer edge of the under bump metal layer and a circumferential outer edge of the large end of the under bump metal layer on the same plane coincide.