CN112885801A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN112885801A
CN112885801A CN201911205324.8A CN201911205324A CN112885801A CN 112885801 A CN112885801 A CN 112885801A CN 201911205324 A CN201911205324 A CN 201911205324A CN 112885801 A CN112885801 A CN 112885801A
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China
Prior art keywords
layer
metal
solder
bump
forming
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CN201911205324.8A
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Chinese (zh)
Inventor
庄凌艺
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN201911205324.8A priority Critical patent/CN112885801A/en
Publication of CN112885801A publication Critical patent/CN112885801A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure relates to the field of semiconductor technology, and provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a semiconductor substrate, a metal bonding pad, a bump, a first solder layer, a metal blocking layer and a second solder layer, wherein the metal bonding pad is arranged on the semiconductor substrate; the lug is arranged on the metal bonding pad; the first solder layer is arranged on one side of the lug, which is far away from the metal pad; the metal blocking layer is arranged on one side of the first solder layer far away from the bump and is provided with an accommodating groove, and a groove opening of the accommodating groove faces to the direction far away from the first solder layer; the second solder layer is arranged in the accommodating groove, and part of the second solder layer protrudes out of the notch of the accommodating groove. Since the first solder layer and the second solder layer have the property of being stretchable by reflow high-temperature melting, the height adjustment is automatically performed, so that the problem of non-wetting caused by deformation of the packaged substrate after reflow can be reduced.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for manufacturing the same.
Background
With the increasing functionality, performance and integration level of integrated circuits, and the emergence of new types of integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and accounts for an increasing proportion of the value of the entire electronic system. The bump interconnection technology is becoming a key technology for narrow-pitch interconnection of next-generation chips due to its good electrical performance and electromigration resistance.
In the prior art, in the flip chip welding process of a chip, a packaging substrate is heated to warp, the height difference between the chip and the substrate occurs, the solder quantity is insufficient due to tin climbing to cause the non-wetting problem, and the solder quantity is too much to cause the problem of solder bridging between bumps.
Disclosure of Invention
It is a primary object of the present disclosure to overcome at least one of the above-mentioned deficiencies of the prior art and to provide a semiconductor structure and a method for fabricating the same.
According to a first aspect of the present invention, there is provided a semiconductor structure comprising:
a semiconductor substrate;
the metal bonding pad is arranged on the semiconductor substrate;
the bump is arranged on the metal bonding pad;
the first welding flux layer is arranged on one side of the lug, which is far away from the metal pad;
the metal blocking layer is arranged on one side of the first solder layer, which is far away from the bump, and is provided with an accommodating groove, and a notch of the accommodating groove faces to the direction far away from the first solder layer;
the second solder layer is arranged in the accommodating groove, and part of the second solder layer protrudes out of the notch of the accommodating groove.
In an embodiment of the invention, the accommodating grooves are all provided with the second solder layers.
In one embodiment of the present invention, the metal barrier layer has a U-shaped cross-section.
In an embodiment of the invention, the bump is a copper pillar, and the semiconductor structure further includes:
and at least part of the under bump metal layer is clamped between the metal pad and the bump.
In one embodiment of the present invention, the semiconductor structure further comprises:
the first protective layer is arranged on the semiconductor substrate and provided with a first opening, and a part of the metal bonding pad is exposed by the first opening.
In one embodiment of the present invention, the semiconductor structure further comprises:
the second protective layer is arranged on the first protective layer and provided with a second opening, and the caliber of the second opening is smaller than or equal to that of the first opening;
the under bump metal layer at least covers the bottom surface and the side wall surface of the second opening, and at least part of the under bump metal layer is arranged in the second opening.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor structure, comprising:
providing a semiconductor substrate, and forming a metal bonding pad on the semiconductor substrate;
forming a bump on the metal pad;
forming a first solder layer on one side of the bump away from the metal pad;
forming a metal blocking layer on one side of the first solder layer, which is far away from the bump, wherein the metal blocking layer is provided with an accommodating groove, and a notch of the accommodating groove faces to the direction far away from the first solder layer;
a second solder layer is formed in the receiving groove such that a portion of the second solder layer protrudes out of the notch of the receiving groove.
In an embodiment of the invention, before forming the bump, the manufacturing method further includes:
forming an under bump metal layer on the metal pad;
at least part of the under bump metal layer is clamped between the metal pad and the bump.
In an embodiment of the invention, before forming the bump, the manufacturing method further includes:
forming a first protective layer on a semiconductor substrate;
the first protective layer is provided with a first opening, and a part of the metal bonding pad is exposed by the first opening.
In one embodiment of the present invention, after forming the first protective layer, the manufacturing method further includes:
forming a second protective layer on the first protective layer and the upper surface of the metal pad;
after forming the second protective layer, forming an under bump metal layer on the metal pad and the second protective layer;
the second protective layer is provided with a second opening, the caliber of the second opening is smaller than or equal to that of the first opening, the under-bump metal layer at least covers the bottom surface and the side wall surface of the second opening, and at least part of the under-bump metal layer is arranged in the second opening.
In an embodiment of the invention, before forming the bump, the manufacturing method further includes:
forming a first photoresist layer on the semiconductor substrate except for the positions corresponding to the bumps and the first solder layer;
after forming the bump and the first solder layer, the first photoresist layer is removed.
In one embodiment of the present invention, before forming the metal barrier layer, the manufacturing method further includes:
forming a mask layer on the semiconductor substrate on which the first solder layer is formed;
and photoetching the mask layer by adopting a photoetching process to expose the first solder layer, and forming a metal barrier layer on the first solder layer and the mask layer.
In one embodiment of the present invention, after the forming the metal barrier layer, the manufacturing method further includes:
forming a second photoresist layer on the metal barrier layer at a position corresponding to the first solder layer;
etching the metal barrier layer at the position not covered by the second photoresist layer;
removing the second photoresist layer;
filling solder in the accommodating groove to form a second solder layer;
and removing the mask layer.
In one embodiment of the present invention, after the forming the metal barrier layer, the manufacturing method further includes:
forming a third photoresist layer on the metal barrier layer except the position corresponding to the first solder layer;
filling solder in the accommodating groove to form a second solder layer;
removing the third photoresist layer;
etching the metal barrier layer at the position not covered by the solder;
and removing the mask layer.
The semiconductor structure comprises a semiconductor substrate, a metal bonding pad, a bump, a first solder layer, a metal blocking layer and a second solder layer, wherein the second solder layer and the first solder layer are respectively arranged on the upper side and the lower side of the metal blocking layer, the second solder layer is arranged in the accommodating groove of the metal blocking layer, and the second solder layer is wrapped in the metal blocking layer, so that the non-wetting problem caused by insufficient solder amount and the solder bridging problem caused by too much solder amount in the flip chip welding process can be solved.
Drawings
Various objects, features and advantages of the present disclosure will become more apparent from the following detailed description of preferred embodiments thereof, when considered in conjunction with the accompanying drawings. The drawings are merely exemplary illustrations of the disclosure and are not necessarily drawn to scale. In the drawings, like reference characters designate the same or similar parts throughout the different views. Wherein:
FIG. 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment;
FIG. 2 is a schematic diagram of a semiconductor structure according to another exemplary embodiment;
FIG. 3 is a schematic diagram illustrating an assembly of a semiconductor structure and a package substrate according to an exemplary embodiment;
FIG. 4 is a schematic diagram illustrating a semiconductor structure after an under bump metallurgy layer is formed using a method for fabricating the semiconductor structure, in accordance with one exemplary embodiment;
FIG. 5 is a schematic diagram illustrating a structure after a first solder layer is formed using a method of fabricating a semiconductor structure according to an exemplary embodiment;
FIG. 6 is a schematic diagram illustrating a method of fabricating a semiconductor structure after removing a first layer of photoresist, according to an exemplary embodiment;
FIG. 7 is a schematic diagram illustrating a structure after photolithography of a masking layer using a method of fabricating a semiconductor structure, according to an exemplary embodiment;
FIG. 8 is a schematic diagram illustrating a structure after a metal barrier layer is formed using a method of fabricating a semiconductor structure, according to an exemplary embodiment;
FIG. 9 is a schematic diagram illustrating a second photoresist layer formed by a method for forming a semiconductor structure in accordance with one exemplary embodiment;
FIG. 10 is a schematic diagram illustrating a structure after etching a metal barrier layer using a method of fabricating a semiconductor structure, according to an exemplary embodiment;
FIG. 11 is a schematic diagram illustrating a method of fabricating a semiconductor structure after removing a second layer of photoresist, in accordance with one illustrative embodiment;
fig. 12 is a schematic structural view after a second solder layer is formed by a method of manufacturing a semiconductor structure according to an exemplary embodiment;
FIG. 13 is a schematic diagram illustrating a structure after etching a mask layer using a method for fabricating a semiconductor structure, in accordance with one exemplary embodiment;
FIG. 14 is a schematic structural view after a third photoresist layer is formed using a method for fabricating a semiconductor structure, in accordance with another exemplary embodiment;
fig. 15 is a schematic structural view after a second solder layer is formed by a method of manufacturing a semiconductor structure according to another exemplary embodiment;
FIG. 16 is a schematic diagram illustrating a method of fabricating a semiconductor structure after removing a third layer of photoresist, in accordance with another exemplary embodiment;
fig. 17 is a schematic diagram illustrating a structure after etching an under bump metallurgy layer using a method for fabricating a semiconductor structure according to another exemplary embodiment.
The reference numerals are explained below:
1. a package substrate; 10. a metal pad; 11. a first photoresist layer; 12. a mask layer; 13. a second photoresist layer; 14. a third photoresist layer; 20. a semiconductor substrate; 30. a bump; 40. a first solder layer; 50. a metal barrier layer; 51. accommodating grooves; 60. a second solder layer; 70. a metal layer under the bump; 80. a first protective layer; 90. and a second protective layer.
Detailed Description
Exemplary embodiments that embody features and advantages of the present disclosure are described in detail below in the specification. It is to be understood that the disclosure is capable of various modifications in various embodiments without departing from the scope of the disclosure, and that the description and drawings are to be regarded as illustrative in nature, and not as restrictive.
In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary structures, systems, and steps in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various example features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples in the figures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of this disclosure.
An embodiment of the present invention provides a semiconductor structure, referring to fig. 1 and fig. 2, the semiconductor structure includes: a semiconductor substrate 20; a metal pad 10 disposed on the semiconductor substrate 20; a bump 30 disposed on the metal pad 10; a first solder layer 40 disposed on a side of the bump 30 away from the metal pad 10; the metal blocking layer 50 is arranged on one side of the first solder layer 40 far away from the bump 30, the metal blocking layer 50 is provided with a containing groove 51, and a notch of the containing groove 51 faces to the direction far away from the first solder layer 40; the second solder layer 60 is disposed in the receiving groove 51, and a portion of the second solder layer 60 protrudes out of the notch of the receiving groove 51.
In the semiconductor structure according to an embodiment of the present invention, the metal pad 10 is disposed on the upper surface of the semiconductor substrate 20, and then the bump 30, the first solder layer 40, the metal blocking layer 50, and the second solder layer 60 are sequentially disposed upward. Since the second solder layer 60 is wrapped in the metal barrier layer 50, the problems of non-wetting caused by insufficient solder amount during tin climbing and solder bridging caused by too much solder amount during flip chip soldering can be improved.
In one embodiment, as shown in fig. 3, the semiconductor structure is a stretchable metal, and the package substrate 1 is warped by heating during the flip chip bonding process, and the first solder layer 40 has the property of being stretchable by reflowing and melting at high temperature, so that the height adjustment is automatically performed, and the non-wetting problem caused by the deformation of the package substrate 1 after reflow can be reduced.
In one embodiment, the receiving groove 51 of the metal blocking layer 50 has only one opening, that is, the side wall and the bottom wall of the receiving groove 51 form a semi-closed groove, and the opening of the receiving groove 51 faces the direction away from the first solder layer 40, so as to wrap the second solder layer 60, and the receiving groove 51 can limit the second solder layer 60 from diffusing to the first solder layer 40, and due to the wrapping effect of the receiving groove 51, the second solder layer 60 does not diffuse in a large amount, thereby avoiding the solder bridging problem.
In one embodiment, first solder layer 40 and second solder layer 60 may be one of lead, tin, and silver or an alloy containing any of the solder metals described above. For example, the material of first solder layer 40, and/or second solder layer 60 may be an alloy containing 91.5% to 98.5% tin and 8.5% to 1.5% silver. Alternatively, the material of first solder layer 40, and/or second solder layer 60 may be an alloy containing 93.2% to 96.5% tin and 6.8% to 3.5% silver, and the material of first solder layer 40, and/or second solder layer 60 may be an alloy containing 98.2% to 98.5% tin and 1.8% to 1.5% silver.
In one embodiment, the semiconductor base 20 includes a semiconductor substrate and a number of IC lines and insulating layers. The material of the metal pad 10 may be, but is not limited to, aluminum or copper.
In one embodiment, the accommodating grooves 51 are each provided therein with a second solder layer 60. The portion of the second solder layer 60 protruding the receiving groove 51 may cover a partial upper surface of the metal barrier layer 50, or completely cover the upper surface of the metal barrier layer 50, and does not exclude completely not cover the upper surface of the metal barrier layer 50.
In one embodiment, the metal barrier layer 50 is U-shaped in cross-section. The cross section of the metal blocking layer 50 may be understood as a longitudinal cross section of the metal blocking layer 50 with reference to fig. 1 and 2.
In one embodiment, the material of the metal barrier layer 50 may include nickel. The specific shape of the metal barrier layer 50 may be bowl-shaped. For example, the structure can be a structure which has arc-shaped side walls and a circular bottom and encloses a containing cavity with an opening. The receiving cavity is a receiving groove 51.
In one embodiment, the bump 30 is a copper pillar, and the semiconductor structure further includes: and an under bump metal layer 70, at least a part of the under bump metal layer 70 being sandwiched between the metal pad 10 and the bump 30. The metal material layer of the under bump metallurgy 70 may include a Ti layer, a TiW layer, and a Cu layer. The under bump metallurgy 70 is electrically connected to the metal pad 10. The under bump metallurgy 70 makes the bump 30 not directly contact with the metal pad 10.
In one embodiment, the semiconductor structure further comprises: the first protection layer 80 is disposed on the semiconductor substrate 20, the first protection layer 80 has a first opening, and a portion of the metal pad 10 is exposed by the first opening, that is, the first protection layer 80 covers a circumferential outer edge of the metal pad 10. The material of the first protection layer 80 may be one or a combination of silicon dioxide and silicon nitride.
In one embodiment, the first protective layer 80 covers a portion of the metal pad 10 and a region of the semiconductor substrate 20 outside the metal pad 10.
In one embodiment, the semiconductor structure further comprises: a second passivation layer 90 disposed on the first passivation layer 80, the second passivation layer 90 having a second opening, wherein the aperture of the second opening is smaller than or equal to the aperture of the first opening; the under bump metal layer 70 at least covers the bottom surface and the sidewall surface of the second opening, and at least a portion of the under bump metal layer 70 is disposed in the second opening. The material of the second protective layer 90 may be polyimide.
In one embodiment, the under bump metallurgy 70 is disposed on a portion of the second protective layer 90 and the exposed metal pad 10. In one embodiment, the under bump metallurgy 70 may wrap the bumps 30, that is, the bumps 30 are all located in the open cavities formed by the under bump metallurgy 70, and the plane of the notches of the under bump metallurgy 70 is on the same plane as the bottom surface of the first solder layer 40.
In one embodiment, as shown in fig. 1, the semiconductor structure is composed of a semiconductor substrate 20, a metal pad 10, a bump 30, a first solder layer 40, a metal blocking layer 50, a second solder layer 60, an under bump metal layer 70, a first protection layer 80 and a second protection layer 90, wherein the first protection layer 80 covers the metal pad 10 and blocks a portion of the metal pad 10, the second protection layer 90 is disposed on the first protection layer 80 and covers a portion of the metal pad 10, and the second protection layer 90 and the first protection layer 80 cover the metal pad 10 in opposite positions, i.e., the first protection layer 80 is disposed under the second protection layer 90. The second protective layer 90 does not cover the middle of the metal pad 10, and the under bump metallurgy 70 arranges metal material layers such as a Ti layer, a TiW layer, and a Cu layer on the second protective layer 90 and the metal pad 10 by physical vapor deposition, and the Ti layer can adhere and block metal copper from entering the semiconductor substrate 20, and the Cu layer can form an electroplated electrode. The bump 30 has a T-shaped cross section, i.e., the small end is located inside the under bump metallurgy 70, and the large end is located outside the under bump metallurgy 70.
In another embodiment, as shown in fig. 2, the semiconductor structure is composed of a semiconductor substrate 20, a metal pad 10, a bump 30, a first solder layer 40, a metal blocking layer 50, a second solder layer 60, an under bump metal layer 70, and a first protection layer 80, wherein the first protection layer 80 covers the metal pad 10 and shields a portion of the metal pad 10. The under bump metallurgy 70 is formed by disposing metal material layers such as Ti layer, TiW layer, and Cu layer on the metal pad 10 by physical vapor deposition, and the Ti layer can adhere and block metal copper from entering the semiconductor substrate 20, and the Cu layer can form an electroplated electrode. The bump 30 has a rectangular cross section, and the bump 30 is located between the under bump metallurgy 70 and the first solder layer 40.
An embodiment of the present invention also provides a method for manufacturing a semiconductor structure, including: providing a semiconductor substrate 20, and forming a metal pad 10 on the semiconductor substrate 20; forming a bump 30 on the metal pad 10; forming a first solder layer 40 on a side of the bump 30 away from the metal pad 10; forming a metal barrier layer 50 on a side of the first solder layer 40 away from the bump 30, wherein the metal barrier layer 50 has a receiving groove 51, and a notch of the receiving groove 51 faces a direction away from the first solder layer 40; the second solder layer 60 is formed in the receiving groove 51, and a portion of the second solder layer 60 is made to protrude from the notch of the receiving groove 51.
In one embodiment, prior to forming the bump 30, the manufacturing method further includes: forming an under bump metallurgy layer 70 on the metal pad 10; at least a portion of the under bump metal layer 70 is sandwiched between the metal pad 10 and the bump 30.
In one embodiment, prior to forming the bump 30, the manufacturing method further includes: forming a first protective layer 80 on the semiconductor substrate 20; the first protection layer 80 has a first opening, and the first opening exposes a portion of the metal pad 10.
In one embodiment, after forming the first protection layer 80, the manufacturing method further includes: forming a second protective layer 90 on the upper surfaces of the first protective layer 80 and the metal pad 10; after forming the second protective layer 90, forming an under bump metallurgy layer 70 on the metal pad 10 and the second protective layer 90; the second passivation layer 90 has a second opening, the aperture of the second opening is smaller than or equal to the aperture of the first opening, the under bump metallurgy 70 covers at least the bottom surface and the sidewall surface of the second opening, and at least a portion of the under bump metallurgy 70 is disposed in the second opening.
In one embodiment, prior to forming the bump 30, the manufacturing method further includes: forming a first photoresist layer 11 on the semiconductor substrate 20 except for the positions corresponding to the bumps 30 and the first solder layers 40; after forming the bump 30 and the first solder layer 40, the first photoresist layer 11 is removed.
In one embodiment, before forming the metal barrier layer 50, the manufacturing method further includes: forming a mask layer 12 on the semiconductor substrate 20 on which the first solder layer 40 is formed; the mask layer 12 is etched using a photolithography process to expose the first solder layer 40, and a metal blocking layer 50 is formed on the first solder layer 40 and the mask layer 12.
In one embodiment, after forming the metal barrier layer 50, the manufacturing method further includes: forming a second photoresist layer 13 on the metal blocking layer 50 at a position corresponding to the first solder layer 40; etching the metal barrier layer 50 at the position not covered by the second photoresist layer 13; removing the second photoresist layer 13; filling the accommodating groove 51 with solder to form a second solder layer 60; the mask layer 12 is removed.
In one embodiment, after forming the metal barrier layer 50, the manufacturing method further includes: forming a third photoresist layer 14 on the metal blocking layer 50 except for the position corresponding to the first solder layer 40; filling the accommodating groove 51 with solder to form a second solder layer 60; removing the third photoresist layer 14; etching the metal barrier layer 50 at locations not covered by the solder; the mask layer 12 is removed.
In one embodiment, the method for manufacturing the semiconductor structure comprises the following specific steps:
as shown in fig. 4, a first protection layer 80 is formed on the metal pad 10, a second protection layer 90 is formed on the first protection layer 80 and the upper surface of the metal pad 10 by using a deposition process, an opening is formed in the second protection layer 90 at a position where the bump 30 is prepared in advance by using a photolithography process, and a metal material is deposited on the metal pad 10 and the second protection layer 90 to form an under bump metal layer 70, wherein the under bump metal layer 70 covers the entire second protection layer 90 and covers the opening of the second protection layer 90. The material of the first protection layer 80 may be one or a combination of silicon dioxide and silicon nitride, and the material of the second protection layer 90 may be polyimide. The metal material layer of the under bump metal layer 70 may include a Ti layer, a TiW layer, and a Cu layer, the under bump metal layer 70 is formed on the metal pad 10 and the second passivation layer 90 by Physical Vapor Deposition (PVD), the Ti layer of the under bump metal layer 70 may be used to adhere and block metal copper from entering the semiconductor substrate 20 and the metal pad 10, and the Cu layer of the under bump metal layer 70 may be used as an electrode for forming an electroplated copper pillar (bump 30).
As shown in fig. 5, a first photoresist layer 11 is formed on the second passivation layer 90 except for the positions corresponding to the bumps 30 and the first solder layers 40, i.e., a space for forming the bumps 30 and the first solder layers 40 is reserved in the middle of the first photoresist layer 11, and then the bumps 30 and the first solder layers 40 are electroplated. The first photoresist layer 11 may be a photoresist layer, and after the photoresist layer is coated, the photoresist layer is exposed and developed to form a space for disposing the bump 30 and the first solder layer 40. The material of the first solder layer 40 may be one of lead, tin, and silver or an alloy containing any one of the above solder metals. For example, the material of the first solder layer 40 may be an alloy containing 91.5% to 98.5% of tin and 8.5% to 1.5% of silver. Alternatively, the material of the first solder layer 40 may be an alloy with a tin content of 93.2% to 96.5% and a silver content of 6.8% to 3.5%, the material of the first solder layer 40 may be an alloy with a tin content of 98.2% to 98.5% and a silver content of 1.8% to 1.5%, and the bump 30 is a copper pillar.
As shown in fig. 6, the first photoresist layer 11 is removed after the electroplated bump 30 and the first solder layer 40 are formed.
As shown in fig. 7, a mask layer 12 is formed on the semiconductor substrate 20 on which the first solder layer 40 is formed, and the mask layer 12 is lithographed to expose the top surface of the first solder layer 40. The mask layer 12 may be a polyimide layer.
As shown in fig. 8, a metal barrier layer 50 is deposited over the mask layer 12 and the first solder layer 40 by Physical Vapor Deposition (PVD) technique. The metal barrier layer 50 may be a nickel layer, and an electroplating process is used to increase the thickness of the nickel layer when the metal barrier layer 50 needs to be thickened.
As shown in fig. 9, a second photoresist layer 13 is formed on the metal blocking layer 50 at a position corresponding to the first solder layer 40. The second photoresist layer 13 covers the top of the first solder layer 40, and serves as a mask for photolithography of the metal barrier layer 50, and the second photoresist layer 13 may be a photoresist layer.
As shown in fig. 10, the metal material of the metal barrier layer 50 at the position not covered by the second photoresist layer 13 is etched.
As shown in fig. 11, the second photoresist layer 13 is removed to expose the accommodating groove 51 on the metal barrier layer 50.
As shown in fig. 12, the accommodating groove 51 is filled with solder to form a second solder layer 60, and the second solder layer 60 is higher than the metal barrier layer 50. The material of the second solder layer 60 may be one of lead, tin and silver or an alloy containing any one of the above solder metals. For example, the material of the second solder layer 60 may be an alloy containing 91.5% to 98.5% tin and 8.5% to 1.5% silver. Alternatively, the material of the second solder layer 60 may be an alloy containing 93.2% to 96.5% of tin and 6.8% to 3.5% of silver, and the material of the second solder layer 60 may be an alloy containing 98.2% to 98.5% of tin and 1.8% to 1.5% of silver.
As shown in fig. 13, the mask layer 12 is etched. Then, the under bump metallurgy 70 is etched, and finally, a high temperature reflow process is performed to form a solder bump on the surface of the metal blocking layer 50, so as to form the semiconductor structure shown in fig. 1.
In another embodiment, a method for manufacturing a semiconductor structure includes:
after the fabrication process of fig. 4 to 8 is completed, the metal barrier layer 50 is deposited on the mask layer 12 and the first solder layer 40 by Physical Vapor Deposition (PVD) technique.
As shown in fig. 14, a third photoresist layer 14 is formed on the metal material of the metal blocking layer 50 except at the position corresponding to the first solder layer 40. The third photoresist layer 14 may be a photoresist layer.
As shown in fig. 15, the accommodating groove 51 is filled with solder to form a second solder layer 60, and the height of the second solder layer 60 is higher than the metal blocking layer 50 but lower than the third photoresist layer 14. The material of the solder layer may be one of lead, tin and silver or an alloy containing any one of the above solder metals. For example, the material of the second solder layer 60 may be an alloy containing 91.5% to 98.5% tin and 8.5% to 1.5% silver. Alternatively, the material of the second solder layer 60 may be an alloy containing 93.2% to 96.5% of tin and 6.8% to 3.5% of silver, and the material of the second solder layer 60 may be an alloy containing 98.2% to 98.5% of tin and 1.8% to 1.5% of silver.
As shown in fig. 16, the third photoresist layer 14 is removed.
As shown in fig. 17, the mask layer 12 is etched. Then, the under bump metallurgy 70 is etched, and finally, a high temperature reflow process is performed to form a solder bump on the surface of the metal blocking layer 50, so as to form the semiconductor structure shown in fig. 1.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and exemplary embodiments be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.

Claims (14)

1. A semiconductor structure, comprising:
a semiconductor substrate;
the metal bonding pad is arranged on the semiconductor substrate;
the bump is arranged on the metal bonding pad;
the first solder layer is arranged on one side of the bump, which is far away from the metal bonding pad;
the metal blocking layer is arranged on one side, far away from the bump, of the first solder layer and provided with an accommodating groove, and a notch of the accommodating groove faces to the direction far away from the first solder layer;
the second solder layer is arranged in the accommodating groove, and part of the second solder layer protrudes out of the notch of the accommodating groove.
2. The semiconductor structure of claim 1, wherein the receiving grooves are all provided with the second solder layer therein.
3. The semiconductor structure of claim 1, wherein the metal blocking layer has a U-shaped cross-section.
4. The semiconductor structure of any one of claims 1 to 3, wherein the bump is a copper pillar, the semiconductor structure further comprising:
and at least part of the under bump metal layer is clamped between the metal pad and the bump.
5. The semiconductor structure of claim 4, further comprising:
the first protection layer is arranged on the semiconductor substrate and provided with a first opening, and the first opening exposes part of the metal bonding pad.
6. The semiconductor structure of claim 5, further comprising:
the second protective layer is arranged on the first protective layer and provided with a second opening, and the caliber of the second opening is smaller than or equal to that of the first opening;
the under bump metal layer at least covers the bottom surface and the side wall surface of the second opening, and at least part of the under bump metal layer is arranged in the second opening.
7. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, and forming a metal pad on the semiconductor substrate;
forming a bump on the metal pad;
forming a first solder layer on one side of the bump away from the metal pad;
forming a metal blocking layer on one side of the first solder layer, which is far away from the bump, wherein the metal blocking layer is provided with a containing groove, and a notch of the containing groove faces to the direction far away from the first solder layer;
a second solder layer is formed within the receiving groove and a portion of the second solder layer is caused to protrude out of the notch of the receiving groove.
8. The method of manufacturing according to claim 7, wherein before forming the bump, the method of manufacturing further comprises:
forming an under bump metal layer on the metal pad;
at least part of the under bump metal layer is clamped between the metal pad and the bump.
9. The method of manufacturing according to claim 8, wherein before forming the bump, the method of manufacturing further comprises:
forming a first protective layer on the semiconductor substrate;
the first protection layer is provided with a first opening, and the first opening exposes a part of the metal bonding pad.
10. The manufacturing method according to claim 9, wherein after forming the first protective layer, the manufacturing method further comprises:
forming a second protective layer on the first protective layer and the upper surface of the metal pad;
forming the under bump metallurgy layer on the metal pad and the second protective layer after forming the second protective layer;
the second protective layer is provided with a second opening, the caliber of the second opening is smaller than or equal to that of the first opening, the under-bump metal layer at least covers the bottom surface and the side wall surface of the second opening, and at least part of the under-bump metal layer is arranged in the second opening.
11. The manufacturing method according to any one of claims 7 to 10, wherein before forming the bump, the manufacturing method further comprises:
forming a first photoresist layer on the semiconductor substrate except for the positions corresponding to the bumps and the first solder layer;
and after the bump and the first solder layer are formed, removing the first photoresist layer.
12. The manufacturing method according to any one of claims 7 to 10, characterized in that, before forming the metal barrier layer, the manufacturing method further comprises:
forming a mask layer on the semiconductor substrate on which the first solder layer is formed;
and photoetching the mask layer by adopting a photoetching process to expose the first solder layer, and forming the metal barrier layer on the first solder layer and the mask layer.
13. The manufacturing method according to claim 12, wherein after the forming of the metal barrier layer, the manufacturing method further comprises:
forming a second photoresist layer on the metal barrier layer at a position corresponding to the first solder layer;
etching the metal barrier layer at the position not covered by the second photoresist layer;
removing the second photoresist layer;
filling solder in the accommodating groove to form the second solder layer;
and removing the mask layer.
14. The manufacturing method according to claim 12, wherein after the forming of the metal barrier layer, the manufacturing method further comprises:
forming a third photoresist layer on the metal barrier layer except the position corresponding to the first solder layer;
filling solder in the accommodating groove to form the second solder layer;
removing the third photoresist layer;
etching the metal barrier layer at the position not covered by the solder;
and removing the mask layer.
CN201911205324.8A 2019-11-29 2019-11-29 Semiconductor structure and manufacturing method thereof Pending CN112885801A (en)

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Application Number Priority Date Filing Date Title
CN201911205324.8A CN112885801A (en) 2019-11-29 2019-11-29 Semiconductor structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911205324.8A CN112885801A (en) 2019-11-29 2019-11-29 Semiconductor structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN112885801A true CN112885801A (en) 2021-06-01

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Country Status (1)

Country Link
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