CN210639218U

CN210639218U - Phase testing device of relay protection device

Info

Publication number: CN210639218U
Application number: CN201921452036.8U
Authority: CN
Inventors: 鲍斌; 刘家庆; 孙正伟; 王开白; 阴宏民; 刘庆伟; 廖晓春; 范凯; 陶宇超; 孙雨桐; 陶冶; 曲欣瑶; 李丹; 贲驰; 孙羽; 曾令森; 王慧琼; 高学强; 邓碧青; 常靖松
Original assignee: Wuhan Huadian Shuncheng Technology Co ltd; Northeast Branch Of State Grid Corp Of China; Hohai University HHU
Current assignee: Wuhan Huadian Shuncheng Technology Co ltd; Northeast Branch Of State Grid Corp Of China; Hohai University HHU
Priority date: 2019-09-03
Filing date: 2019-09-03
Publication date: 2020-05-29
Anticipated expiration: 2029-09-03

Abstract

The utility model provides a phase test device of relay protection device, through set up the gain amplifier able to programme in signal conditioning circuit, can adjust the magnification, it has characteristics such as low offset voltage, low input bias current, low temperature drift and higher common mode rejection ratio, has certain inhibitory action to high frequency interference; by arranging the sampling retainer, analog quantity signals input in the A/D conversion process can be ensured not to change, synchronous sampling of each channel is ensured, the phase relation of each analog quantity is kept unchanged before and after sampling, and because the circuit structures of each signal processing circuit are the same, synchronous acquisition of current and voltage can be realized; different channel signals are loaded through the analog switch to select one group of voltage signals and current signals, and the selected voltage signals and the current signals are sent to the A/D converter for processing, so that the circuit structure is simplified, and the integration level of the circuit is improved.

Description

Phase testing device of relay protection device

Technical Field

The utility model relates to a relay protection technical field especially relates to a relay protection device phase place testing arrangement.

Background

The traditional relay protection and instrument analog quantity input adopt cables to transmit analog quantities of secondary voltage and current, and primary current and voltage are respectively converted into analog quantities of secondary current and secondary voltage through a current transformer and a voltage transformer. The analog quantity is transmitted to the relay protection device through conversion or directly through an A/D interface of the relay protection device. And the relay protection device determines whether to trip or not through calculation and analysis of data. If tripping is needed, the relay outputs the switching value to the intelligent operation box, and tripping operation of the circuit breaker is achieved. And after tripping, the intelligent circuit breaker returns to the current state and transmits the current state to the intelligent operation box, and then the current state is transmitted to the input quantity input simulation module for receiving, and whether a correct tripping action is performed or not is judged.

Relay protection is an important secondary device in an electric power system, and can ensure safe and reliable operation of the electric power system, so that periodic detection of a relay protection device is required. The relay protection device can ensure the wiring correctness of the alternating current input circuit of the protection device only if the phase measurement is correct, and can be put into operation after the test is correct. The principle of the phase testing device of the relay protection device is that voltage or current is respectively added on the primary sides of a current transformer and a voltage transformer, voltage, current phase and amplitude control is utilized to simulate line and transformer load voltage and current, transformer protection, bus protection and line protection are commonly used, when protection is carried out, the phase of a current signal or a voltage signal on the current transformer or the voltage transformer is usually detected, but the collected current signal and the collected voltage signal in the existing phase testing device of the relay protection device are generally only subjected to amplification and filtering processing, the collected current signal and the collected voltage signal have large high-frequency components and are asynchronous in current signal collection or voltage signal collection, and the testing precision of the phase testing device of the relay protection device is not high. Therefore, for solving the above problem, the utility model provides a relay protection device phase testing device can synchronous acquisition electric current or voltage, and the high frequency composition among the eliminating circuit improves and detects the precision.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a relay protection device phase place testing arrangement can synchronous acquisition electric current or voltage, high frequency component among the elimination circuit, improves and detects the precision.

The technical scheme of the utility model is realized like this: the utility model provides a phase test device of a relay protection device, which comprises two alternating current sources, an alternating current voltage source, a voltage transformer, a current transformer, a multi-path analog quantity acquisition unit, a switching value input unit, a switching value output unit and a processor, wherein the analog quantity acquisition unit comprises a signal conditioning circuit, a low-pass filter, a sampling retainer, an analog switch and an A/D converter which are electrically connected in sequence;

the current transformer and the voltage transformer are connected on a bus in parallel, a PWM interface of the processor is respectively electrically connected with control ends of an alternating current source and an alternating current voltage source, an output end of the alternating current source is electrically connected with a primary side of the current transformer, an output end of the alternating current voltage source is electrically connected with a primary side of the voltage transformer, a secondary side of the current transformer and a secondary side of the voltage transformer are respectively electrically connected with input ends of two paths of signal conditioning circuits in a one-to-one correspondence manner, a digital output port of the A/D converter is electrically connected with the PWM interface of the processor, an output end of the switching value input unit is electrically connected with the processor, and an input end of the switching value output unit.

On the basis of the above technical solution, preferably, the signal conditioning circuit includes resistors R47-R49, a capacitor C32, an operational amplifier OPA2277, and a PGA205 amplifier;

the inverting input end of the operational amplifier OPA2277 is electrically connected with the secondary side of the current transformer or the secondary side of the voltage transformer, the non-inverting input end of the operational amplifier OPA2277 is grounded through a resistor R48, a resistor R47 is connected between the inverting input end of the operational amplifier OPA2277 and the output end of the operational amplifier OPA2277 in parallel, the output end of the operational amplifier OPA2277 is electrically connected with the VIN + pin of the PGA205 amplifier through a resistor R48, one end of a capacitor C32 is electrically connected with the VIN + pin of the PGA205 amplifier, the other end of the capacitor C32 is grounded, the VIN-pin of the PGA205 amplifier is grounded, and the VO pin of.

Further preferably, the low-pass filter comprises a resistor R50 and a capacitor C35;

the VO pin of the PGA205 amplifier is electrically connected to the input terminal of the sample-and-hold device through a resistor R50, one end of a capacitor C35 is electrically connected to the input terminal of the sample-and-hold device, and the other end of the capacitor C35 is grounded.

Further preferably, the sample holder comprises an LF198 chip, a resistor R51, a resistor R52, an adjustable resistor R23 and a capacitor C36;

the VO pin of the PGA205 amplifier is electrically connected with the IN pin of the LF198 chip through a resistor R50, the LOGIC pin of the LF198 chip is grounded through a resistor R52, the LOGIC REF pin of the LF198 chip is grounded, the OFFSET ADJ pin of the LF198 chip is electrically connected with a sliding sheet of an adjustable resistor R23, one end of the adjustable resistor R23 is grounded, the other end of the adjustable resistor R23 is electrically connected with a power supply, the CH pin of the LF198 chip is grounded through a capacitor C36, and the OUT pin of the LF198 chip is electrically connected with the input end of the analog switch.

Further preferably, the analog switch comprises an AD7503 chip;

pins A0, A1, A2 and EN of the AD7503 chip are electrically connected with I/O ports of the processor in a one-to-one correspondence mode, a pin S5 of the AD7503 chip is electrically connected with a pin OUT of the LF198 chip, and the pin OUT of the AD7503 chip is electrically connected with a simulation input port of the A/D converter.

Further preferably, the A/D converter comprises an ADS8556 chip;

the CH _ A0 pin of the ADS8556 chip is electrically connected with the OUT pin of the AD7503 chip, and the DB0-DB15 pins of the ADS8556 chip are electrically connected with the I/O ports of the processor in a one-to-one correspondence mode.

Further preferably, the processor comprises a TMS320F2812 chip;

pins IOA0-IOA15 of the TMS320F2812 chip are electrically connected with pins DB0-DB15 of the ADS8556 chip in a one-to-one corresponding mode, pins IOF7, IOF6 and XINT of the TMS320F2812 chip are electrically connected with pins CS, RESET and BUSY of the ADS8556 chip in a one-to-one corresponding mode, pins IOD0 of the TMS320F2812 chip are electrically connected with pins RD, CONVSTA, CONVSTB and CONVSTC of the ADS8556 chip in a one-to-one corresponding mode, and pins GPIOA0_ PWM1, GPIOA1_ PWM2, GPIOA2_ PWM3 and GPIOA3_ PWM4 of the TMS320F2812 chip are electrically connected with pins A0, A1, A2 and EN of the AD7503 chip in a one-to one mode.

On the basis of the above technical solution, preferably, the maximum output capacity of the ac current source is 300A, and the maximum output capacity of the ac voltage source is 10 kV.

The utility model discloses a relay protection device phase place testing arrangement has following beneficial effect for prior art:

(1) the programmable gain amplifier is arranged in the signal conditioning circuit, so that the amplification factor can be adjusted, and the signal conditioning circuit has the characteristics of low offset voltage, low input bias current, low temperature drift, higher common-mode rejection ratio and the like, and has a certain inhibition effect on high-frequency interference;

(2) by arranging the sampling retainer, analog quantity signals input in the A/D conversion process can be ensured not to change, synchronous sampling of each channel is ensured, the phase relation of each analog quantity is kept unchanged before and after sampling, and because the circuit structures of each signal processing circuit are the same, synchronous acquisition of current and voltage can be realized;

(3) different channel signals are loaded through the analog switch to select one group of voltage signals and current signals, and the selected voltage signals and the current signals are sent to the A/D converter for processing, so that the circuit structure is simplified, and the integration level of the circuit is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a structural diagram of a phase testing device of a relay protection device according to the present invention;

fig. 2 is a circuit diagram of a signal conditioning circuit in a phase testing device of a relay protection device according to the present invention;

fig. 3 is a circuit diagram of the connection between the sampling keeper and the analog switch in the phase testing device of the relay protection device of the present invention;

fig. 4 is a circuit diagram of an a/D converter in a phase testing device of a relay protection device according to the present invention;

fig. 5 is a schematic diagram of the connection between the processor and the a/D converter and the analog switch in the phase testing apparatus of the relay protection apparatus of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.

As shown in fig. 1, the utility model discloses a relay protection device phase testing device, it includes two alternating current source, an alternating current voltage source, voltage transformer, current transformer, analog quantity acquisition unit, switching value input unit, switching value output unit and treater. The current transformer and the voltage transformer are connected on a bus in parallel, a PWM interface of the processor is respectively electrically connected with control ends of an alternating current source and an alternating current voltage source, an output end of the alternating current source is electrically connected with a primary side of the current transformer, an output end of the alternating current voltage source is electrically connected with a primary side of the voltage transformer, a secondary side of the current transformer and a secondary side of the voltage transformer are electrically connected with an input end of an analog quantity acquisition unit, an output end of the analog quantity acquisition unit is electrically connected with the PWM interface of the processor, an output end of a switching quantity input unit is electrically connected with the processor, and an input end of a switching quantity output unit is electrically connected with the processor.

The analog quantity acquisition unit is mainly used for acquiring current or voltage and is responsible for converting an analog signal into a digital signal. In this embodiment, as shown in fig. 1, the analog acquisition unit comprises a signal conditioning circuit, a low pass filter, a sample holder, an analog switch and an a/D converter electrically connected in sequence, wherein, the signal conditioning circuit, the low-pass filter and the sample holder can only process one path of analog signals, in this embodiment, the channel formed by the signal conditioning circuit, the low pass filter and the sample holder is an analog channel, the analog switch can select one circuit from the multiple analog channels to output to the A/D converter, therefore, the analog acquisition unit can comprise a plurality of analog channels, the output ends of the plurality of analog channels are respectively and correspondingly electrically connected with the switch input ends of the analog switches, the analog switch can realize the conversion of a plurality of paths of analog signals by only using one path of A/D converter, thereby simplifying the circuit structure and the volume of the device.

The signal conditioning circuit converts the current and the voltage output by the current transformer or the voltage transformer into the voltage meeting the requirement of the measuring range of the A/D converter, and simultaneously has a certain inhibiting effect on high-frequency interference. In the present embodiment, as shown in fig. 2, the signal conditioning circuit includes resistors R47-R49, capacitor C32, operational amplifier OPA2277 and PGA205 amplifier; specifically, the inverting input terminal of the operational amplifier OPA2277 is electrically connected to the secondary side of the current transformer or the secondary side of the voltage transformer, the non-inverting input terminal of the operational amplifier OPA2277 is grounded through the resistor R48, the resistor R47 is connected in parallel between the inverting input terminal of the operational amplifier OPA2277 and the output terminal thereof, the output terminal of the operational amplifier OPA2277 is electrically connected to the VIN + pin of the PGA205 amplifier through the resistor R48, one end of the capacitor C32 is electrically connected to the VIN + pin of the PGA205 amplifier, the other end of the capacitor C32 is grounded, the VIN-pin of the PGA205 amplifier is grounded, and the VO pin of the PGA205 amplifier is electrically connected to the low-pass filter. The amplifier is characterized in that the resistor R47 is a feedback resistor, the operational amplifier OPA2277 amplifies the secondary side current or voltage of a current transformer or a voltage transformer, the PGA205 amplifier is a programmable gain amplifier, the laser correction technology is adopted, the amplifier has the characteristics of low offset voltage, low input bias current, low temperature drift, high common mode rejection ratio and the like, the amplification factor is controlled by a pin A0 and a pin A1, and when the pin A0 and the pin A1 are both 0, the amplification factor is 1; when pin a0 and pin a1 are 1 and 0, respectively, the magnification is 2; when pin a0 and pin a1 are 0 and 1, respectively, the magnification is 4; when the pin a0 and the pin a1 are both 1, the amplification factor is 8, and in this embodiment, the pin a0 and the pin a1 are floating, i.e., the amplification factor of the PGA205 amplifier is 1.

The filter circuit can restore the output signal of the signal conditioning circuit to the input signal without distortion. In the present embodiment, as shown in fig. 2, the low-pass filter includes a resistor R50 and a capacitor C35; the VO pin of the PGA205 amplifier is electrically connected to the input terminal of the sample-and-hold device through a resistor R50, one end of a capacitor C35 is electrically connected to the input terminal of the sample-and-hold device, and the other end of the capacitor C35 is grounded. The resistor R50 and the capacitor C35 form an RC filter circuit, so that a high-frequency part in an output signal of the signal conditioning circuit can be filtered, the occurrence of a frequency spectrum aliasing phenomenon can be avoided, and the cleanness of the input signal is ensured.

The sampling holder ensures that the analog quantity signal input in the A/D conversion process does not change, and ensures synchronous sampling of each channel, so that the phase relation of each analog quantity is kept unchanged before and after sampling. In the present embodiment, as shown in fig. 3, the sample-and-hold device includes an LF198 chip, a resistor R51, a resistor R52, an adjustable resistor R23, and a capacitor C36; specifically, a VO pin of the PGA205 amplifier is electrically connected to an IN pin of the LF198 chip through a resistor R50, a LOGIC pin of the LF198 chip is grounded through a resistor R52, a LOGIC REF pin of the LF198 chip is grounded, an OFFSET ADJ pin of the LF198 chip is electrically connected to a slip sheet of the adjustable resistor R23, one end of the adjustable resistor R23 is grounded, the other end of the adjustable resistor R23 is electrically connected to a power supply, a CH pin of the LF198 chip is grounded through a capacitor C36, and an OUT pin of the LF198 chip is electrically connected to an input end of the analog switch. The LF198 chip integrates a sampling and holding circuit consisting of bipolar insulated gate field effect tubes, and has the characteristics of high sampling speed, low holding and descending speed, high precision and the like. When the amplifier is used as a single amplifier, the current gain precision is 0.002%; when the sampling time is less than 6us, the precision can reach 0.01 percent; by adopting the bipolar input state, low deviation voltage and wide frequency band can be obtained. When the holding capacitance is 1uF, the falling speed is 5 mV/min.

The analog quantity mainly comprises two types of voltage signals and current signals. Wherein, the voltage signal needs to select a signal from A, B, C and a zero sequence voltage channel; the current signal selects one of the A, B, C three DC signal paths, so to realize the selection of the signal, the analog switch is used to select the signal in this embodiment. In this embodiment, as shown in fig. 3, the analog switch includes an AD7503 chip, pins a0, a1, a2, and EN of the AD7503 chip are electrically connected to the I/O ports of the processor in a one-to-one correspondence manner, a pin S5 of the AD7503 chip is electrically connected to a pin OUT of the LF198 chip, and a pin OUT of the AD7503 chip is electrically connected to the analog input port of the a/D converter. The signal selection is completed by an electronic analog switch AD7503, one group of voltage and current signals is selected by loading different channel signals to the chip, and the selected group of voltage and current signals is sent to an A/D converter for processing.

And the A/D converter is used for converting the analog signal output by the analog switch into a digital signal and sending the digital signal to the processor for processing. In the present embodiment, as shown in fig. 4, the a/D converter includes an ADS8556 chip; specifically, a CH _ A0 pin of the ADS8556 chip is electrically connected with an OUT pin of the AD7503 chip, and DB0-DB15 pins of the ADS8556 chip are electrically connected with I/O ports of the processor in a one-to-one correspondence manner.

In this embodiment, the processor is mainly responsible for receiving the signals collected and processed by the analog quantity collecting unit and the switching value input unit, and outputting the control signal to control the switching value output unit. In this embodiment, the processor includes a TMS320F2812 chip; because the pins of the TMS320F2812 chip are dense and the pins are inconvenient to view, fig. 5 only lists the pins used in this embodiment, the minimum system is the same as that in the data manual, the IOA0-IOA15 pins of the TMS320F2812 chip are electrically connected with the DB0-DB15 pins of the ADS8556 chip one by one, the IOF7, IOF6 and XINT pins of the TMS320F2812 chip are electrically connected with the CS, RESET and BUSY pins of the ADS8556 chip one by one, the IOD0 pin of the TMS320F2812 chip is electrically connected with the RD, CONVSTA and CONVSTA pins of the ADS8556 chip, and the GPIOA0_ PWM1, oa1_ PWM2, GPIOA2_ PWM3 and GPIOA3_ 4 pins of the TMS320F2812 chip are electrically connected with the a0, a1, a2 and gpien pins of the AD 7503.

The switching value input unit mainly detects the state and the change of a switching signal and comprises a plurality of switching value input circuits with the same structure, a typical switching value input circuit is an optical coupling isolation circuit, the on-off signal of a switch in the phase testing device of the relay protection device reaches a processor through the optical coupling isolation circuit, and the processor can know the on-off state of the switch; the switching value output unit is mainly used for controlling the on-off of a switching signal, and is typically applied to controlling an intermediate relay by controlling the on-off of a small signal, so that the on-off control of a large signal is realized.

In this embodiment, the maximum output of the ac current source is 300A, and the maximum output of the ac voltage source is 10 kV.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The utility model provides a relay protection device phase place testing arrangement, its includes two alternating current source, an alternating current voltage source, voltage transformer, current transformer, multichannel analog quantity acquisition unit, switching value input unit, switching value output unit and treater, its characterized in that: the analog quantity acquisition unit comprises a signal conditioning circuit, a low-pass filter, a sampling retainer, an analog switch and an A/D converter which are electrically connected in sequence;

the intelligent switching device comprises a current transformer, a voltage transformer, a processor, an alternating current source, an alternating current voltage source, an A/D converter, a switching value input unit, a switching value output unit and a processor, wherein the current transformer and the voltage transformer are connected on a bus in parallel, a PWM interface of the processor is respectively and electrically connected with control ends of the alternating current source and the alternating current voltage source, an output end of the alternating current source is electrically connected with a primary side of the current transformer, an output end of the alternating current voltage source is electrically connected with a primary side of the voltage transformer, a secondary side of the current transformer and a secondary side of the voltage transformer are respectively and electrically connected with input ends of two signal conditioning circuits in a.

2. The phase testing device of claim 1, wherein: the signal conditioning circuit comprises resistors R47-R49, a capacitor C32, an operational amplifier OPA2277 and a PGA205 amplifier;

the inverting input end of the operational amplifier OPA2277 is electrically connected with the secondary side of the current transformer or the secondary side of the voltage transformer, the non-inverting input end of the operational amplifier OPA2277 is grounded through a resistor R48, a resistor R47 is connected between the inverting input end of the operational amplifier OPA2277 and the output end of the operational amplifier OPA2277 in parallel, the output end of the operational amplifier OPA2277 is electrically connected with the VIN + pin of the PGA205 amplifier through a resistor R48, one end of a capacitor C32 is electrically connected with the VIN + pin of the PGA205 amplifier, the other end of the capacitor C32 is grounded, the VIN-pin of the PGA205 amplifier is grounded, and the VO pin of the.

3. The phase testing device of claim 2, wherein: the low-pass filter comprises a resistor R50 and a capacitor C35;

4. The phase testing device of claim 3, wherein: the sampling holder comprises an LF198 chip, a resistor R51, a resistor R52, an adjustable resistor R23 and a capacitor C36;

5. The phase testing device of claim 4, wherein: the analog switch comprises an AD7503 chip;

the A0, A1, A2 and EN pins of the AD7503 chip are electrically connected with the I/O ports of the processor in a one-to-one correspondence mode, the S5 pin of the AD7503 chip is electrically connected with the OUT pin of the LF198 chip, and the OUT pin of the AD7503 chip is electrically connected with the analog input port of the A/D converter.

6. The phase testing device of claim 5, wherein: the A/D converter comprises an ADS8556 chip;

7. The phase testing device of claim 6, wherein: the processor comprises a TMS320F2812 chip;

pins IOA0-IOA15 of the TMS320F2812 chip are electrically connected with pins DB0-DB15 of an ADS8556 chip in a one-to-one corresponding mode, pins IOF7, IOF6 and XINT of the TMS320F2812 chip are electrically connected with pins CS, RESET and BUSY of the ADS8556 chip in a one-to-one corresponding mode, pins IOD0 of the TMS320F2812 chip are electrically connected with pins RD, CONVSTA, CONVSTB and CONVSTC of the ADS8556 chip in a one-to-one corresponding mode, and pins GPIOA0_ PWM1, GPIOA1_ PWM2, GPIOA2_ PWM3 and GPIOA3_ PWM4 of the TMS320F2812 chip are electrically connected with pins A0, A1, A2 and EN of the AD7503 chip in a one-to one mode.

8. The phase testing device of claim 1, wherein: the maximum output quantity of the alternating current source is 300A, and the maximum output quantity of the alternating current voltage source is 10 kV.