CN108241137B - Basic error traceability device of merging unit tester - Google Patents
Basic error traceability device of merging unit tester Download PDFInfo
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- CN108241137B CN108241137B CN201711362080.5A CN201711362080A CN108241137B CN 108241137 B CN108241137 B CN 108241137B CN 201711362080 A CN201711362080 A CN 201711362080A CN 108241137 B CN108241137 B CN 108241137B
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 23
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- 230000003287 optical effect Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 12
- 238000001514 detection method Methods 0.000 abstract description 7
- 238000012360 testing method Methods 0.000 abstract description 3
- 238000010835 comparative analysis Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/02—Testing or calibrating of apparatus covered by the other groups of this subclass of auxiliary devices, e.g. of instrument transformers according to prescribed transformation ratio, phase angle, or wattage rating
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- Testing Electric Properties And Detecting Electric Faults (AREA)
Abstract
The invention discloses a basic error tracing device of a merging unit tester, which is characterized by comprising an upper computer, an analog sampling module, a first synchronization module and a first network port module, wherein the analog sampling module comprises a current transformer module, a voltage transformer module, an A/D conversion module, a first relay module, a first FPGA module and a first STM32 singlechip; the advantage is when detecting merging unit tester, will receive first sampling value signal, second sampling value signal and IEC61850 message signal by first STM32 singlechip and host computer and carry out comparative analysis processing to realize the error process of tracing to the merging unit tester that is examined, whole device simple structure, occupation space are less, with low costs and detection process is convenient fast, and the testing result precision is higher.
Description
Technical Field
The invention relates to an electrical instrument and meter detection device, in particular to a basic error tracing device of a merging unit tester.
Background
The measures or means adopted by power supply units in each place for the links of type selection, acceptance, periodic detection and the like of the electronic transformer and the merging unit are not complete, comprehensive and accurate, and are replaced by relay protection testers, and a method of combining the branch instruments is adopted, so that professional electronic transformers and merging unit testers are rarely adopted.
When the professional electronic transformer and merging unit tester is adopted to detect the electronic transformer and merging unit, the detection result is more accurate, however, the verification of the type of tester by the electric department of the network and the provincial network company is not authoritative and complete, and a method of combining the standard devices is generally adopted, so that the electronic transformer and merging unit tester has the advantages of complex overall structure, more occupied space, higher cost, complex testing process and difficult precision transmission; the national power grid metering center is an integral calibrating device using a difference measuring method as a core, equipment of a polar coordinate system is calibrated by using a rectangular coordinate system, and errors exist in amplitude and phase, so that an error tracing process of the calibrating device is troublesome.
Disclosure of Invention
The invention aims to solve the technical problem of providing the basic error tracing device of the merging unit tester, which has the advantages of simple structure, small occupied space, low cost and convenient and quick error tracing process.
The technical scheme adopted for solving the technical problems is as follows: the basic error tracing device of the merging unit tester comprises an upper computer, an analog sampling module, a first synchronization module and a first network port module, wherein the analog sampling module comprises a current transformer module, a voltage transformer module, an A/D conversion module, a first relay module, a first FPGA module and a first STM32 singlechip, the upper computer is connected with the first STM32 singlechip, the first STM32 singlechip is connected with the first FPGA module through an FSMC bus, the input end of the first synchronization module is connected with the input end of an external synchronization signal, the output end of the first synchronization module is connected with the input end of the synchronization signal of the first FPGA module, the input end of the current transformer module is respectively connected with the three-phase current input end of an external detected device, the input end of the voltage transformer module is respectively connected with the three-phase voltage input end of the external detected device, the first FPGA module respectively sends a first voltage switching command signal and a first switching command signal to the first relay module, the input end of the first FPGA module is connected with the first switching module A/D control module and the first FPGA module receives a voltage switching command signal corresponding to the first input end of the first FPGA module, the first switching module receives a sampling value signal corresponding to the first voltage signal of the first switching module A/D control module, the A/D conversion module sends a second sampling value signal corresponding to the received second voltage signal to the first FPGA module, the input end of the first network port module is connected with the IEC61850 message signal output end of the external detected device, and the output end of the first network port module is connected with the digital signal input end of the first FPGA module.
The three-phase program control source module comprises a second STM32 singlechip, a second FPGA module, a D/A conversion module, three paths of first power amplifier modules, three paths of second power amplifier modules, a booster module, a current booster module and a second relay module, wherein the second STM32 singlechip is connected with the second FPGA module through an FSMC bus, a D/A control output port of the second FPGA module is connected with an input end of the D/A conversion module, the second FPGA module sends configuration signals to the D/A conversion module according to preset configuration parameters, the D/A conversion module respectively sends corresponding voltage signals to the three paths of first power amplifier modules and the three paths of second power amplifier modules according to the received configuration signals, three voltage output ports of the first power amplifier module are respectively connected with three-phase voltage input ports of the booster module, three current output ports of the second power amplifier module are respectively connected with three-phase current input ports of the current booster module, the second FPGA module respectively sends a second voltage switching command signal and a second current switching command signal to the second relay module, the second relay module controls the booster module to send three-phase voltage signals to the voltage transformer module according to the second voltage switching command signal, the second relay module controls the current booster module to send three-phase current signals to the current transformer module according to the second current switching command signal, the input end of the second synchronization module is connected with the synchronous signal output end of the second FPGA module, the output end of the second synchronization module is connected with the input end of the first synchronization module, the input end of the second network port module is connected with the IEC61850 message signal output end of the second FPGA module, and the output end of the second network port module is connected with the input end of the first network port module. When the passive merging unit tester is verified by using the structure, a standard three-phase voltage signal, a standard three-phase current signal and an IEC61850 message signal are set in a three-phase program control source module, the set standard three-phase voltage signal, standard three-phase current signal and IEC61850 message signal are respectively sent to a tested passive merging unit tester and an analog sampling module by the three-phase program control source module, then the ratio difference and the phase difference displayed on software of the tested passive merging unit tester are observed and compared with the ratio difference and the phase difference displayed on related software set on an upper computer, so that the error tracing process of the tested merging unit tester is realized, wherein the synchronous signal can adopt a self synchronous clock mode or an external synchronous clock mode, and when adopting the self synchronous clock mode, the synchronous mode of the analog sampling module is synchronous output B code/PPS, and the synchronous mode of the tested passive merging unit tester is receiving optical B code/PPS; if an external synchronous clock mode is adopted, the synchronous mode of the analog sampling module and the passive merging unit tester to be detected is that the received light B code/PPS is adopted.
The first network port module comprises a first electric network port and a first optical network port, the first electric network port is used for sending a first electric signal based on an IEC61850 message input by an external inspected device to the first FPGA module, and the first optical network port is used for sending a first optical signal based on the IEC61850 message input by the external inspected device to the first FPGA module.
Compared with the prior art, the invention has the advantages that when the merging unit tester is detected, three-phase current signals are respectively input to the input end of the current transformer module from the three-phase current input end of the merging unit tester to be detected, three-phase voltage signals are respectively input to the input end of the voltage transformer module from the three-phase voltage input end of the merging unit tester to be detected, the first synchronization module receives the synchronization signals input by the external synchronization signal input end and sends the synchronization signals to the first FPGA module, the first FPGA module sends a first voltage switching command signal and a first current switching command signal to the first relay module according to the received synchronization signals, the first relay module controls the voltage transformer module to send a first voltage signal to the A/D conversion module according to the first current switching command signal, the A/D conversion module sends corresponding first sampling value signals to the first FPGA module according to the received first voltage signals, the A/D conversion module sends corresponding second sampling value signals to the first FPGA module according to the received second sampling value signals to the first FPGA module 850, the first FPGA module sends the first sampling value signals to the first SCM 6132, the first SCM signal is received by the first SCM module and the first SCM 6132, the first SCM signal is received by the first SCM signal to the first SCM module receives the first SCM signal from the first SCM signal to the first SCM signal, the SCM signal is processed by the SCM 32, the SCM signal is processed by the SCM signal, and the SCM signal is processed by the SCM signal, therefore, the error tracing process of the detected merging unit tester is realized, the whole device has the advantages of simple structure, small occupied space, low cost, rapid and convenient detection process and higher detection result precision.
Drawings
Fig. 1 is a block diagram showing the construction principle of the first embodiment;
fig. 2 is a partial schematic block diagram of the second embodiment.
Detailed Description
The invention is described in further detail below with reference to the embodiments of the drawings.
Embodiment one: the basic error tracing device of the merging unit tester comprises an upper computer 1, an analog sampling module, a first synchronization module 2 and a first network port module 3, wherein the analog sampling module comprises a current transformer module 41, a voltage transformer module 42, an A/D conversion module 43, a first relay module 44, a first FPGA module 45 and a first STM32 singlechip 46, the upper computer 1 is connected with the first STM32 singlechip 46, the first STM32 singlechip 46 is connected with the first FPGA module 45 through an FSMC bus, the input end of the first synchronization module 2 is connected with the input end of an external synchronization signal, the output end of the first synchronization module 2 is connected with the input end of a synchronization signal of the first FPGA module 45, the input end of the current transformer module 41 is respectively connected with the three-phase current input end of an external detected device 5, the input end of the voltage transformer module 42 is respectively connected with the three-phase voltage input end of the external detected device 5, the first FPGA module 45 respectively sends a first voltage switching command signal and a first current switching command signal to the first relay module 44, the first relay module 44 is used for controlling the first relay module to send the first voltage switching command signal to the first FPGA module 45A/D/DC signal to the first FPGA module 43, the first current signal is received by the first FPGA module 43/D signal to the corresponding to the first FPGA module 43, the first current-D signal is received by the first FPGA module 43, the first current-D signal is correspondingly connected with the first current-phase signal of the first FPGA module 43/D signal, and the first current-D signal is received by the first FPGA module 43, the input end of the first network port module 3 is connected with the IEC61850 message signal output end of the external detected device 5, and the output end of the first network port module 3 is connected with the digital signal input end of the first FPGA module 45.
When the structure described in embodiment one is used for detecting the active merging unit tester, firstly, three-phase voltage values and three-phase current values output by a three-phase source are set on the detected active merging unit tester, the amplitude and the phase of a detected digital packet are set, the three-phase voltage values and the three-phase current values output by the detected active merging unit tester are respectively accessed from the current transformer module 41 and the voltage transformer module 42, a first sampling value signal and a first sampling value signal are output to the first FPGA module 45 after analog-to-digital conversion by the A/D conversion module 43, then the first FPGA module 45 respectively sends the received first sampling value signal and the received second sampling value signal to the first STM32 singlechip 46, the detected merging unit tester sends IEC61850 message signals corresponding to the detected digital packet to the first FPGA module 45 through the first network port module 3, the first FPGA module 45 sends the received IEC61850 message signals to the first STM32 singlechip 46, finally, the first STM32 singlechip 46 and the upper computer 1 carry out comparison and the detection result to the PPS 32 singlechip, the phase difference signal is displayed by the first FPGA module 1, the comparison and the error signal is displayed by the corresponding to the PPS 32 singlechip, and the error signal is compared with the error signal of the detected digital packet, and the error signal is displayed by the PPS 1, and the error signal is displayed by the corresponding to the detected digital packet.
Embodiment two: the rest is the same as the first embodiment, and the difference is that the three-phase program control source module comprises a three-phase program control source module, a second synchronization module 6 and a second network port module 7, the three-phase program control source module comprises a second STM32 singlechip 81, a second FPGA module 82, a D/A conversion module 83, a three-way first power amplifier module 84, a three-way second power amplifier module 85, a booster module 86, a current booster module 87 and a second relay module 88, the second STM32 singlechip 81 is connected with the second FPGA module 82 through an FSMC bus, a D/A control output port of the second FPGA module 82 is connected with an input end of the D/A conversion module 83, the second FPGA module 82 sends configuration signals to the D/A conversion module 83 according to preset configuration parameters, the D/A conversion module 83 respectively sends corresponding voltage signals to the three-way first power amplifier module 84 and the three-way second power amplifier module 85 according to the received configuration signals, the voltage output ports of the three-way first power amplifier module 84 are respectively connected with the three-phase voltage input ports of the booster module 86, the current output ports of the three-way second power amplifier module 85 are respectively connected with the three-phase current input ports of the booster module 87, the second FPGA module 82 respectively sends a second voltage switching command signal and a second current switching command signal to the second relay module 88, the second relay module 88 controls the booster module 86 to send the three-phase voltage signal to the voltage transformer module 42 according to the second voltage switching command signal, the second relay module 88 controls the booster module 87 to send the three-phase current signal to the current transformer module 41 according to the second current switching command signal, the input end of the second synchronization module 6 is connected with the synchronization signal output end of the second FPGA module 82, the output end of the second synchronization module 6 is connected with the input end of the first synchronization module 2, the input end of the second network port module 7 is connected with the IEC61850 message signal output end of the second FPGA module 82, and the output end of the second network port module 7 is connected with the input end of the first network port module 3.
When the passive merging unit tester is verified by using the structure as described in the embodiment II, a standard three-phase voltage signal, a standard three-phase current signal and an IEC61850 message signal are set in the three-phase program control source module, the set standard three-phase voltage signal, standard three-phase current signal and IEC61850 message signal are respectively sent to the tested passive merging unit tester and the analog sampling module by the three-phase program control source module, then the ratio difference and the phase difference displayed on the software of the tested passive merging unit tester are observed and compared with the ratio difference and the phase difference displayed on the related software set on the upper computer 1, so that the error tracing process of the tested merging unit tester is realized, wherein the synchronous signal can adopt a self synchronous clock mode or an external synchronous clock mode, and when adopting the self synchronous clock mode, the synchronous mode of the analog sampling module is synchronous output of B code/PPS, and the synchronous mode of the tested passive merging unit tester is receiving light B code/PPS; if an external synchronous clock mode is adopted, the synchronous mode of the analog sampling module and the passive merging unit tester to be detected is that the received light B code/PPS is adopted.
The basic error tracing device of the merging unit tester adopting the structure described in the embodiment is compatible with verification of the electronic transformer calibrator and the merging unit tester, and can be used as a common electronic transformer calibrator and merging unit tester to test the electronic transformer or merging unit.
Claims (1)
1. The basic error tracing device of the merging unit tester is characterized by comprising an upper computer, an analog sampling module, a first synchronization module and a first network port module, wherein the analog sampling module comprises a current transformer module, a voltage transformer module, an A/D conversion module, a first relay module, a first FPGA module and a first STM32 singlechip, the upper computer is connected with the first STM32 singlechip, the first STM32 singlechip is connected with the first FPGA module through an FSMC bus, the input end of the first synchronization module is connected with the input end of an external synchronization signal, the output end of the first synchronization module is connected with the input end of the synchronization signal of the first FPGA module, the input end of the current transformer module is respectively connected with the three-phase current input end of an external detected device, the input end of the voltage transformer module is respectively connected with the three-phase voltage input end of the external detected device, the first FPGA module respectively sends a first voltage switching command signal to the first relay module and a first FPGA module and sends a voltage switching command signal to the first relay module, the first FPGA module sends a voltage switching signal to the first FPGA module and a control module receives a voltage switching signal to the first input end of the first FPGA module, the input end of the current transformer module receives a voltage switching signal to the first voltage converter module, the input end of the first FPGA module receives the voltage signal to the first voltage converter module, the input end of the first voltage transformer module is connected with the three-phase voltage signal input end of the input signal, the A/D conversion module sends a second sampling value signal corresponding to the received second voltage signal to the first FPGA module, the input end of the first network port module is connected with the IEC61850 message signal output end of the external detected device, the output end of the first network port module is connected with the digital signal input end of the first FPGA module, the first network port module comprises a first electric network port and a first optical network port, the first electric network port is used for sending a first electric signal based on the IEC61850 message and input by the external detected device to the first FPGA module, and the first optical network port is used for sending a first optical signal based on the IEC61850 message and input by the external detected device to the first FPGA module;
the three-phase program control source module comprises a second STM32 singlechip, a second FPGA module, a D/A conversion module, three paths of first power amplifier modules, three paths of second power amplifier modules, a booster module, a current booster module and a second relay module, wherein the second STM32 singlechip is connected with the second FPGA module through an FSMC bus, a D/A control output port of the second FPGA module is connected with an input end of the D/A conversion module, the second FPGA module sends configuration signals to the D/A conversion module according to preset configuration parameters, the D/A conversion module respectively sends corresponding voltage signals to the three paths of first power amplifier modules and the three paths of second power amplifier modules according to the received configuration signals, three voltage output ports of the first power amplifier module are respectively connected with three-phase voltage input ports of the booster module, three current output ports of the second power amplifier module are respectively connected with three-phase current input ports of the current booster module, the second FPGA module respectively sends a second voltage switching command signal and a second current switching command signal to the second relay module, the second relay module controls the booster module to send three-phase voltage signals to the voltage transformer module according to the second voltage switching command signal, the second relay module controls the current booster module to send three-phase current signals to the current transformer module according to the second current switching command signal, the input end of the second synchronization module is connected with the synchronous signal output end of the second FPGA module, the output end of the second synchronization module is connected with the input end of the first synchronization module, the input end of the second network port module is connected with the IEC61850 message signal output end of the second FPGA module, and the output end of the second network port module is connected with the input end of the first network port module.
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| CN111141967B (en) * | 2019-10-28 | 2023-03-24 | 许昌开普检测研究院股份有限公司 | Method and system for detecting measurement error of merging unit tester of power system |
| CN112363104A (en) * | 2020-12-07 | 2021-02-12 | 海南电网有限责任公司 | Online calibrator for electric energy meter |
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