CN210628268U - Collimation light path structure for adjusting parallelism of chip sucker and substrate sucker - Google Patents
Collimation light path structure for adjusting parallelism of chip sucker and substrate sucker Download PDFInfo
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- CN210628268U CN210628268U CN201922014602.3U CN201922014602U CN210628268U CN 210628268 U CN210628268 U CN 210628268U CN 201922014602 U CN201922014602 U CN 201922014602U CN 210628268 U CN210628268 U CN 210628268U
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- 239000000758 substrate Substances 0.000 title claims abstract description 103
- 230000003287 optical effect Effects 0.000 claims abstract description 42
- 238000003384 imaging method Methods 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 description 12
- 238000001179 sorption measurement Methods 0.000 description 9
- 239000004579 marble Substances 0.000 description 8
- 230000001678 irradiating effect Effects 0.000 description 4
- 241000252254 Catostomidae Species 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
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Abstract
The utility model discloses an alignment light path structure of adjustment chip sucking disc and base plate sucking disc depth of parallelism has solved current bonding equipment and has had the adjustment to be out of position through the depth of parallelism between self-adaptation adjustment chip sucking disc and the base plate sucking disc before the bonding and lead to the problem that bonding product quality is low and the rejection rate is high. The utility model images the same target in the collimation imaging camera through the double collimation imaging light path; in the imaging light path, except for the reflector of the chip sucker with the reflecting mirror surface and the reflector of the substrate sucker with the reflecting mirror surface, each prism is positioned in a preset optical system, the position and the angle of each prism are constant, and the position of the target for generating the image A can be changed only by adjusting the reflector of the chip sucker with the reflecting mirror surface, so that the adjustment of the parallelism between the chip sucker and the substrate sucker can be realized by adjusting the position of the chip sucker with the reflecting mirror surface; the parallelism between the chip sucker and the substrate sucker is greatly improved.
Description
Technical Field
The invention relates to manufacturing equipment of large-scale integrated circuit devices, in particular to a collimating optical path structure for parallelism between a chip sucker and a substrate sucker in bonding process equipment for flip chip.
Background
The flip chip welding equipment is mainly used for the flip chip welding process of manufacturing large-scale integrated circuit devices, and completes the direct interconnection and bonding of the chip and the substrate, so that the package has more excellent circuit characteristics of high frequency, low delay and low crosstalk, and the reliability of the assembly and interconnection of circuits, parts or systems can be effectively improved; the flip chip bonding equipment mainly comprises three parts: the first part is a circuit substrate placing table arranged on a marble reference platform, and the circuit substrate placing table can be adjusted in position along the X direction, in position along the Y direction and in rotation along a theta axis vertical to a plane formed by the X direction and the Y direction; the second part is a Z-direction lifting arm mechanism arranged right above the marble reference platform, the lower end of the Z-direction lifting arm mechanism is provided with a pitching and deflecting platform, a chip sucker is arranged on the pitching and deflecting platform, the main function of the Z-direction lifting arm mechanism is to realize the bonding of a chip and a substrate by pressing down, and before the bonding, the leveling of the chip sucker and the substrate sucker is realized by the adjustment of pitching and deflecting; the third part is an optical system which is arranged between the reading circuit substrate placing table and the Z-direction lifting arm mechanism and mainly used for detecting whether the chip and the substrate are aligned in place or not and detecting the parallelism of bonding of the chip and the substrate; the bonded reading circuit substrate is placed on the XY theta positioning platform, the bonded chip is adsorbed on the pitching and deflecting platform, the position of the XY theta positioning platform is adjusted and controlled, the bonded chip and the reading circuit substrate are aligned in place, the pitching and deflecting platform is adjusted, the reading circuit substrate and the bonded chip meet the bonding parallelism requirement, after alignment and parallelism adjustment are finished, the Z-direction lifting arm is pressed downwards, the bonded chip and the reading circuit substrate are pressed and bonded together, and therefore the flip-chip bonding technological process of the chip is completed.
The existing bonding process equipment is provided with an optical system, and a microscopic system and a laser system are respectively arranged in the optical system; the parallelism of the sucking discs of the bonded chip and the sucking discs for placing the reading circuit substrate is measured through a laser system in an optical system, and the parallelism of the two sucking discs can meet the requirement of the designed bonding parallelism by adjusting the pitching deflection platform according to the parallelism measuring result of the two sucking discs; then, adsorbing the pre-bonded chip on a chip adsorption sucker, placing a read circuit substrate on the read circuit substrate sucker with a reflector surface, starting a microscope system, aligning the chip adsorbed on the chip adsorption sucker with the read circuit substrate adsorbed on the substrate sucker, pressing down a Z-direction lifting arm after aligning is completed, and pressing and bonding the chip and the read circuit substrate together through compression; the existing optical system only completes the parallelism detection and adjustment of a chip adsorption sucker and a reading circuit substrate sucker, but not the parallelism determination and adjustment of two bonding bodies of a bonded chip and a reading circuit substrate, and has the problem that the parallelism between the two bonding bodies can not be ensured to meet the design requirement when the chip and the substrate are bonded, thereby directly influencing the working performance of a circuit board after the bonding is completed; in addition, a laser system and a microscope system in an optical system of the existing equipment are respectively and independently arranged, and the defect that the optical system occupies a large space exists.
The field operation steps are as follows: the reading circuit substrate is placed on an XY theta positioning platform below, the bonded chip is adsorbed on an upper pitching deflection platform, and accurate alignment of the chip and the substrate is firstly carried out; then, the XY theta positioning platform and the pitching deflection platform are controlled to enable the reading circuit substrate to be parallel to the bonded chip, finally, the Z-direction lifting arm presses the pitching deflection platform downwards, the bonded chip and the reading circuit substrate are bonded together through pressure welding, and therefore the flip chip bonding process of the chip is completed; the existing leveling means is used for adjusting the parallelism of the two suckers in a self-adaptive mode, namely, a chip sucker is pressed down to a substrate sucker in advance to be leveled and set, and the parallelism of the two suckers is adjusted according to the memory set for leveling.
Disclosure of Invention
The invention provides a collimation light path structure for adjusting parallelism of a chip sucker and a substrate sucker, which solves the technical problems of low quality and high rejection rate of bonded products caused by the fact that the parallelism between the chip sucker and the substrate sucker is not adjusted by self-adaptive adjustment before bonding of the conventional bonding equipment.
The invention solves the technical problems by the following technical scheme:
a bonding process device for chip inversion comprises a marble reference platform, a Y-direction moving guide rail mounting base is arranged on the marble reference platform, a positioning platform Y-direction moving platform guide rail is mounted on the Y-direction moving guide rail mounting base, a positioning platform Y-direction moving slide block is arranged on the positioning platform Y-direction moving platform guide rail, a positioning platform X-direction moving guide rail is arranged on the top end surface of the positioning platform Y-direction moving slide block, a positioning platform X-direction moving slide block is arranged on the positioning platform X-direction moving guide rail, the positioning platform X-direction moving slide block is movably arranged on the positioning platform X-direction moving guide rail through the bottom surface of the rear side end of the positioning platform X-direction moving slide block, an air-floating supporting pad is arranged on the bottom surface of the front side end of the positioning platform X-direction moving slide block, the air-floating supporting pad is movably arranged on the top surface of the marble reference platform, a theta rotation platform and a, a reading circuit substrate placing table is arranged on the top surface of the theta rotating platform, a substrate sucker with a reflecting mirror surface is arranged on the reading circuit substrate placing table, a reading circuit substrate is placed on the substrate sucker with the reflecting mirror surface, and a substrate parallelism adjusting mark point is arranged on the reading circuit substrate; a Z-direction lifting arm is arranged right above the theta rotating platform, a pitching deflection adjusting motor and a pitching deflection adjusting platform are respectively arranged at the bottom end of the Z-direction lifting arm, a chip adsorption platform is fixedly arranged on the lower bottom surface of the pitching deflection adjusting platform, a chip sucker with a reflecting mirror surface is adsorbed on the lower bottom surface of the chip adsorption platform, a chip is adsorbed on the lower bottom surface of the chip sucker with the reflecting mirror surface, and a chip parallelism adjusting mark point is arranged on the lower bottom surface of the chip; an XY direction moving platform of the optical system is movably arranged between the reading circuit substrate placing platform and the Z direction lifting arm, and an optical system operation box is hung on the XY direction moving platform of the optical system.
The optical system operation box is provided with a collimation light path for leveling a chip adsorption sucker and a reading circuit substrate sucker, the collimation light path consists of a red LED point light source, a blue LED point light source, a semi-transparent semi-reflective mirror, a collimation objective lens, a reflector, a target image generating plate, a light filter, a substrate sucker with a reflecting mirror surface, a chip sucker with a reflecting mirror surface and a collimation imaging camera, an icon generated by irradiating the light of the red LED point light source on the target image generating plate is reflected by the chip sucker with the reflecting mirror surface, a chip sucker position state image A is generated in the collimation imaging camera, an icon generated by irradiating the light of the blue LED point light source on the target image generating plate is reflected by the substrate sucker with the reflecting mirror surface, and a substrate sucker position state image B is generated in the collimation imaging camera.
A bonding method for flip chip characterized by the steps of: a microscopic light path for aligning the chip and the substrate is arranged in the optical system operation box, and the microscopic light path consists of a semi-transparent semi-reflecting mirror, a collimating objective, a reflecting mirror, a focusing objective, a pentagonal prism and a microscopic imaging camera with a light source; light rays of a light source in the microscopic imaging camera with the light source irradiate the reflecting surface at the mark point on the chip, and the reflected light rays image the mark point image C of the chip in the microscopic imaging camera; meanwhile, light of a light source in a microscopic imaging camera with the light source irradiates a reflecting surface at a mark point on a substrate, the reflected light images a substrate mark point image D in the microscopic imaging camera, and if the chip mark point image C is not coincident with the substrate mark point image D, a read circuit substrate placing table is adjusted until the chip mark point image C is coincident with the substrate mark point image D, so that the alignment work of the chip and the read circuit substrate is completed.
A collimation light path structure for adjusting parallelism of a chip sucker and a substrate sucker comprises an optical system operation box, a chip sucker with a reflector surface and a substrate sucker with a reflector surface, wherein a red LED point light source is arranged in the optical system operation box, a first half-transmitting half-reflecting mirror is arranged on the right side of the red LED point light source, a first collimation objective lens is arranged on the right side of the first half-transmitting half-reflecting mirror, a target image generating plate is arranged on the right side of the first collimation objective lens, a first reflector forming an angle of 45 degrees with the horizontal plane is arranged on the right side of the target image generating plate, a second half-transmitting half-reflecting mirror is arranged under the first reflector, a second reflector forming an angle of 135 degrees with the horizontal plane is arranged on the right side of the second half-transmitting half-reflecting mirror, a first light filter is arranged right above the second reflector, and a chip sucker with a reflector surface is arranged right above the first light filter, a third reflector forming an angle of 135 degrees with the horizontal plane is arranged on the left side of the second half-transmitting half-reflecting mirror, a fourth reflector forming an angle of 135 degrees with the horizontal plane is arranged right below the third reflector, a second collimating objective lens is arranged on the left side of the fourth reflector, and a collimating imaging camera is arranged on the left side of the second collimating objective lens; a blue LED point light source is arranged under the first semi-transparent semi-reflective mirror, a fifth reflective mirror forming an angle of 45 degrees with the horizontal plane is arranged under the second semi-transparent semi-reflective mirror, a sixth reflective mirror forming an angle of 45 degrees with the horizontal plane is arranged on the right side of the fifth reflective mirror, a second optical filter is arranged under the sixth reflective mirror, and a substrate sucker with a reflective mirror surface is arranged under the second optical filter.
A target generation image A of a target image reflected by a chip sucker with a reflector and a target generation image B of the target image reflected by a substrate sucker with a reflector are respectively generated in the collimation imaging camera.
A method for adjusting the parallelism of a chip sucker and a substrate sucker by using a collimated light path is characterized by comprising the following steps:
red light rays emitted by a red LED point light source are transmitted by a first half-mirror and a first collimating objective in sequence, and then target image red light rays are formed on a target image generating plate, the formed target image red light rays are reflected by a first reflecting mirror, a second half-mirror and a second reflecting mirror in sequence, are filtered by a first optical filter, irradiate on a reflecting mirror surface of a chip sucker with a reflecting mirror surface, and are reflected by the reflecting mirror surface, and then are sequentially filtered by the first optical filter, reflected by the second reflecting mirror, transmitted by the second half-mirror, reflected by a third reflecting mirror, reflected by a fourth reflecting mirror and transmitted by the second collimating objective to generate a target generating image A in a collimating imaging camera, wherein the target generating image A is formed by the target image reflected by the chip sucker with the reflecting mirror surface;
after the blue light emitted by the blue LED point light source is reflected by the first half-transmitting half-reflecting mirror and transmitted by the first collimating objective lens in sequence, forming a target image blue light on the target image generating plate, wherein the formed target image blue light is reflected by the first reflector, transmitted by the second half-transmitting and half-reflecting mirror, reflected by the fifth reflector and reflected by the sixth reflector in sequence, after being filtered by a second optical filter, the light irradiates on a reflecting mirror surface of a substrate sucker with a reflecting mirror surface, and after being reflected by the reflecting mirror surface of the substrate sucker, the light passes through the second optical filter for filtering, the reflection of a sixth reflecting mirror, the reflection of a fifth reflecting mirror, the reflection of a second semi-permeable semi-reflecting mirror, the reflection of a third reflecting mirror, the reflection of a fourth reflecting mirror and the transmission of a second collimating objective lens in sequence, generating a target generation image B of a target image after the target image is reflected by a substrate sucker with a reflector surface in a collimation imaging camera;
and if the target generation image A and the target generation image B are not coincident, adjusting the pitching and yawing adjusting platform, changing the posture of the chip sucker with the reflecting mirror surface until the target generation image A after the target image is reflected by the chip sucker with the reflecting mirror surface is coincident with the target generation image B after the target image is reflected by the substrate sucker with the reflecting mirror surface, and finishing the adjustment operation of the parallelism of the chip sucker and the substrate sucker.
The same target is imaged in the collimation imaging camera through the double collimation imaging optical paths; in the imaging light path, except for the reflector of the chip sucker with the reflecting mirror surface and the reflector of the substrate sucker with the reflecting mirror surface, each prism is positioned in a preset optical system, the position and the angle of each prism are constant, and under the condition that the horizontal position of the substrate sucker with the reflecting mirror surface is not changed, the position of a target for generating an image A can be changed only by adjusting the reflector of the chip sucker with the reflecting mirror surface, so that the adjustment of the parallelism between the chip sucker and the substrate sucker can be realized by adjusting the position of the chip sucker with the reflecting mirror surface; particularly, for the double-collimation imaging optical path, the imaging numerical value of the coincidence degree of the target generation image A and the target generation image B is easy to obtain, and the parallelism of the chip sucker and the substrate sucker is greatly improved by controlling the difference degree of the two imaging numerical values.
Drawings
FIG. 1 is a diagram of a collimated light path for adjusting parallelism between a chip chuck and a substrate chuck in accordance with the present invention;
FIG. 2 is a schematic diagram of the general structure of the bonding process equipment for flip chip of the present invention;
fig. 3 is a schematic view of the structure of XY θ stage on the marble reference stage 21 of the present invention;
FIG. 4 is a schematic diagram of the optical system operation platform of the present invention;
fig. 5 is a schematic structural view of the Z-direction lift arm mechanism of the present invention.
Detailed Description
The invention is described in detail below with reference to the accompanying drawings:
a bonding process device for chip flip-chip comprises a marble reference platform 21, a Y-direction moving guide rail mounting base 9 is arranged on the marble reference platform 21, a positioning platform Y-direction moving platform guide rail 8 is arranged on the Y-direction moving guide rail mounting base 9, a positioning platform Y-direction moving slider 7 is arranged on the positioning platform Y-direction moving platform guide rail 8, a positioning platform X-direction moving guide rail 6 is arranged on the top end surface of the positioning platform Y-direction moving slider 7, a positioning platform X-direction moving slider 22 is arranged on the positioning platform X-direction moving guide rail 6, the positioning platform X-direction moving slider 22 is movably arranged on the positioning platform X-direction moving guide rail 6 through the bottom surface of the rear end of the positioning platform X-direction moving slider 22, an air-floating supporting pad 10 is arranged on the bottom surface of the front end of the positioning platform X-direction moving slider 22, the air-floating supporting pad 10 is movably arranged on, a theta rotation platform 3 and a rotation driving motor 11 are respectively arranged on the top end surface of a positioning platform X-direction moving slide block 22, a read circuit substrate placing platform 1 is arranged on the top surface of the theta rotation platform 3, a substrate sucker 2 with a reflecting mirror surface is arranged on the read circuit substrate placing platform 1, a read circuit substrate 4 is arranged on the substrate sucker 2 with the reflecting mirror surface, and a substrate parallelism adjusting mark point 5 is arranged on the read circuit substrate 4; a Z-direction lifting arm 17 is arranged right above the theta rotary platform 3, a pitching deflection adjusting motor 18 and a pitching deflection adjusting platform 12 are respectively arranged at the bottom end of the Z-direction lifting arm 17, a chip adsorption platform 13 is fixedly arranged on the lower bottom surface of the pitching deflection adjusting platform 12, a chip sucker 14 with a reflecting mirror surface is adsorbed on the lower bottom surface of the chip adsorption platform 13, a chip 15 is adsorbed on the lower bottom surface of the chip sucker 14 with the reflecting mirror surface, and a chip parallelism adjusting mark point 16 is arranged on the lower bottom surface of the chip 15; an XY-direction moving table 19 of an optical system is movably provided between the reading circuit board placement table 1 and the Z-direction lift arm 17, and an optical system operation box 20 is hung on the XY-direction moving table 19 of the optical system.
An optical system operation box 20 is internally provided with a collimation light path for leveling a chip adsorption sucker and a reading circuit substrate sucker, wherein the collimation light path consists of a red LED point light source, a blue LED point light source, a semi-transparent semi-reflecting mirror, a collimation objective lens, a reflecting mirror, a target image generating plate, a light filter, a substrate sucker 2 with a reflecting mirror surface, a chip sucker 14 with a reflecting mirror surface and a collimation imaging camera, an icon generated by irradiating the light of the red LED point light source on the target image generating plate is reflected by the chip sucker 14 with the reflecting mirror surface, a chip sucker position state image A is generated in the collimation imaging camera, and an icon generated by irradiating the light of the blue LED point light source on the target image generating plate is reflected by the substrate sucker 2 with the reflecting mirror surface, and a substrate sucker position state image B is generated in the collimation imaging camera; the invention adjusts the pitching and the yawing degree of the chip sucker by respectively carrying out the light reflection imaging on the chip sucker and the light reflection imaging on the substrate sucker on the same target image through the collimation light path and comparing whether the two images are superposed or not, thereby achieving the parallelism of the two suckers.
A bonding method for flip chip characterized by the steps of: a microscopic light path for aligning the chip and the substrate is arranged in the optical system operation box 20, and the microscopic light path consists of a semi-transparent semi-reflecting mirror, a collimating objective lens, a reflecting mirror, a focusing objective lens, a pentagonal prism and a microscopic imaging camera with a light source; light rays of a light source in the microscopic imaging camera with the light source irradiate the reflecting surface at the mark point on the chip, and the reflected light rays image the mark point image C of the chip in the microscopic imaging camera; meanwhile, light of a light source in a microscopic imaging camera with the light source irradiates a reflecting surface at a mark point on a substrate, the reflected light images a mark point image D of the substrate in the microscopic imaging camera, and if the chip mark point image C is not coincident with the substrate mark point image D, the read circuit substrate placing table 1 is adjusted until the chip mark point image C is coincident with the substrate mark point image D, so that the alignment work of the chip and the read circuit substrate is completed; the invention combines the light source in the microscopic imaging camera, and irradiates the chip mark point and the substrate mark point through the respective light rays irradiated by the microscopic imaging camera, so that the two mark points are reflected and imaged in the microscopic imaging camera, and the accurate alignment of the chip and the substrate is realized by adjusting the superposition of the reflected and imaged two mark points.
A collimation light path structure for adjusting parallelism of a chip sucker and a substrate sucker comprises an optical system operation box 20, a chip sucker 14 with a reflector surface and a substrate sucker 2 with a reflector surface, wherein a red LED point light source 23 is arranged in the optical system operation box 20, a first half-transmitting and half-reflecting mirror 24 is arranged on the right side of the red LED point light source 23, a first collimation objective 25 is arranged on the right side of the first half-transmitting and half-reflecting mirror 24, a target image generating plate 26 is arranged on the right side of the first collimation objective 25, a first reflector 27 forming an angle of 45 degrees with the horizontal plane is arranged on the right side of the target image generating plate 26, a second half-transmitting and half-reflecting mirror 28 is arranged under the first reflector 27, a second reflector 29 forming an angle of 135 degrees with the horizontal plane is arranged on the right side of the second half-transmitting and half-reflecting mirror 28, a first light filter 30 is arranged right above the second reflector 29, a chip sucker 14 with a reflector surface is arranged right above the first optical filter 30, a third reflector 31 forming an angle of 135 degrees with the horizontal plane is arranged on the left side of the second half-mirror 28, a fourth reflector 32 forming an angle of 135 degrees with the horizontal plane is arranged right below the third reflector 31, a second collimating objective lens 33 is arranged on the left side of the fourth reflector 32, and a collimating imaging camera 34 is arranged on the left side of the second collimating objective lens 33; a blue LED point light source 35 is provided directly below the first half mirror 24, a fifth mirror 36 forming an angle of 45 ° with the horizontal plane is provided directly below the second half mirror 28, a sixth mirror 37 forming an angle of 45 ° with the horizontal plane is provided on the right side of the fifth mirror 36, a second filter 38 is provided directly below the sixth mirror 37, and a substrate chuck 2 having a reflecting mirror surface is provided directly below the second filter 38.
In the collimating and imaging camera 34, a target generation image a in which the target image is reflected by the chip chuck 14 with a mirror surface and a target generation image B in which the target image is reflected by the substrate chuck 2 with a mirror surface are generated, respectively.
A method for adjusting the parallelism of a chip sucker and a substrate sucker by using a collimated light path is characterized by comprising the following steps:
after red light rays emitted by the red LED point light source (23) are transmitted by the first half-transmitting and half-reflecting mirror 24 and the first collimating objective lens 25 in sequence, the target image red light is formed on the target image generating plate 26, and the formed target image red light is reflected by the first reflecting mirror 27, the second half mirror 28 and the second reflecting mirror 29 in this order, after being filtered by the first optical filter 30, the light irradiates the reflecting mirror surface of the chip sucker 14 with the reflecting mirror surface, and after being reflected by the reflecting mirror surface, the light is filtered by the first optical filter 30, reflected by the second reflecting mirror 29, transmitted by the second half mirror 28, reflected by the third reflecting mirror 31, reflected by the fourth reflecting mirror 32 and transmitted by the second collimating objective lens 33 in sequence, and then a target generation image A of a target image reflected by the chip sucker 14 with the reflecting mirror surface is generated in the collimating imaging camera 34;
after the blue light emitted by the blue LED point light source 35 is reflected by the first half mirror 24 and transmitted by the first collimating objective 25, the blue light of the target image is formed on the target image generating plate 26, and the formed blue light of the target image is reflected by the first reflector 27, transmitted by the second half mirror 28, reflected by the fifth reflector 36, and reflected by the sixth reflector 37 in sequence, and after being filtered by the second filter 38, the light irradiates the reflecting mirror surface of the substrate sucker 2 with the reflecting mirror surface, and after being reflected by the reflecting mirror surface of the substrate sucker 2, the light is filtered by the second filter 38, reflected by the sixth reflecting mirror 37, reflected by the fifth reflecting mirror 36, reflected by the second half mirror 28, reflected by the third reflecting mirror 31, reflected by the fourth reflecting mirror 32 and transmitted by the second collimating objective 33, generating a target generation image B in the collimation imaging camera 34 after the target image is reflected by the substrate sucker 2 with a reflecting mirror surface;
if the target generation image A and the target generation image B are not coincident, the pitching and yawing adjusting platform 12 is adjusted, the posture of the chip sucker 14 with the reflecting mirror surface is changed until the target generation image A after the target image is reflected by the chip sucker 14 with the reflecting mirror surface is coincident with the target generation image B after the target image is reflected by the substrate sucker 2 with the reflecting mirror surface, and the adjustment operation of the parallelism of the chip sucker and the substrate sucker is completed.
Claims (2)
1. A collimation light path structure for adjusting parallelism of a chip sucker and a substrate sucker comprises an optical system operation box (20), the chip sucker (14) with a reflector surface and the substrate sucker (2) with the reflector surface, and is characterized in that a red LED point light source (23) is arranged in the optical system operation box (20), a first half-transmitting and half-reflecting mirror (24) is arranged on the right side of the red LED point light source (23), a first collimation objective lens (25) is arranged on the right side of the first half-transmitting and half-reflecting mirror (24), a target image generating plate (26) is arranged on the right side of the first collimation objective lens (25), a first reflector (27) forming an angle of 45 degrees with a horizontal plane is arranged on the right side of the target image generating plate (26), a second half-transmitting and half-reflecting mirror (28) is arranged under the first reflector (27), a second reflector (29) forming an angle of 135 degrees with the horizontal plane is arranged on the right side of the second half-transmitting and half-reflecting mirror (28), a first optical filter (30) is arranged right above the second reflector (29), a chip sucker (14) with a reflector surface is arranged right above the first optical filter (30), a third reflector (31) forming an angle of 135 degrees with the horizontal plane is arranged on the left side of the second half-mirror (28), a fourth reflector (32) forming an angle of 135 degrees with the horizontal plane is arranged right below the third reflector (31), a second collimating objective lens (33) is arranged on the left side of the fourth reflector (32), and a collimating imaging camera (34) is arranged on the left side of the second collimating objective lens (33); a blue LED point light source (35) is arranged under the first half-transmitting and half-reflecting mirror (24), a fifth reflecting mirror (36) forming an angle of 45 degrees with the horizontal plane is arranged under the second half-transmitting and half-reflecting mirror (28), a sixth reflecting mirror (37) forming an angle of 45 degrees with the horizontal plane is arranged on the right side of the fifth reflecting mirror (36), a second optical filter (38) is arranged under the sixth reflecting mirror (37), and a substrate sucker (2) with a reflecting mirror surface is arranged under the second optical filter (38).
2. The structure of claim 1, wherein a target generation image A of the target image reflected by the chip sucker (14) with a reflecting mirror surface and a target generation image B of the target image reflected by the substrate sucker (2) with a reflecting mirror surface are generated in the collimating imaging camera (34).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922014602.3U CN210628268U (en) | 2019-11-20 | 2019-11-20 | Collimation light path structure for adjusting parallelism of chip sucker and substrate sucker |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922014602.3U CN210628268U (en) | 2019-11-20 | 2019-11-20 | Collimation light path structure for adjusting parallelism of chip sucker and substrate sucker |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110854054A (en) * | 2019-11-20 | 2020-02-28 | 西北电子装备技术研究所(中国电子科技集团公司第二研究所) | Collimation light path structure for adjusting parallelism of chip sucker and substrate sucker |
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2019
- 2019-11-20 CN CN201922014602.3U patent/CN210628268U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110854054A (en) * | 2019-11-20 | 2020-02-28 | 西北电子装备技术研究所(中国电子科技集团公司第二研究所) | Collimation light path structure for adjusting parallelism of chip sucker and substrate sucker |
| CN110854054B (en) * | 2019-11-20 | 2024-06-04 | 西北电子装备技术研究所(中国电子科技集团公司第二研究所) | Collimation light path structure for adjusting parallelism of chip sucker and substrate sucker |
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