CN210626609U

CN210626609U - SMT semi-finished product testing system

Info

Publication number: CN210626609U
Application number: CN201920580018.1U
Authority: CN
Inventors: 徐贵健
Original assignee: Beijing Senbo Embedden Computer Co ltd
Current assignee: Beijing Senbo Embedden Computer Co ltd
Priority date: 2019-04-25
Filing date: 2019-04-25
Publication date: 2020-05-26
Anticipated expiration: 2029-04-25

Abstract

The utility model relates to a SMT semi-manufactured goods test system, through the probe to 104 on the integrated circuit board the signal tested lead to the support plate, through setting up the test circuit system on the support plate, DEBUG display element, bus extension network unit etc. judge the exactness of PC104 integrated circuit board signal and function, operate the information display of needs through control panel to reach product test's purpose, guarantee product quality. The utility model is suitable for a SMT semi-manufactured goods detects, realizes the commonality that the detection of multiple project and product needs, practicality, uniformity.

Description

SMT semi-finished product testing system

Technical Field

The utility model belongs to the technical field of the SMT production line detects, particularly, for a SMT semi-manufactured goods test system.

Background

With the rapid development of the electronic industry, the production efficiency, quality control and cost of electronic manufacturing enterprises determine the competitiveness of the enterprises; with the development of IC packaging towards high integration, high performance, multiple leads and narrow pitch, it has promoted the wide application of SMT (surface mount technology) technology in high-end electronic products, and the SMT technology has entered a fast and good development period under the drive of high-end products such as communications.

In the detection stage of the SMT production line, the existing probe test has high manufacturing cost, huge equipment and no operability on the general production line, is suitable for research and development and scientific research, can only test the relative on-off and resistance value data of the static board card by the flying probe test, and has no guidance on production.

In view of this, the present invention is especially provided.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a solve not enough among the above-mentioned prior art, provide a new SMT semi-manufactured goods test system, be applicable to among the SMT semi-manufactured goods testboard test circuit.

In order to solve the technical problem, the utility model adopts the following basic concept:

the utility model provides a SMT semi-manufactured goods test system, includes power module and support plate, sets up test circuit system on the support plate, and test circuit system includes treater, DEBUG display element, bus extension network unit, control panel unit and power and protection circuit unit control panel unit, power and protection circuit unit, DEBUG display element and the equal circuit connection of bus extension network unit the treater, power module is the power supply of whole test circuit system.

As one of the preferred embodiments of the SMT half finished product testing system described above, the DEBUG display unit is a PC104 bus extension DEBUG display circuit, which includes a bidirectional transceiver, and the transceiver is accessed to an ISA bus to be able to acquire a detection signal of a board under test; the transceiver circuit is connected with the processor, and the processor circuit is connected with a DEBUG display nixie tube.

As one of the preferred embodiments of the SMT semi-finished product testing system described above, the transceiver is an isolation chip SN74LVC 4245.

As one of the preferred embodiments of the SMT semi-finished product testing system, the bus expansion network unit comprises a PC104 bus expansion network chip, and the bus expansion network chip is connected with a PCI + bus for accessing a tested board.

As one of the preferred embodiments of the SMT semi-finished product testing system described above, the control panel unit includes a switch, an indicator light, a reset key, the DEBUG display nixie tube, and a buzzer, all of which are electrically connected to the processor, wherein the indicator light includes a switch indicator light and a reset indicator light.

As one of the preferable embodiments of the SMT semi-finished product testing system, the testing circuit further comprises a VGA, PS/2 signal output unit; the VGA and PS/2 signal output unit comprises a VGA socket and a PS/2 socket, and the VGA socket and the PS/2 socket are used for being connected to a tested board through a test probe so as to be capable of outputting VGA and PS/2 signals of the tested board.

As one preferred embodiment of the SMT system for testing semi-finished products, the power supply and protection circuit unit includes a power input interface resistance detection circuit and a power-on over-current protection circuit.

As one of the preferred embodiments of the SMT semi-finished product testing system described above, the power input interface resistance detection circuit is configured to detect a +5VSB power supply of a board under test; the detection circuit comprises a first operational amplifier U8A and a second operational amplifier U8B, wherein a diode D1 and a protective resistor R17 which are connected in series are arranged between a +5V power supply of the detection circuit and a +5VSB power supply of a detected board and then are connected to the non-inverting input end of the first operational amplifier U8A, and the non-inverting input end is connected with a filter capacitor C32 in series and is grounded; the reverse input end of the first operational amplifier U8A is connected with the output end, and a resistor R74 is arranged between the two ends and grounded; the positive and negative power terminals of the first operational amplifier U8A are respectively connected with +5V voltage and ground; the output end of the first operational amplifier U8A is connected with the non-inverting input end of the second operational amplifier U8B, and the inverting input end of the second operational amplifier U8B is connected with a +5V power supply and the ground through a voltage division resistor R18 and a voltage division resistor R19 respectively; the output end of the second operational amplifier U8B is connected with the grid of the second MOS tube Q2, the source of the second MOS tube is grounded, the drain is connected with the +3.3V power supply through a resistor R20, and the signal CPLD _ PWR _ VSB is output to the processor.

As one of the preferred embodiments of the SMT semi-finished product testing system described above, the power-on over-current protection circuit includes a first MOS transistor Q1 as an electronic switch; the source electrode of the first MOS tube is connected with +5V power supply, and the grid electrode of the first MOS tube is connected with a third MOS tube Q10 to receive a power supply starting signal PS _ ON; the drain electrode of the first MOS tube Q1 is connected with a power supply +5VSB of the board to be detected through a self-on-off fuse F1, and is connected with a voltage monitoring chip through voltage dividing resistors R23 and R22, and the voltage monitoring chip outputs a monitoring signal CPLD _ VCC5VSB to the processor.

As one of the preferred embodiments of the SMT semi-finished product testing system, the voltage monitoring chip adopts a chip MAX 16052.

After the technical scheme is adopted, compared with the prior art, the utility model following beneficial effect has:

the utility model discloses SMT semi-manufactured goods test system mainly provides a test circuit who is applicable to SMT semi-manufactured goods and detects, realizes the detection of multiple project and has the commonality.

Drawings

FIG. 1 is a logic block diagram of the SMT semi-finished product testing system of the present invention;

FIG. 2 is a schematic diagram of a resistance detection circuit of a power input interface of the SMT semi-finished product testing system of the present invention;

FIG. 3 is a schematic diagram of a starting-up over-current protection circuit of the SMT semi-finished product testing system of the present invention;

Detailed Description

The invention will be further described with reference to the accompanying drawings and specific embodiments to assist understanding of the invention.

As shown in fig. 1, an SMT semi-finished product testing system for detecting an SMT production line includes a POWER supply module and a carrier board, where the POWER supply module POWER outputs +5V and +12V voltages as a main POWER supply; the test circuit system is arranged on the carrier plate and comprises a processor, a DEBUG display unit, a bus expansion network unit, a control panel unit, a power supply and protection circuit unit and VGA and PS/2 signal output units; the control panel unit, the power supply and protection circuit unit, the DEBUG display unit, the bus expansion network unit and the VGA, the PS/2 signal output units are all in circuit connection with the processor, and the power supply module supplies power for the whole test circuit system.

Specifically, the processor, namely the master control logic chip CPLD, preferably adopts an LCMXO2-1200-TG100 chip series; the processor controls to output, obtain and process signals of each circuit unit, wherein the DEBUG display unit is a PC104 bus expansion DEBUG display circuit which comprises a bidirectional transceiver connected through an ISA bus network (comprising ISA _ SD [7:0], SA _ SA [9:0], ISA _ RSTDRV and ISA _ LOW #); acquiring a detection signal of a detected plate, performing level conversion through a bidirectional transceiver, and inputting the detection signal into the processor for processing so as to read 80 port information when the detected plate is subjected to power-on self-test; the information read by the processor is displayed through a DEBUG display nixie tube connected with the SPI bus. As preferred embodiment, the utility model discloses in chip SN74LVC4245 is kept apart in the adoption of two-way transceiver, and the commonality is good, is convenient for realize the suitable for to multiple board under test.

The bus extension network unit comprises a PC104 bus extension network chip used for testing the PC104 bus of the tested board; in this embodiment, an ethernet controller I82551 chip is preferably adopted, and is connected to the board under test through the PCI + bus, so as to expand a network, and directly perform a self-test on the inside of the network on the board under test, thereby achieving the purpose of testing the PC104 bus.

The SMT semi-finished product testing system further comprises a tested board network port serial port self-testing unit, the tested board network port serial port self-testing unit comprises a testing pin, the testing pin is directly led out to be connected to a tested board during testing, and the tested board is internally connected with a resistor in a self-testing mode, so that the purpose of self-testing can be achieved.

The control panel unit comprises a switch, an indicator light, a reset key, a DEBUG display nixie tube and a buzzer, wherein the switch, the indicator light, the reset key, the DEBUG display nixie tube and the buzzer are connected with the processor through circuits; when the switch works, the switch transmits a switch signal to the processor, the processor controls the power supply communicated with the tested board, and the switch indicator lamp is controlled to output a signal to display that the switch is started.

The reset key circuit is connected with the tested board to transmit a reset control signal, the reset key is operated to transmit the reset control signal to reset the tested board during working, and the tested board controls an output signal to a reset indicator lamp to display that the reset signal is reset after the reset signal output by the PC104 bus is sent to the processor.

The DEBUG display nixie tube adopts a nixie tube module with an SPI serial port, and is connected to the processor through a circuit to display the information of the reading materials of the processor.

The buzzer is connected with the processor through a circuit and driven by an output signal of the processor so as to carry out sound prompt in the SMT semi-finished product detection process.

VGA, PS 2 signal output unit includes VGA horn socket and PS 2 horn socket, and the socket can be through coordinating this test circuit outer test probe (provided by SMT semi-manufactured goods testboard) circuit intercommunication by the board under test, and during operation, the socket passes through test probe intercommunication the board under test is with corresponding VGA, PS 2 signal output to whether detect board under test VGA, PS 2 signal output is normal.

The power supply and protection circuit unit comprises a power supply input interface resistance detection circuit and a starting-up overcurrent protection circuit; wherein

The power input interface resistance detection circuit is used for detecting the +5VSB power supply of the detected plate; specifically, the detection circuit comprises a first operational amplifier U8A and a second operational amplifier U8B, wherein a diode D1 and a protective resistor R17 which are connected in series are arranged between a +5V power supply of the detection circuit and a +5VSB power supply of a detected board, then the diode D1 and the protective resistor R17 are connected to the non-inverting input end of the first operational amplifier U8A, and the non-inverting input end is connected with a filter capacitor C32 in series and is grounded; the reverse input end of the first operational amplifier U8A is connected with the output end, and a resistor R74 is arranged between the two ends and grounded; the positive and negative power terminals of the first operational amplifier U8A are respectively connected with +5V voltage and ground; the output end of the first operational amplifier U8A is connected with the non-inverting input end of the second operational amplifier U8B, and the inverting input end of the second operational amplifier U8B is connected with a +5V power supply and the ground through a voltage division resistor R18 and a voltage division resistor R19 respectively; the output end of the second operational amplifier U8B is connected to the gate of the second MOS transistor Q2, the source of the second MOS transistor is grounded, the drain is connected to the +3.3V power supply through the resistor R20 (the +3.3V power supply for the peripheral power supply is provided by the power supply chip IC _ LM 1117-3.3), and outputs a signal CPLD _ PWR _ VSB to the processor. The first operational amplifier U8A and the second operational amplifier U8B are preferably LM324 type, but are not limited thereto.

The start-up over-current protection circuit comprises a first MOS tube Q1 serving as an electronic switch; the source electrode of the first MOS tube is connected with +5V power supply, and the grid electrode of the first MOS tube is connected with a third MOS tube Q10 to receive a power supply starting signal PS _ ON; the drain electrode of the first MOS tube Q1 is connected with a power supply +5VSB of the board to be detected through a self-on-off fuse F1, and is connected with a voltage monitoring chip through voltage dividing resistors R23 and R22, and the voltage monitoring chip outputs a monitoring signal CPLD _ VCC5VSB to the processor. When the device works, the first MOS tube Q1 controls the +5VSB power supply of a tested board through the self-on-off fuse F1, the +5VSB voltage is detected, and the first MOS tube Q1 is cut off through the CPLD when the voltage monitoring chip detects that the voltage is abnormal, so that the purpose of overcurrent protection is achieved. Preferably, the first MOS transistor electronic switch in this embodiment preferably adopts an IRF7416PMOS transistor, and is sensitive to reaction; the voltage monitoring chip adopts a chip MAX 16052.

As a further improvement, the processor circuit is connected with a fan to perform forced air cooling on the board card to be detected, so that the stability and the safety of the detection stage are improved.

The utility model provides a SMT semi-manufactured goods test system mainly provides test circuit so that be applied to in the detection stage of CPU module semi-manufactured goods, especially PC104 CPU module semi-manufactured goods, during the test the utility model discloses test system support plate is installed in testboard equipment, can judge whether normal to the product state to PC104 CPU module semi-manufactured goods feeder terminal static resistance monitoring, judges whether normal to the power operating condition on the product through the monitoring to the power current on the PC104 CPU module semi-manufactured goods; monitoring whether the working state of the board card is normal or not through a DEBUG function and a RESET function in the starting process of the semi-finished product of the PC104 CPU module; whether the basic state of the PC104 bus is normal is judged by monitoring and displaying the port of the PC104 bus 80 of the semi-finished product of the PC104 CPU module; carrying an i82551 network through a PC04+ bus on a semi-finished product of a CPU module of the PC104, carrying out a sending and receiving test, and preliminarily monitoring whether the basic state of the PC104+ bus is normal; the test method comprises the steps of leading out probes for a PS/2 port of a semi-finished product of a PC104 CPU module and a VGA display port, and testing whether the functions are normal or not by utilizing the existing method and test software. Because the half-finished product of PC104 CPU module has the empty and same PC04 bus of standard location, consequently the utility model discloses the commonality is better, does benefit to the improvement product detection efficiency.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. The SMT semi-finished product testing system comprises a power supply module and a carrier plate, and is characterized in that a testing circuit system is arranged on the carrier plate, the testing circuit system comprises a processor, a DEBUG display unit, a bus expansion network unit, a control panel unit, a power supply and protection circuit unit, the DEBUG display unit and the bus expansion network unit which are all in circuit connection with the processor, and the power supply module supplies power for the whole testing circuit system.

2. An SMT semi-finished product testing system according to claim 1, wherein the DEBUG display unit is a PC104 bus extension DEBUG display circuit that includes a bi-directional transceiver that accesses an ISA bus to be able to obtain a test signal of a board under test; the transceiver circuit is connected with the processor, and the processor circuit is connected with a DEBUG display nixie tube.

3. An SMT semi-finished product testing system according to claim 2, wherein the transceiver is an isolation chip SN74LVC 4245.

4. An SMT semi-finished product testing system according to claim 1, wherein the bus expansion network unit includes a PC104 bus expansion network chip, the bus expansion network chip being connected to a PCI + bus for accessing a board under test.

5. An SMT semi-finished product testing system according to claim 1, wherein the control panel unit includes a switch, an indicator light, a reset key, the DEBUG display nixie tube, and a buzzer, all electrically connected to the processor, wherein the indicator light includes a switch indicator light and a reset indicator light.

6. An SMT semi-finished product testing system according to claim 1, wherein the testing circuit further includes a VGA, PS/2 signal output unit; the VGA and PS/2 signal output unit comprises a VGA socket and a PS/2 socket, and the VGA socket and the PS/2 socket are used for being connected to a tested board through a test probe so as to be capable of outputting VGA and PS/2 signals of the tested board.

7. An SMT semi-finished product testing system according to claim 1, wherein the power supply and protection circuit unit includes a power input interface resistance detection circuit and a power-on over-current protection circuit.

8. An SMT semi-finished product testing system according to claim 7, wherein the power input interface resistance detection circuit is configured to detect +5VSB power supply of a board under test; the detection circuit comprises a first operational amplifier U8A and a second operational amplifier U8B, wherein a diode D1 and a protective resistor R17 which are connected in series are arranged between a +5V power supply of the detection circuit and a +5VSB power supply of a detected board and then are connected to the non-inverting input end of the first operational amplifier U8A, and the non-inverting input end is connected with a filter capacitor C32 in series and is grounded; the reverse input end of the first operational amplifier U8A is connected with the output end, and a resistor R74 is arranged between the two ends and grounded; the positive and negative power terminals of the first operational amplifier U8A are respectively connected with +5V voltage and ground; the output end of the first operational amplifier U8A is connected with the non-inverting input end of the second operational amplifier U8B, and the inverting input end of the second operational amplifier U8B is connected with a +5V power supply and the ground through a voltage division resistor R18 and a voltage division resistor R19 respectively; the output end of the second operational amplifier U8B is connected with the grid of the second MOS tube Q2, the source of the second MOS tube is grounded, the drain is connected with the +3.3V power supply through a resistor R20, and the signal CPLD _ PWR _ VSB is output to the processor.

9. An SMT semi-finished product testing system according to claim 7, wherein the power-on over-current protection circuit includes a first MOS transistor Q1 as an electronic switch; the source electrode of the first MOS tube is connected with +5V power supply, and the grid electrode of the first MOS tube is connected with a third MOS tube Q10 to receive a power supply starting signal PS _ ON; the drain electrode of the first MOS tube Q1 is connected with a power supply +5VSB of the board to be detected through a self-on-off fuse F1, and is connected with a voltage monitoring chip through voltage dividing resistors R23 and R22, and the voltage monitoring chip outputs a monitoring signal CPLD _ VCC5VSB to the processor.

10. An SMT semi-finished product testing system according to claim 9, wherein the voltage monitoring chip employs a chip MAX 16052.