CN210625001U - Thermoelectric semiconductor refrigerator - Google Patents
Thermoelectric semiconductor refrigerator Download PDFInfo
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- CN210625001U CN210625001U CN201921221493.6U CN201921221493U CN210625001U CN 210625001 U CN210625001 U CN 210625001U CN 201921221493 U CN201921221493 U CN 201921221493U CN 210625001 U CN210625001 U CN 210625001U
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Abstract
The utility model provides a thermoelectric semiconductor refrigerator belongs to semiconductor refrigeration technical field, and this thermoelectric semiconductor refrigerator includes parallel relative first base plate and second base plate, first base plate has the face the first plane of second base plate, the second base plate has the face the second plane of first base plate with be provided with a plurality of thermocouples between the second base plate, the thermocouple intercommunication first plane with the second plane is in order to form the functional area that has the electric current route first base plate and/or the second base plate still is formed with non-functional area. The first substrate and the second substrate are provided with the non-functional areas which can not form a current path, so that the packaging thermal stress borne by the thermoelectric semiconductor refrigerator is reduced, and the reliability of the thermoelectric semiconductor refrigerator in the use process is effectively improved.
Description
Technical Field
The utility model relates to a semiconductor refrigeration technology field particularly, relates to a thermoelectric semiconductor refrigerator.
Background
Thermoelectric semiconductor refrigerators (TECs) are widely used as solid state refrigeration modules in electronic devices and optoelectronic systems requiring precise temperature control. The thermoelectric semiconductor refrigerator is generally composed of an upper electrically insulating and heat conducting substrate and a lower electrically insulating and heat conducting substrate, and a thermocouple pair sandwiched between the upper and lower substrates, wherein the upper and lower substrates are provided with metal flow deflectors for welding the thermocouple pair in the middle to form an internal series circuit.
In many applications of existing thermoelectric semiconductor coolers (TECs), the TECs need to be packaged and soldered between metal materials; however, there is a large difference between the thermal expansion Coefficients (CTE) of the TEC substrate and the thermocouple, which inevitably causes a problem of failure of the conventional TEC due to excessive residual thermal stress.
Meanwhile, in the application process of the TEC, the TEC is often required to be welded on a metal heat sink with high heat conductivity, so as to reduce the heat conduction resistance of the system and enhance the refrigeration capacity of the TEC. However, the thermal expansion coefficients of the metal heat sink for packaging and the TEC substrate are not matched, the metal heat sink with high thermal conductivity often has a larger CTE, after welding and assembling, the stress inside the welded TEC can be further increased, and the TEC is prone to generate microcracks in a larger stress state, so that the alternating current resistance of the TEC is increased, and the refrigeration efficiency of the TEC is reduced. In severe cases, the thermoelectric material is further broken, which directly results in the failure of the TEC.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a thermoelectric semiconductor cooler can reduce encapsulation residual stress, effectively improves thermoelectric semiconductor cooler in the reliability of use.
The embodiment of the utility model is realized like this:
an aspect of an embodiment of the present invention provides a thermoelectric semiconductor cooler, which includes a first substrate and a second substrate opposite to each other in parallel, wherein the first substrate has a first plane facing the second substrate, the second substrate has a second plane facing the first substrate, a plurality of thermocouples are disposed between the first substrate and the second substrate, the thermocouples communicate with the first plane and the second plane to form a functional region having a current path, the first substrate and/or the second substrate is further formed with a non-functional region.
Optionally, a plurality of flow deflectors are respectively disposed on the first plane and the second plane, the flow deflectors of the first plane correspond to the flow deflectors of the second plane in a staggered manner, and the thermocouples are communicated with the flow deflectors of the first plane and the flow deflectors of the second plane in a staggered manner to form a functional region with a current path.
Optionally, the first substrate further includes a third plane opposite to the first plane, the second substrate further includes a fourth plane opposite to the second plane, a conductive layer is disposed on the third plane and/or the fourth plane, and a hollow area is formed in the non-functional area on the conductive layer on the third plane and/or the conductive layer on the fourth plane.
Optionally, the conductive layer is a gold plating layer.
Optionally, the non-functional area is closed and surrounds the periphery of the functional area, and the hollow area is formed in the whole non-functional area.
Optionally, the non-functional area is at least disposed on one side of the periphery of the functional area, and the hollow area is formed in the whole non-functional area.
Optionally, the surface area of the first substrate in the non-functional region accounts for 10% to 15% of the surface area of the first substrate.
Optionally, the thickness of the first substrate is greater than or equal to 2mm, and/or the thickness of the second substrate is greater than or equal to 2 mm.
Optionally, a semiconductor laser chip is disposed on the third plane and/or the fourth plane.
Optionally, a side of the first substrate and/or the second substrate is provided with an optical element.
The utility model discloses beneficial effect includes:
the embodiment of the utility model provides a thermoelectric semiconductor refrigerator is through setting up the non-functional area that can not form the electric current route at first base plate and second base plate, has got rid of the place that residual stress is the biggest among the prior art to reduce thermoelectric semiconductor refrigerator's encapsulation thermal stress, thereby avoided the too big influence that probably leads to the fact the device stability of residual stress, effectively improved thermoelectric semiconductor refrigerator in the reliability of use.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic view of a thermoelectric semiconductor refrigerator according to an embodiment of the present invention;
fig. 2 is a second schematic structural view of a thermoelectric semiconductor refrigerator according to an embodiment of the present invention;
fig. 3 is a third schematic structural view of a thermoelectric semiconductor refrigerator according to an embodiment of the present invention;
FIG. 4 is a fourth schematic view of a thermoelectric semiconductor cooler according to an embodiment of the present invention;
FIG. 5 is a fifth schematic view of a thermoelectric semiconductor cooler according to an embodiment of the present invention;
FIG. 6 is a sixth schematic view of a thermoelectric semiconductor cooler according to an embodiment of the present invention;
fig. 7 is a seventh schematic view of a thermoelectric semiconductor cooler according to an embodiment of the present invention;
fig. 8 is an eighth schematic structural view of a thermoelectric semiconductor refrigerator according to an embodiment of the present invention.
10-first substrate; 11-a first conductive layer; 20-a second substrate; 21-a second conductive layer; 30-a thermocouple; 301-a first thermocouple; 302-a second thermocouple; 303-third thermocouple; 40A-an upper guide vane; 40a 1-a first upper baffle; 40a 2-second upper baffle; 40B-a lower guide vane; 40B 1-a first lower baffle; 50-a semiconductor laser chip; 60-optical element.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Example one
Referring to fig. 1, the present embodiment provides a thermoelectric semiconductor refrigerator, which includes a first substrate 10 and a second substrate 20 that are opposite in parallel, the first substrate 10 having a first plane facing the second substrate 20, the second substrate 20 having a second plane facing the first substrate 10, a plurality of thermocouples 30 disposed between the first substrate 10 and the second substrate 20, the thermocouples 30 communicating the first plane and the second plane to form a functional region having a current path, and a non-functional region formed on the first substrate 10 and/or the second substrate 20.
It should be noted that, first, the functional region is used to implement a current path, the region outside the functional region is a non-functional region, the non-functional region may surround the functional region in a closed manner, the non-functional region may not completely surround the functional region, and the non-functional region may be located at an edge position of the first substrate 10 and the second substrate 20, or may be located at a certain position in the middle of the first substrate 10 and the second substrate 20.
Second, the first substrate 10 and the second substrate 20 are insulated, and current conduction is achieved only by providing a conductive medium on the first plane and the second plane to form a current path.
Third, in the embodiment of the present invention, the current path may be formed by disposing the conductive channel or the conductive medium (e.g., the current guiding plate) on the first substrate 10 and the second substrate 20 to cooperate with the thermocouple 30 to form the functional region, and all features that can achieve similar or identical functions are considered as equivalent features in the art and belong to the scope of the disclosure or protection of the present application.
The embodiment of the utility model provides a thermoelectric semiconductor refrigerator has got rid of the place that residual stress is the biggest among the prior art through the non-functional area that can not form the current path in first base plate 10 and second base plate 20 setting to reduce thermoelectric semiconductor refrigerator's encapsulation thermal stress, thereby avoided the too big influence that probably leads to the fact the device stability of residual stress, effectively improved thermoelectric semiconductor refrigerator in the reliability of use.
A plurality of flow deflectors are respectively arranged on the first plane and the second plane, the upper flow deflector 40A of the first plane corresponds to the lower flow deflector 40B of the second plane in a staggered manner, a plurality of thermocouples 30 are arranged between the first substrate 10 and the second substrate 20, and the thermocouples 30 are communicated with the upper flow deflector 40A of the first plane and the lower flow deflector 40B of the second plane corresponding to the staggered manner to form a functional area with a current path.
It should be noted that, in the first embodiment, the first substrate 10 and the second substrate 20 may be communicated through the flow deflector, specifically, a plurality of flow deflectors are disposed on both the first plane of the first substrate 10 and the second plane of the second substrate 20, a thermocouple 30 is further disposed between the first plane of the first substrate 10 and the second plane of the second substrate 20, the thermocouple 30 communicates with the upper flow deflector 40A of the first plane and the lower flow deflector 40B of the second plane to form a functional region having a current path, and the functional region is used for providing current to the thermoelectric semiconductor refrigerator.
Secondly, at least two thermocouples 30 are arranged on the upper flow deflector 40A of one first plane in a communicated manner, and each thermocouple 30 is also respectively communicated with one lower flow deflector 40B of the second plane; at least two thermocouples 30 are arranged on the lower guide vane 40B of the second plane in a communicating manner, and each thermocouple 30 is also respectively communicated with one upper guide vane 40A of the first plane.
By providing the guide vane in communication with the thermocouple 30, communication is made between the first substrate 10 and the second substrate 20 to form a functional region having a current path.
In the functional region, a plurality of flow deflectors are arranged on the first substrate 10 and the second substrate 20, each flow deflector is provided with at least two thermocouples 30 to form a thermocouple pair, that is, at least two thermocouples 30 are arranged between an upper flow deflector 40A of a first plane and a lower flow deflector 40B of a corresponding second plane to form a thermocouple pair, for example, as shown in fig. 4, a dotted arrow line in fig. 4 is a current flow direction, after the current is introduced, the current enters a corresponding first thermocouple 301 from a first upper flow deflector 40A1, and then enters another adjacent second thermocouple 302 through another first lower flow deflector 40B1 corresponding to the first thermocouple 301, the first lower flow deflector 40B1 simultaneously corresponds to the first thermocouple 301 and the second thermocouple 302, the thermocouple pair formed by the first thermocouple 301 and the second thermocouple 302 is used for conducting the current, the upper second upper flow deflector 40A2 simultaneously corresponds to the second thermocouple 302 and the third thermocouple 303, the current passes from the second thermocouple 302 to the third thermocouple 303 via the upper second upper deflector 40a2, and so on, and the thermoelectric semiconductor refrigerator of the present embodiment has a plurality of thermocouple pairs thereon.
In the functional area, the upper guide vanes 40A of the first plane and the corresponding lower guide vanes 40B of the second plane are not arranged oppositely, but are staggered, as illustrated in fig. 4, the first lower baffle 40B1 corresponds to the first thermocouple 301 and the second thermocouple 302, and one of the thermocouples 30 is connected to the upper baffle 40A of the first plane, namely, the first thermocouple 301 is communicated with the first upper deflector 40a1, the second thermocouple 302 is communicated with the second upper deflector 40a2, the second upper deflector 40a2 is communicated with the third thermocouple 303, and so on, the first lower deflector 40B1 and the second upper deflector 40a2 are arranged in a staggered manner, by providing the cross-connection, the first substrate 10 and the second substrate 20 may be communicated to form a functional region having current by the thermocouple 30 to communicate the upper guide vane 40A of the first plane with the corresponding lower guide vane 40B of the second plane.
The first substrate 10 further includes a third plane opposite to the first plane, the second substrate 20 further includes a fourth plane opposite to the second plane, a conductive layer is disposed on the third plane and/or the fourth plane, the conductive layer of the third plane is the first conductive layer 11, the conductive layer of the fourth plane is the second conductive layer 21, the conductive layer may be a gold-plated layer and is used for bonding an external temperature control device or a heat sink or a laser chip, and a hollow area is formed in the non-functional area of the first conductive layer 11 on the third plane and/or the second conductive layer 21 on the fourth plane.
In this embodiment, the hollow area is formed in the entire non-functional area, i.e., the hollow area is the non-functional area, the hollow area has no conductive layer therein, and the non-functional area is formed by the hollow area without the conductive layer. The non-functional area is closed and surrounds the periphery of the functional area, and the hollow area is formed in the whole non-functional area.
The first substrate 10 and the second substrate 20 are made of ceramic, the ceramic material has good electrical insulation and thermal conductivity, and the flow deflector can be a metal flow deflector for conducting current.
For example, as shown in fig. 1, a first conductive layer 11 is disposed on the first substrate 10, a region outside the first conductive layer 11 is a hollow region, the hollow region is not disposed with the first conductive layer 11, the region is a non-functional region that cannot conduct electricity, and a region of the first conductive layer 11 is a functional region having a current path.
The non-functional region is disposed at least on one side of the periphery of the functional region. For example, when the first substrate 10 and the second substrate 20 are both rectangular, the conductive layer is also rectangular, and the non-functional region (hollow region) may be located on two sides of the first conductive layer 11 as shown in fig. 2, or located around the first conductive layer 11 as shown in fig. 1 to surround the first conductive layer 11, so that the non-functional region is closed and surrounds the periphery of the functional region, of course, the non-functional region may also be located on only one side or three sides of the first conductive layer 11, etc., and the non-functional region is located at a different position, so that the state of the package residual stress at the position in the TEC can be improved, and thus the specific location of the non-functional region is determined according to actual requirements, and the location relationship between the non-functional region and the second conductive layer 21 is similarly derived.
In practical applications, in order to fully exert the function of the thermoelectric semiconductor cooler (TEC), the area of the external temperature control element or the heat sink (when the heat sink is packaged, the thermoelectric semiconductor cooler and the laser chip need to be integrally fixed to a large heat dissipation block, which is the heat sink) or the laser chip bonded to the surface of the conductive layer is usually larger than the area of the conductive layer, and since the hollowed-out area cannot form a bonding interface with the external temperature control element or the heat sink or the laser chip, the thermal stress of the thermoelectric semiconductor cooler thermocouple 30 can be effectively reduced.
Meanwhile, the first substrate 10 and the second substrate 20 may be provided with a conductive layer at the same time, or only one of them may be provided with a conductive layer.
As shown in fig. 3 and 4, the surface area of the first substrate 10 in the non-functional region generally occupies 10% to 15% of the surface area of the first substrate 10. The specific surface area of the non-functional area can be comprehensively evaluated according to the change relationship of the stress along with the surface area of the non-functional area and the change relationship of the TEC heat dissipation efficiency and the surface area along with the non-functional area.
The embodiment of the utility model provides a thermoelectric semiconductor refrigerator, through the conducting layer on shrink first base plate 10 and/or the second base plate 20, make the edge can't form bonding interface with outside accuse temperature component or heat sink or laser chip, through reducing the bonding area between first base plate 10 and/or second base plate 20 and outside accuse temperature component or the metal heat sink or the laser chip, can reduce the encapsulation thermal stress that thermoelectric semiconductor refrigerator received greatly, effectively improve the reliability of thermoelectric semiconductor refrigerator in the use.
Since package residual stress has a marginal effect, namely: the thermoelectric material at the edge of the TEC has a maximum stress, and the stress gradually decreases to a zero stress state from the edge to the center of the TEC. Therefore, the first preferred solution of the embodiment is to provide the non-functional region that cannot form a current path at the edge of the first substrate 10 and the second substrate 20, so as to remove the place where the residual stress is the largest in the prior art, so as to reduce the package thermal stress of the thermoelectric semiconductor cooler, improve the state of the package residual stress in the TEC, thereby avoiding the influence that the excessive residual stress may cause on the device stability, and achieve the effect of improving the reliability of the thermoelectric semiconductor cooler.
Example two
As shown in fig. 5, the thickness of the first substrate 10 and/or the second substrate 20 is 2mm or more.
The basic thickness of the ceramic substrate of the existing thermoelectric semiconductor cooler is smaller than 1.0mm, although the Young modulus of the ceramic is large and the thermal expansion coefficient is small, the thin ceramic plate can not effectively prevent the thermal stress generated in the packaging process from being transferred to the thermocouple 30, and can not effectively relieve the residual packaging stress from being transferred to the thermoelectric material in the TEC. The present embodiment improves the reliability of the thermoelectric semiconductor cooler by thickening the first and second substrates 10 and 20 to reduce the stress that transitions into the thermocouple 30 pair.
As shown in fig. 6 and 7, the thickness of the first substrate 10 or the second substrate 20 may be increased independently, or the thickness of the first substrate 10 and the thickness of the second substrate 20 may be increased simultaneously.
As shown in fig. 8, the first substrate 10 further includes a third plane opposite to the first plane, the second substrate 20 further includes a fourth plane opposite to the second plane, the third plane and/or the fourth plane are provided with semiconductor laser chips 50, and the side surfaces of the first substrate 10 and/or the second substrate 20 are provided with optical elements 60.
A sub-heat sink (when a chip is arranged on the surface of the thermoelectric semiconductor refrigerator, the thermoelectric semiconductor refrigerator and the chip have different materials, when the chip generates heat, the thermoelectric semiconductor refrigerator and the chip have different thermal stresses, and the sub-heat sink is arranged between the chip and the thermoelectric semiconductor refrigerator and used for the stress caused by the different materials) welded with the first substrate 10 and the second substrate 20 can be omitted, the welding interface of the thermoelectric semiconductor refrigerator is reduced, and the reliability of the whole thermoelectric semiconductor refrigerator is improved; because the first substrate 10 and the second substrate 20 are thick enough, for a chip with a concentrated heat source, the semiconductor laser chip 50 can be directly surface-mounted on the third plane of the first substrate 10 or the fourth plane of the second substrate 20, or the semiconductor laser chip 50 is mounted on both the third plane and the fourth plane, without additionally adding a heat sink; for the optoelectronic device, the required optical element 60 may also be directly mounted on the side of the first substrate 10 or the side of the second substrate 20, or both the side of the first substrate 10 and the side of the second substrate 20 may be mounted with the optical element 60.
When the thermoelectric semiconductor refrigerator is used, the thermoelectric semiconductor refrigerator radiates heat for a laser chip, the optical element 60 shapes laser emitted by the laser chip, the thickness of the existing TEC ceramic is 1.0mm, and the semiconductor laser chip 50 and the optical element 60 cannot be added on the side edge of the TEC because the thermoelectric semiconductor refrigerator is too thin, so that the semiconductor laser chip 50 and the optical element 60 can be directly arranged on a substrate in the embodiment, the complex connection relation is omitted, the whole thermoelectric semiconductor refrigerator is simple in structure, and the functional effect is more obvious.
The present embodiment improves the reliability of the thermoelectric semiconductor refrigerator by thickening the first and second substrates 10 and 20, thereby reducing the stress that transits into the thermocouple 30 pair.
The two embodiments relate to the technical field of semiconductor refrigeration, can be widely applied to all fields using thermoelectric semiconductor refrigerators (TECs), including optical communication semiconductor lasers, high-power semiconductor lasers and the like, and can also be applied to the fields of laser devices, medical treatment, industrial processing and the like.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A thermoelectric semiconductor cooler, comprising: the thermoelectric module comprises a first substrate and a second substrate which are opposite in parallel, wherein the first substrate is provided with a first plane facing the second substrate, the second substrate is provided with a second plane facing the first substrate, a plurality of thermocouples are arranged between the first substrate and the second substrate, the thermocouples are communicated with the first plane and the second plane to form a functional area with a current path, and a non-functional area is further formed on the first substrate and/or the second substrate.
2. A thermoelectric semiconductor cooler according to claim 1, wherein a plurality of flow deflectors are respectively provided on the first plane and the second plane, and the flow deflectors of the first plane correspond to the flow deflectors of the second plane in an interlaced manner, and the thermocouple communicates the flow deflectors of the first plane and the flow deflectors of the second plane in an interlaced manner to form a functional region having a current path.
3. The thermoelectric semiconductor refrigerator according to claim 1, wherein the first substrate further comprises a third plane opposite to the first plane, the second substrate further comprises a fourth plane opposite to the second plane, a conductive layer is disposed on the third plane and/or the fourth plane, and a hollow area is formed on the non-functional area of the conductive layer on the third plane and/or the conductive layer on the fourth plane.
4. A thermoelectric semiconductor cooler according to claim 3, wherein said electrically conductive layer is a gold plating layer.
5. A thermoelectric semiconductor cooler according to claim 3, wherein the non-functional region is closed around the periphery of the functional region, and the hollowed-out region is formed over the non-functional region.
6. A thermoelectric semiconductor cooler according to claim 3, wherein said non-functional region is provided at least on one side of the periphery of said functional region, and said hollowed-out region is formed throughout said non-functional region.
7. A thermoelectric semiconductor cooler according to any one of claims 1 to 6, wherein the surface area of the first substrate in the nonfunctional area is 10-15% of the surface area of the first substrate.
8. A thermoelectric semiconductor cooler according to any one of claims 1 to 6, wherein said first substrate has a thickness of 2mm or more and/or said second substrate has a thickness of 2mm or more.
9. A thermoelectric semiconductor cooler according to claim 3, wherein a semiconductor laser chip is provided on the third and/or fourth planes.
10. A thermoelectric semiconductor cooler according to claim 3 or 9, characterized in that the sides of the first and/or second substrate are provided with optical elements.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921221493.6U CN210625001U (en) | 2019-07-30 | 2019-07-30 | Thermoelectric semiconductor refrigerator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921221493.6U CN210625001U (en) | 2019-07-30 | 2019-07-30 | Thermoelectric semiconductor refrigerator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110345663A (en) * | 2019-07-30 | 2019-10-18 | 西安炬光科技股份有限公司 | Thermoelectric semiconductor refrigerator and thermoelectric cooler module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110345663A (en) * | 2019-07-30 | 2019-10-18 | 西安炬光科技股份有限公司 | Thermoelectric semiconductor refrigerator and thermoelectric cooler module |
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