CN210536770U

CN210536770U - Hundred million level pixel array camera device

Info

Publication number: CN210536770U
Application number: CN201922310807.6U
Authority: CN
Inventors: 尹江明; 陈小天; 唐新春; 王大雷; 邵逢仙; 黄营磊
Original assignee: Hunan Aoying Chuangshi Information Technology Co Ltd
Current assignee: Hunan Aoying Chuangshi Information Technology Co Ltd
Priority date: 2019-12-20
Filing date: 2019-12-20
Publication date: 2020-05-15
Anticipated expiration: 2029-12-20

Abstract

The utility model relates to the technical field of industrial cameras, and discloses a hundred million-level pixel array camera device to improve the resolution of an industrial camera, wherein the camera device comprises an imaging module, which is used for acquiring the optical information of an object to be shot and obtaining imaging photon information according to the optical information; the sensor control module is used for preprocessing the imaging photon information to obtain an electronic image signal; the acquisition module is used for acquiring the electronic image signals in real time, encoding the electronic image signals and transmitting the encoded electronic image signals to the processing module through the transmission module; the transmission module is used for converting the electronic image signal after the coding processing into an optical fiber signal and transmitting the optical fiber signal to the processing module; and the processing module is used for receiving the optical fiber signal and processing the optical fiber signal to generate an image.

Description

Hundred million level pixel array camera device

Technical Field

The utility model relates to an industry camera technical field especially relates to a hundred million grades of pixel array camera device.

Background

In daily use, the industrial camera has wide application in scenes such as video detection, scene learning and the like, and with the increasing use rate of the industrial camera, the requirements of people on the industrial camera are also increasing. The applied industrial camera in the market is mainly limited by conditions such as manufacturing process, optical resolution, phase difference and sampling rate, so that the video acquisition resolution of a single chip is limited, 80M pixels are a bottleneck of most manufacturers, and under the current industrial means, the problem can be solved only by continuously amplifying the area of the chip, but the cost problem caused by the method can be improved according to exponential level. Some manufacturers adjust the pixel size of the chip down to improve the resolution, so that the exposure time and the processing time are increased to obtain clear imaging, the output frame frequency can only reach 1 frame or 2 frames per second, and only camera phones, not real-time cameras, can be manufactured by adopting the method. At present, some manufacturers do not obtain high-resolution cameras, so that pixels break through hundred million levels, hundreds of cameras with 4K x 4K are overlapped in volume, and a plurality of lenses are used for realizing a compound-eye camera. And the multi-part camera can only output a video with a fixed frame format and a fixed view angle, and the details interested in the view angle cannot be displayed in high resolution.

Therefore, how to improve the resolution of the industrial camera becomes an urgent problem to be solved.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a hundred million grades of pixel array camera devices to improve the resolution ratio of industry camera.

To achieve the above object, the present invention provides a hundred million level pixel array imaging device, comprising:

the imaging module is used for acquiring optical information of an object to be shot and acquiring imaging photon information according to the optical information;

the sensor control module is used for preprocessing the imaging photon information to obtain an electronic image signal;

the acquisition module is used for acquiring the electronic image signal in real time, encoding and then transmitting the electronic image signal to the processing module through the transmission module;

the transmission module is used for converting the electronic image signal after the coding processing into an optical fiber signal and transmitting the optical fiber signal to the processing module;

and the processing module is used for receiving the optical fiber signal and processing the optical fiber signal to generate an image.

Preferably, the imaging module includes a lens and a sensor photosurface, and the sensor photosurface and the lens are arranged according to a preset angle so that imaging photon information is imaged at a set position of the sensor photosurface.

Preferably, the preset angle ranges from 45 degrees or less.

Preferably, the sensor control module includes: the interface chip comprises a first acquisition chip GMAX4651, an interface chip ERM5-040-02.0-L-DV-TR and a peripheral circuit of the interface chip, wherein the peripheral circuit of the interface chip comprises a capacitor C2 and a capacitor C3;

the 1 st pin to the 68 th pin of the chip ERM5-040-02.0-L-DV-TR are data transmission pins, the data transmission pins are respectively connected with data transmission pins of an acquisition chip GMAX4651, the 69 th pin of the chip ERM5-040-02.0-L-DV-TR is respectively connected with the 71 th pin, the 73 th pin, the 75 th pin, the 77 th pin and the 79 th pin and then grounded, the 70 th pin of the chip ERM5-040-02.0-L-DV-TR is respectively connected with the 72 th pin, the 74 th pin, the 76 th pin, the 78 th pin and the 80 th pin, and simultaneously connected with one end of the capacitor C2 and one end of the capacitor C3, and the other end of the C2 is connected with the other end of the capacitor C3 and then grounded.

Preferably, the acquisition module comprises: the interface chip ERM5-040-02.0-L-DV-TR, the second acquisition chip xc7K160T-2FFG676xc7K160T-2FFG676, the polar capacitor C55, the capacitor C56 and the capacitor C57;

the VCCO _13 pin of the second acquisition chip xc7K160T-2FFG676 is connected to one end of the polar capacitor C55, one end of the capacitor C56, and one end of the capacitor C57, respectively, and the other end of the polar capacitor C55 is connected to the other end of the capacitor C56 and the other end of the capacitor C57, respectively, and then grounded.

Preferably, the transmission module includes a chip 74441-;

one end of the inductor L20 is connected to one end of the inductor L21 and the FPGA _ VCC3V3 terminal respectively, the other end of the inductor L20 is connected to the VCCR pin of the chip 74441-0010 and one end of the polar capacitor C141, the VCCR pin of the chip 74441 and 0010 is connected to the VCC3V3 terminal, the other end of the inductor L21 is connected to one end of the polar capacitor C143 of the chip, one end of the capacitor C144 and the VCCT pin of the chip 74441 and 0010, the other end of the polar capacitor C141 is connected to one end of the capacitor C142, the other end of the polar capacitor C143, the other end of the capacitor C144, and the VEET _3 pin of the chip 74441 and 0010, respectively, and the terminals are grounded, the other end of the capacitor C142 is connected to a VCC3V3 end, and the VEER _1 pin, the VEER _2 pin, the VEER _3 pin, the VEET _1 pin and the VEET _2 pin of the chip 74441 and 0010 are all connected to the VEET _3 pin;

one end of the resistor R108 is connected to one end of the resistor R109, one end of the resistor R110, one end of the resistor R111, one end of the resistor R112, one end of the resistor R113, the anode of the light emitting diode D7, and one end of the resistor R114, respectively, and the ends are connected to a VCC3V3 end, the other end of the resistor R108 is connected to a TX _ FAULT pin of a chip 74441-, the other end of the resistor R116 is connected with the base electrode of the triode Q20, the emitter electrode of the triode Q20 is grounded, the cathode of the light emitting diode D7 is connected with one end of the resistor R115, the other end of the resistor R115 is connected with the collector electrode of the triode Q20, and the other end of the resistor R114 is connected with the collector electrode of the triode Q20;

the resistor R118 is connected to one end of the resistor R119, and the end is connected to a VCC3V3 end, the other end of the resistor R118 is respectively connected to the RS0 pin of the chip 74441-.

The utility model discloses following beneficial effect has:

the utility model provides a pair of hundred million level pixel array camera device, this camera device includes: the imaging module is used for acquiring optical information of an object to be shot and acquiring imaging photon information according to the optical information; the sensor control module is used for preprocessing the imaging photon information to obtain an electronic image signal; the acquisition module is used for acquiring the electronic image signals in real time, encoding the electronic image signals and transmitting the encoded electronic image signals to the processing module through the transmission module; the transmission module is used for converting the electronic image signal after the coding processing into an optical fiber signal and transmitting the optical fiber signal to the processing module; the processing module is used for receiving the optical fiber signal and processing the optical fiber signal to generate an image; the camera device can improve the visual angle and the resolution of the industrial camera.

The present invention will be described in further detail below with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. In the drawings:

fig. 1 is a block diagram of a hundred million class pixel array imaging device according to a preferred embodiment of the present invention;

FIG. 2 is a circuit diagram of a sensor control module of a preferred embodiment of the present invention;

fig. 3 is a circuit diagram of a portion of an acquisition module according to a preferred embodiment of the present invention;

fig. 4 is another circuit diagram of a portion of the acquisition module of the preferred embodiment of the present invention;

fig. 5 is a circuit diagram of a transmission module according to a preferred embodiment of the present invention.

Detailed Description

The embodiments of the invention will be described in detail below with reference to the drawings, but the invention can be implemented in many different ways as defined and covered by the claims.

As shown in fig. 1, the present embodiment provides a giga-level pixel array image pickup apparatus including:

the acquisition module is used for acquiring the electronic image signals in real time, encoding the electronic image signals and transmitting the encoded electronic image signals to the processing module through the transmission module;

The hundred million level pixel array camera shooting device can improve the visual angle and the resolution of an industrial camera. The resolution of the image pickup device of the hundred million level pixel array in the embodiment can reach 2 hundred million resolution and above.

As a preferred embodiment of this embodiment, the imaging module includes a lens and a sensor photosensitive surface, and the sensor photosensitive surface and the lens are disposed at a preset angle so that the imaging photon information is imaged at a set position of the sensor photosensitive surface. In this embodiment, the range of the preset angle is not more than 45 degrees. This angle setting can make the formation of image of outside focus distinguish the formation of image in the side position of camera lens, simultaneously, through the relative position of adjustment sensor photosurface and camera lens, can distinguish the formation of image on 2 sensor photosurfaces with the light beam of a camera lens different positions. By the design of the porous common-mirror composite imaging optical structure, a huge optical structure, a plurality of sensor arrays and a plurality of processing center arrays are omitted, and the size of the camera device can be reduced to the maximum extent. The size of the image pickup device in the embodiment can be 300x 300x 160 mm. The camera in the embodiment is small in size and convenient to carry.

In order to ensure imaging effect and present a perfect image in different application environments, the sensor control module in this embodiment automatically manages the chip on the control circuit, outputs the chip synchronously, and performs optimal configuration of parameters according to feedback from the back end.

In this embodiment, as shown in fig. 2, the sensor control module includes: the interface chip comprises a first acquisition chip GMAX4651, an interface chip ERM5-040-02.0-L-DV-TR and a peripheral circuit of the interface chip, wherein the peripheral circuit of the interface chip comprises a capacitor C2 and a capacitor C3;

the 1 st pin to the 68 th pin of the chip ERM5-040-02.0-L-DV-TR are data transmission pins, the data transmission pins are respectively connected with the data transmission pins of the acquisition chip GMAX4651, the 69 th pin of the chip ERM5-040-02.0-L-DV-TR is respectively connected with the 71 th pin, the 73 th pin, the 75 th pin, the 77 th pin and the 79 th pin and then grounded, the 70 th pin of the chip ERM5-040-02.0-L-DV-TR is respectively connected with the 72 th pin, the 74 th pin, the 76 th pin, the 78 th pin and the 80 th pin, and is simultaneously connected with one end of a capacitor C2 and one end of a capacitor C3, and the other end of the C2 is connected with the other end of a capacitor C3 and then grounded.

As a preferred embodiment of this embodiment, the acquisition module in this embodiment uses an FPGA to perform custom direct acquisition, so that a space of a video acquisition coding chip is saved, acquisition work and video coding on LVDS signals are completed, and ISP control is completed.

Specifically, as shown in fig. 3 and 4, the acquisition module includes: the interface chip ERM5-040-02.0-L-DV-TR, the second acquisition chip xc7K160T-2FFG676xc7K160T-2FFG676, the polar capacitor C55, the capacitor C56 and the capacitor C57;

the VCCO _13 pin of the second acquisition chip xc7K160T-2FFG676 is connected with one end of a polar capacitor C55, one end of a capacitor C56 and one end of a capacitor C57 respectively, and the other end of the polar capacitor C55 is connected with the other end of a capacitor C56 and the other end of a capacitor C57 respectively and then grounded.

As a preferred embodiment of this embodiment, in order to ensure real-time transmission processing of high-speed video, a video data transmission bandwidth with a resolution of 2 hundred million is as high as 2GB/S, so that high-speed signals are seriously received by external interference, and the transmission loss of electrical signals is very large, therefore, the transmission module in this embodiment performs internal video signal serial coding by using photoelectric conversion, obtains high-speed serial signals and converts the serial signals into optical signals, and through optical fiber transmission, the transmission bandwidth maximally supports 4GB/S, and the transmission can be improved to 80 KM.

In this embodiment, as shown in fig. 5, the transmission module includes a chip 74441-;

one end of an inductor L20 is respectively connected with one end of an inductor L21 and an FPGA _ VCC3V3 end, the other end of an inductor L20 is respectively connected with a VCCR pin of a chip 74441-;

one end of the resistor R108 is connected to one end of the resistor R109, one end of the resistor R110, one end of the resistor R111, one end of the resistor R112, one end of the light emitting diode D7 of the resistor R113, and one end of the resistor R114, which are connected to the VCC3V3 terminal, the other end of the resistor R108 is connected to the TX _ FAULT pin of the chip 74441-, the other end of the resistor R115 is connected with the collector of the triode Q20, and the other end of the resistor R114 is connected with the collector of the triode Q20;

the resistor R118 is connected to one end of the resistor R119, and the end is connected to the VCC3V3 end, the other end of the resistor R118 is respectively connected to the RS0 pin of the chip 74441-.

As a preferred embodiment of this embodiment, the processing module adopts a processing architecture of FPGA + GPU, and performs operations such as video splicing, target detection, target recognition, and video encoding and decoding by using the flexible coding characteristics and real-time processing characteristics of FPGA and the ultra-strong parallel computing characteristics of GPU.

As a preferred embodiment of the present embodiment, the image capturing apparatus further includes a power control module to complete functions of power supply, power consumption management, abnormality recovery, and the like of the entire image capturing apparatus. It should be noted that the power control module is an existing module, and only the above functions need to be satisfied when selecting the type. Here, the description is omitted.

In this embodiment, through the mutual cooperation of the six modules, after the high-speed acquisition, the high-speed transmission and the high-speed processing of the 4-channel sensor are completed, a situation video, a window video, a high-resolution real video and the like can be output in real time according to an instruction.

The main processing work of the processing module is as follows: firstly, reading configuration information and initializing splicing parameters. Then 4 video capture threads are created, one for each video source. And starting video acquisition. And 2 encoding threads, one encoding panoramic data and one encoding detail data are created. And the splicing module receives all video acquisition data, and performs panoramic splicing after each path of acquisition is finished. After splicing is finished, the panoramic data and the detail data are respectively sent to a panoramic coding thread and a detail coding thread. After the encoding is completed, the encoding thread sends the encoded video data to a streaming server (rtsp, rtmp or file) through the streaming output module. And synchronously sending the coded video to a video detection module for detection processing; further, the client accesses the playing page through a browser, or directly plays the video stream through a player such as a VLC. The user can drag the detail frame in the browser to set the position of the detail video. And sending the data to the splicing system through an http command. And after receiving the command, an http service module in the splicing system sets parameter information of the detail video, and in the subsequent splicing process, outputs the detail data of the new position.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An image pickup apparatus of a one hundred million level pixel array, comprising:

2. The image capture device of claim 1, wherein the imaging module comprises a lens and a sensor photosensitive surface, and the sensor photosensitive surface and the lens are arranged at a predetermined angle to enable imaging photon information to be imaged at a predetermined position of the sensor photosensitive surface.

3. The image capturing apparatus of claim 2, wherein the predetermined angle is within a range of 45 degrees or less.

4. The image capture device of one hundred million pixel arrays according to claim 1, wherein the sensor control module comprises: the interface chip comprises a first acquisition chip GMAX4651, an interface chip ERM5-040-02.0-L-DV-TR and a peripheral circuit of the interface chip, wherein the peripheral circuit of the interface chip comprises a capacitor C2 and a capacitor C3;

5. The image capture device of one hundred million level pixel array of claim 1, wherein the acquisition module comprises: the interface chip ERM5-040-02.0-L-DV-TR, the second acquisition chip xc7K160T-2FFG676, the polar capacitor C55, the capacitor C56 and the capacitor C57;

6. The device as claimed in claim 1, wherein the transmission module comprises a chip 74441 and 0010 and peripheral circuits thereof, the peripheral circuits comprise an inductor L20, an inductor L21, a polar capacitor C141, a polar capacitor C143, a capacitor C142, a capacitor C144, a resistor R108, a resistor R109, a resistor R110, a resistor R111, a resistor R112, a resistor R113, a resistor R114, a resistor R115, a resistor R116, a resistor R117, a resistor R118, a resistor R119, a resistor R120, a resistor R121, a light emitting diode D7 and a transistor U20;