CN210526310U - Electric eddy speed damper control system for automobile - Google Patents

Electric eddy speed damper control system for automobile Download PDF

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Publication number
CN210526310U
CN210526310U CN201921531147.8U CN201921531147U CN210526310U CN 210526310 U CN210526310 U CN 210526310U CN 201921531147 U CN201921531147 U CN 201921531147U CN 210526310 U CN210526310 U CN 210526310U
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cpu
storage battery
power supply
input
optocoupler
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丁左武
梅旭
倪永娟
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Nanjing Dingbo Controller Co Ltd
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Nanjing Dingbo Controller Co Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02TCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
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    • Y02T10/64Electric machine technologies in electromobility

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Abstract

The utility model relates to an eddy current retarder control system for automobile, the first pulse width modulation signal output end of CPU is connected with the control pulse input end of a retarder drive module through an optical coupler, and the drive pulse output end of the retarder drive module is respectively connected with the grid of each excitation drive IGBT; the collector of each excitation drive IGBT is connected with the anode of the storage battery, and the excitation coil of the eddy current retarder is connected between the emitter of each excitation drive IGBT and the cathode of the storage battery; a plurality of excitation unit freewheeling diodes which are mutually connected in parallel are connected between the emitter of each excitation driving IGBT and the cathode of the storage battery. The storage battery provides +5V power supply for the CPU through the voltage reduction chip, and provides +15V power supply for each driving module through the voltage reduction chip. And each gear switch of the gear shifting handle is respectively connected with ports PA0, PA1, PA2, PA3 and PA4 of the CPU through an optical coupler so as to change the input duty ratio. The system changes the braking force of the retarder by controlling the current of the excitation coil, so that the eddy current retarder is safe and reliable, and the driving comfort is good.

Description

Electric eddy speed damper control system for automobile
Technical Field
The utility model relates to a retarder stopper for car, in particular to eddy current retarder control system for car belongs to car retarder brake control technical field.
Background
With the development of the expressway and the improvement of the requirements of people on driving comfort and safety, higher and higher requirements are put forward on the automobile retarder.
Under the conditions of frequent braking and deceleration and long-distance downhill braking of the heavy-duty vehicle, the retarder can be started, so that stable deceleration is realized, and abrasion and heating caused by braking are avoided. The retarder can not only improve the safety and reliability of automobile running, but also reduce the abrasion of the brake shoe block and the wheel hub of the automobile and the maintenance cost, thereby being popular with automobile manufacturers and automobile users. The retarder in the market mainly comprises several types such as an eddy current retarder, a hydraulic retarder and the like.
The heat generated in the working process of the eddy current retarder can not be effectively dissipated in time, the temperature of the retarder is far over 100 ℃ due to the heat generated in the working process of the eddy current retarder, and a shell of the eddy current retarder even becomes a fireball due to overhigh temperature.
The controller of the existing eddy current retarder utilizes four electromagnetic relays to supply power to four excitation coils. In the first gear, one relay in the four relays is switched on, and one excitation coil works; in the second gear, two relays in the four relays are switched on, and two excitation coils work; in the third gear, three relays in the four relays are switched on, and three excitation coils work; and in the fourth gear, the four relays are fully switched on, and the four magnet exciting coils work. The controller with the structure can not realize stepless gear shifting.
The time lag of the hydraulic retarder during engagement is long, and the lag time after disengagement is also long; the power loss is large when the device does not work; the mechanical transmission part is complex, the structure is more complex when the mechanical transmission part is particularly used for a trailer, and the retarder works effectively when the vehicle runs at low speed.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome the problem that exists among the prior art, provide an eddy current retarder control system for car, the electric current size through control eddy current retarder excitation coil changes the brake force of retarber, makes eddy current retarder safe and reliable, and it is good to drive the travelling comfort.
IN order to solve the technical problem, the utility model discloses an eddy current retarder control system for automobile, including CPU, CPU's pulse width modulation signal output end CPU-PWM1 links to each other with the input of sixth opto-coupler G6, and the output of sixth opto-coupler G6 links to each other with retarder drive module U3's control pulse input U3-IN, and retarder drive module's drive pulse output U3-HO links to each other with the grid that excites the drive IGBT respectively; the collector of each excitation drive IGBT is connected with the positive electrode of the storage battery, and the excitation coil LX of the eddy current retarder is connected between the emitter of each excitation drive IGBT and the negative electrode of the storage battery; a plurality of excitation unit freewheeling diodes which are mutually connected in parallel are connected between the emitter of each excitation driving IGBT and the cathode of the storage battery.
Compared with the prior art, the utility model discloses following beneficial effect has been obtained: the maximum working current of the excitation coil LX of the eddy current retarder exceeds 100A and even can reach 150A, and although the rated working current of a single IGBT can reach 150A, the heat dissipation of the IGBT in practical application cannot reach the optimal state; the pins of the IGBT cannot bear large current for a long time; the excessive current causes the internal resistance of the IGBT to generate heat seriously. The heat generated during the turn-on and turn-off of the IGBT seriously affects the safe operation of the controller. To the eddy current retarder in the course of the work, eddy current retarder excitation coil LX's operating voltage is lower, the higher problem of operating current, the utility model discloses a plurality of parallelly connected IGBT1, IGBT2 to IGBTn drive eddy current retarder's eddy current retarder excitation coil LX each other to adopt a plurality of parallelly connected excitation unit freewheeling diodes EJG1, EJG2 to EJGn of each other to carry out the afterflow. When the IGBT1, the IGBT2 to IGBTn are turned off, the self-induction current generated by the self-induced electromotive force of the eddy current retarder excitation coil LX may be consumed inside the eddy current retarder excitation coil LX through the excitation unit freewheel diodes EJG1, EJG2 to EJGn. A duty ratio signal output by a CPU-PWM1 (pulse width modulation signal output end of the CPU) is isolated by a high voltage and a low voltage of a sixth optical coupler G6 and is sent to a control pulse input end U3-IN of a retarder driving module U3, the duty ratio signal is output by a driving pulse output end U3-HO after being amplified by the retarder driving module U3, and the duty ratios of the IGBT1, the IGBT2 and the IGBTn are controlled after current limiting by current limiting resistors XLR1 and XLR2 to XLRn, so that the current regulation of an excitation coil LX of the eddy current retarder is realized.
As an improvement of the present invention, the shift handle of the eddy current retarder is provided with an automatic shift switch K0, a first shift switch K1, a second shift switch K2, a third shift switch K3 and a fourth shift switch K4, the automatic shift switch K0 is connected in series to the input end of a first optical coupler G1, and the output end of the first optical coupler G1 is connected to the PA0 port of the CPU; the first-gear switch K1 is connected in series with the input end of the second optocoupler G2, and the output end of the second optocoupler G2 is connected with the PA1 port of the CPU; the second-gear switch K2 is connected in series with the input end of a third optocoupler G3, and the output end of the third optocoupler G3 is connected with the PA2 port of the CPU; the three-gear switch K3 is connected in series with the input end of a fourth optocoupler G4, and the output end of the fourth optocoupler G4 is connected with the PA3 port of the CPU; the four-gear switch K4 is connected in series with the input end of a fifth optocoupler G5, and the output end of the fifth optocoupler G5 is connected with the PA4 port of the CPU. A gear shifting handle with five gears is used as a gear shifting signal input element, the working voltage of a gear switch is +24V, the working voltage of a control system CPU is +5V, high-voltage and low-voltage isolation is performed by adopting a light coupler, and the light couplers from the first light coupler G1 to the fifth light coupler G5 can adopt PAB 817. When the gear shifting handle is shifted to the first gear, the automatic gear switch K0 and the first gear switch K1 are closed, the other gear switches are all in an off state, the PA0 of the CPU is logic '1', the PA1 is logic '1', the PA2 is logic '0', the PA3 is logic '0', the PA4 is logic '0', the duty ratio output by the pulse width modulation signal output end CPU-PWM1 of the CPU is 1/4, and the current of the corresponding excitation coil LX of the eddy current retarder is 37A. When the gear shifting handle is shifted to the second gear, the automatic gear switch K0, the first gear switch K1 and the second gear switch K2 are closed, the other gear switches are all in an off state, the PA0 of the CPU is logic '1', the PA1 is logic '1', the PA2 is logic '1', the PA3 is logic '0', the PA4 is logic '0', the duty ratio output by the pulse width modulation signal output end of the CPU-PWM1 is 2/4, and the current of the corresponding exciting coil LX of the eddy current retarder is 74A. When the gear shifting handle is shifted to a third gear, the automatic gear switch K0, the first gear switch K1, the second gear switch K2 and the third gear switch K3 are closed, the fourth gear switch K4 is in an off state, the PA0 of the CPU is logic '1', the PA1 is logic '1', the PA2 is logic '1', the PA3 is logic '1', the PA4 is logic '0', the duty ratio output by the pulse width modulation signal output end of the CPU-PWM1 is 3/4, and the current of the corresponding excitation coil LX of the eddy current retarder is 101A. When the gear shifting handle is shifted to a fourth gear, the automatic gear switch K0, the first gear switch K1, the second gear switch K2, the third gear switch K3 and the fourth gear switch K4 are all closed, the PA0 of the CPU is logic '1', the PA1 is logic '1', the PA2 is logic '1', the PA3 is logic '1', the PA4 is logic '1', the duty ratio output by the pulse width modulation signal output end of the CPU-PWM1 is 4/4, and the current of the corresponding excitation coil LX of the eddy current retarder is 148A. When the vehicle runs on a long slope, the gear shifting handle can be shifted to an automatic gear when the vehicle speed is more than 10km/h, the automatic gear switch K0 is closed, and other gear switches are in an off state; the pin PA0 is changed from logic '0' to '1', the PA1 is logic '0', the PA2 is logic '0', the PA3 is logic '0', the PA4 is logic '0', the cruise control mode is started, the CPU reads the vehicle running speed value, the duty ratio of the PWM1 is adjusted by using a PID algorithm, and the duty ratios of the IGBT1 and the IGBT2 to IGBTn are adjusted, so that the vehicle running speed is constant. In the automatic gear mode, the duty ratio output by a pulse width modulation signal output end CPU-PWM1 is larger than the duty ratio of the first gear and smaller than or equal to the duty ratio of the fourth gear.
As a further improvement of the utility model, the battery anode is connected with the voltage input end U1-VIN of the voltage reduction chip U1 after being sequentially connected with the thermistor RM and the diode D6 in series, the voltage sensitive resistor YM is connected in series between the thermistor RM and the battery cathode, and the freewheeling diode D7 and the capacitor C1 are connected in parallel between the voltage input end U1-VIN of the voltage reduction chip U1 and the battery cathode; a voltage output end I U1-SW of the voltage reduction chip I U1 is connected with a CPU-GND through a slide rheostat I HR1, a pin at the upper end of the slide rheostat I HR1 provides a +5V power supply for the CPU, and the middle end of the slide rheostat I HR1 is connected with a feedback pin I U1-FB of the voltage reduction chip I U1; a voltage input end II U2-VIN of the voltage reduction chip II U2 is connected with a voltage input end I U1-VIN of the voltage reduction chip I U1 in parallel, a voltage output end II U2-SW of the voltage reduction chip II U2 is connected with the cathode of the storage battery through a sliding rheostat II HR2, the upper end of the sliding rheostat II HR2 provides +15V power for each driving module, and the middle end of the sliding rheostat II HR2 is connected with a feedback pin II U2-FB of the voltage reduction chip II U2; the voltage reduction chip I U1 and the voltage reduction chip II U2 both adopt XL4016 modules, and the negative electrode of the storage battery is connected with the CPU-GND through an inductor L1. In the utility model, the power supply voltage for the CPU is +5V, and the power supply voltage for the driving module is + 15V; the maximum current of the excitation coil LX of the eddy current retarder exceeds 100A, so that the end voltage of the storage battery is reduced more, and the end voltage is unstable. The thermistor RM is a positive temperature coefficient, so that the impact of the voltage on the input voltage of the XL4016 module when the terminal voltage of the storage battery is greatly changed can be effectively buffered; the piezoresistor YM can further buffer the impact of overhigh self-induced electromotive force generated by the exciting coil LX of the eddy current retarder on the XL4016 module when the IGBT is turned off; when the terminal voltage of the storage battery is reduced to be lower than the allowable input voltage of the XL4016 module, the diode D6 can effectively prevent the current from flowing backwards; the capacitor C1 acts as a voltage regulator, keeping the input voltage of the XL4016 module higher than the minimum allowable input voltage for a long period of time. The voltage output end U1-SW of the voltage reduction chip I U1 can accurately output +5V voltage for the CPU to use through the resistance value adjustment of the slide rheostat I HR 1. The voltage output end two U2-SW of the voltage reduction chip two U2 can accurately output +15V voltage for each driving module to use through the resistance value adjustment of the sliding rheostat two HR 2. The inductance L1 can reduce the effect of the battery terminal voltage variation on the voltage used by the CPU.
As a further improvement of the present invention, a pulse width modulation signal output end CPU-PWM1 of the CPU is connected to an input positive electrode of a sixth optical coupler G6 through a current limiting resistor R19, an input negative electrode of the sixth optical coupler G6 is connected to a CPU-GND, and a pull-down resistor R20 is connected between the input positive electrode and the input negative electrode of the sixth optical coupler G6; the collector of the output end of the sixth optical coupler G6 is connected with a +15V power supply, the emitter of the output end of the sixth optical coupler G6 is connected with the control pulse input end U3-IN of the retarder drive module U3, the control pulse input end U3-IN is connected with the cathode of the storage battery through a pull-down resistor R21, and the output end of the sixth optical coupler G6 is connected with a freewheeling diode D10 IN parallel; the operating power supply end U3-Vcc of the retarder driving module U3 is connected with +15V power supply, the input ground end U3-COM of the retarder driving module U3 is connected with the cathode of the storage battery and is connected with +15V power supply through a capacitor C10, the upper end of the eddy current retarder excitation coil LX is connected with the output stage reference ground end U3-Vs, the output stage reference ground end U3-Vs is connected with the output stage operating power supply end U3-VB through a capacitor C11, and the output stage operating power supply end U3-VB is connected with +15V power supply through a diode D11; two ends of the excitation coil LX of the eddy current retarder are connected in series with a resistor R22 and a capacitor C12. A duty ratio signal output by a CPU-PWM1 at a pulse width modulation signal output end of the CPU is limited by a current limiting resistor R19 and then is sent to an input end of a sixth optical coupler G6, when a pull-down resistor R20 ensures that the CPU-PWM1 outputs a logic level '0', the level of the input end of the sixth optical coupler G6 is also logic '0', and a light-emitting diode ensures that the light-emitting diode can be reliably cut off; when the voltage at the control pulse input end U3-IN of the retarder driving module U3 suddenly rises, the freewheeling diode D10 freewheels; the capacitor C10 is used as a voltage stabilizing capacitor, and the capacitor C11 and the diode D11 form a bootstrap circuit to generate VB voltage; the resistor R22 and the capacitor C12 form a first energy storage circuit. After the retarder driving module U3 amplifies the duty ratio signal input by the control pulse input end U3-IN, the same duty ratio is output by the driving pulse output end U3-HO, and the on-off of the IGBTn, the IGBT1 and the IGBT2 are controlled.
As a further improvement of the utility model, a normally open contact of a relay JD1 is connected between the collector and the emitter of each excitation drive IGBT, a coil of the relay JD1 is connected between the anode and the cathode of the storage battery and is connected in series with a temperature control switch WK, and the temperature control switch WK is installed on the circuit board; a detection branch is connected between a coil of the relay JD1 and the temperature-controlled switch WK, the detection branch comprises a detection resistor R31 and a detection resistor R32 which are connected in series, the detection resistor R31 and the detection resistor R32 are connected with a PAD1 port of the CPU, and the lower end of the detection resistor R32 is connected with the CPU-GND. When the temperature of the circuit board exceeds a set value, for example, exceeds 120 ℃, the normally open type temperature controlled switch WK is closed, the coil of the relay JD1 is energized to close the normally open contact, and the voltage difference between the collector and the emitter of the IGBT1, the IGBT2 to the IGBTn is reduced to 0V, so that the temperature of the circuit board is reduced. When the temperature-controlled switch WK is closed, the voltage value between the detection resistor R31 and the detection resistor R32 changes, the PAD1 port of the CPU receives a signal that the circuit board is overheated, the CPU enables the duty ratio output by a pulse width modulation signal output end CPU-PWM1 to be 0, and the IGBT1, the IGBT2 to the IGBTn stop working, so that the circuit board is further protected.
As a further improvement of the present invention, the three-CPU-PWM 3 pulse width modulation signal output terminal of the CPU is connected to the input anode of the seventh optical coupler G7 through a current limiting resistor R23, the input cathode of the seventh optical coupler G7 is connected to the CPU-GND, and a pull-down resistor R24 is connected between the input anode and the input cathode of the seventh optical coupler G7; the collector of the output end of the seventh optocoupler G7 is connected with a +15V power supply, the emitter of the output end of the seventh optocoupler G7 is connected with a control pulse input end U4-IN of a brake lamp driving module U4, the control pulse input end U4-IN is connected with the cathode of the storage battery through a pull-down resistor R25, and the output end of the seventh optocoupler G7 is connected with a freewheeling diode D12 IN parallel; the working power supply end U4-Vcc of the brake lamp driving module U4 is connected with a +15V power supply, the input ground end U4-COM of the brake lamp driving module U4 is connected with the cathode of the storage battery and is connected with the +15V power supply through a capacitor C13, the upper end of the brake lamp LP1 is connected with the output stage reference ground end U4-Vs, the output stage reference ground end U4-Vs is connected with the output stage working power supply end U4-VB through a capacitor C14, and the output stage working power supply end U4-VB is connected with the +15V power supply through a diode D13; the driving pulse output end U4-HO of the brake lamp driving module U4 is connected with the grid electrode of the brake lamp driving IGBTn +1 through a current-limiting resistor XLRn +1, the collector electrode of the brake lamp driving IGBTn +1 is connected with the anode of the storage battery, and the brake lamp LP1 is connected between the emitter electrode of the brake lamp driving IGBTn +1 and the cathode of the storage battery; a brake unit freewheeling diode EJGn +1 is connected between the emitting electrode of the brake lamp driving IGBTn +1 and the cathode of the storage battery, and a resistor R26 and a capacitor C15 are connected in series between the two ends of the brake lamp LP 1. The vehicle is usually provided with six brake lights, the total power is 144W, and the total rated working current is 4A. When braking, the brake gear switch is shifted to enable a pin PA0 of the CPU to be changed into logic '1', a pulse width modulation signal output end three CPU-PWM3 of the CPU outputs a 4/4 duty ratio signal, the current is limited by a current limiting resistor R23 and then is sent to an input end of a seventh optical coupler G7, a pull-down resistor R24 ensures that when the CPU-PWM3 outputs logic level '0', the level of the input end of the seventh optical coupler G7 is also logic '0', and a light-emitting diode can be reliably cut off; when the voltage at the control pulse input terminal U4-IN of the brake lamp driving module U4 suddenly rises, the freewheeling diode D12 freewheels. The capacitor C13 is used as a voltage stabilizing capacitor, and the capacitor C14 and the diode D13 form a bootstrap circuit to generate VB voltage; the resistor R26 and the capacitor C15 form a second energy storage circuit. Through the isolation of the seventh optocoupler G7, a 4/4 duty ratio signal is sent to a control pulse input end U4-IN of a brake lamp driving module U4, amplified by the brake lamp driving module U4, and then output a 4/4 duty ratio signal through a driving pulse output end U4-HO to control IGBTn +1 to be switched on, so that the brake lamp is lightened. IGBTn +1 can be NPN type IGBT tube with rated working current of 40A.
As a further improvement of the present invention, the pulse width modulation signal output end of the CPU, five CPU-PWM5, is connected to the input anode of the eighth optocoupler G8 through a current limiting resistor R27, the input cathode of the eighth optocoupler G8 is connected to the CPU-GND, and a pull-down resistor R28 is connected between the input anode and the input cathode of the eighth optocoupler G8; the collector of the output end of the eighth optocoupler G8 is connected with a +15V power supply, the emitter of the output end of the eighth optocoupler G8 is connected with a control pulse input end U5-IN of a motor driving module U5, the control pulse input end U5-IN is connected with the cathode of the storage battery through a pull-down resistor R29, and the output end of the eighth optocoupler G8 is connected with a freewheeling diode D14 IN parallel; the working power supply end U5-Vcc of the motor driving module U5 is connected with a +15V power supply, the input ground end U5-COM of the motor driving module U5 is connected with the cathode of the storage battery and is connected with a +15V power supply through a capacitor C16, the upper end of a cooling liquid pump motor M1 is connected with an output-level reference ground end U5-Vs, the output-level reference ground end U5-Vs is connected with an output-level working power supply end U5-VB through a capacitor C17, and the output-level working power supply end U5-VB is connected with the +15V power supply through a diode D15; a driving pulse output end U5-HO of the motor driving module U5 is connected with a grid electrode of a motor driving IGBT through a current limiting resistor XLRn +2, a collector electrode of the motor driving IGBT is connected with the anode of a storage battery, and a cooling liquid pump motor M1 and a fan motor M2 are connected between an emitter electrode of the motor driving IGBT and the cathode of the storage battery in parallel; a motor unit freewheeling diode EJGn +2 is connected between the emitter of the motor drive IGBT and the cathode of the storage battery, and a resistor R30 and a capacitor C18 are connected between the two ends of a cooling liquid pump motor M1 in series. The rated power of the cooling liquid pump motor M1 is about 120W, and the rated working current is 5A; the rated power of the fan motor M2 is about 72W, and the rated working current is 3A; the IGBTn +2 can be selected from NPN type IGBT tubes with rated working current of 80A. After the automobile is started, a pulse width modulation signal output end of a CPU (Central processing Unit) -PWM (pulse width modulation) 5 outputs a 4/4 duty ratio signal, the current is limited by a current limiting resistor R27 and then is sent to an input end of an eighth optocoupler G8, when a pull-down resistor R28 ensures that the CPU-PWM5 outputs logic level '0', the level of the input end of the eighth optocoupler G8 is also logic '0', and a light-emitting diode ensures that the light-emitting diode can be reliably cut off; when the voltage of the control pulse input end U5-IN of the motor driving module U5 suddenly rises, the freewheeling diode D14 carries out freewheeling; the capacitor C16 is used as a voltage stabilizing capacitor, and the capacitor C17 and the diode D15 form a bootstrap circuit to generate VB voltage; the resistor R30 and the capacitor C18 form a third energy storage circuit. Through the isolation of the eighth optocoupler G8, a 4/4 duty ratio signal is sent to a control pulse input end U5-IN of a motor driving module U5, amplified by the motor driving module U5, and then output a 4/4 duty ratio signal through a driving pulse output end U5-HO to control IGBTn +2 to be switched on, so that a cooling liquid pump motor M1 and a fan motor M2 are started.
As a further improvement of the invention, the speed signal output end of a speed sensor S1 of the automobile is connected with the speed signal input end PJ6 of the CPU through a current limiting resistor R16, a pull-up resistor R17 is connected in series between the speed signal input end PJ6 and the CPU +5V power supply, the grounding end of the speed sensor S1 of the automobile is connected with the CPU-GND, and a capacitor C8 is arranged between the speed signal input end PJ6 of the CPU and the CPU-GND; a cooling liquid flow passage 1C of a stator of the eddy current retarder is internally provided with a T1 of a cooling liquid temperature sensor, a temperature signal output end of a T1 of the cooling liquid temperature sensor is connected with a temperature signal input end PAD0 of a CPU, a pull-up resistor R18 is connected in series between the temperature signal input end PAD0 and a power supply of the CPU +5V, a grounding end of a T1 of the cooling liquid temperature sensor is connected with the negative electrode of a storage battery, and a capacitor C9 is arranged between the temperature signal input end PAD0 of the CPU and the negative electrode of the storage. The invention adopts the speed signal output by the speed sensor S1 of the gear box as the speed detection signal of the retarder control system, and the CPU reads the Hall signal value by utilizing the PJ6 port with the external interrupt function and provides the speed signal for the cruise mode. T1 of the coolant temperature sensor is a negative temperature coefficient, the resistance value at 100 ℃ is 4.52k omega, and the resistance value at 20 ℃ is 42.16k omega; the CPU reads the PAD0 value, and through interpolation, the stator cooling liquid temperature value of the retarder can be calculated.
Drawings
The invention will be described in further detail with reference to the drawings and the detailed description, which are provided for reference and illustration purposes only and are not intended to limit the invention.
Fig. 1 is the utility model discloses well gearshift handle switches to the input signal working principle picture of different gears.
Fig. 2 is a peripheral circuit diagram of the CPU of the present invention.
Fig. 3 is an electrical schematic diagram of the +5V/+15V power supply for the control system of the present invention.
Fig. 4 is the utility model discloses well speed of a motor vehicle detects branch diagram.
Fig. 5 is the utility model discloses well eddy current retarder's stator cooling liquid temperature detects branch diagram.
Fig. 6 is the utility model discloses well eddy current retarder excitation coil drive circuit and circuit board overheat protection circuit schematic diagram.
Fig. 7 is a schematic diagram of a driving circuit of the brake lamp of the present invention.
Fig. 8 is a schematic diagram of a driving circuit of the pump motor and the fan motor of the present invention.
Detailed Description
As shown in fig. 1, the automatic gear switch K0 and the current-limiting resistor R1 are connected in series between the positive pole of the battery and the input positive pole of the first optocoupler G1, the input negative pole of the first optocoupler G1 is connected to the negative pole of the battery, and the battery voltage is usually 24V. A pull-down resistor R2 is connected between the input positive electrode and the input negative electrode of the first optical coupler G1, the collector of the output end of the first optical coupler G1 is connected with a +5V power supply of the CPU, the emitter of the output end of the first optical coupler G1 is connected with a PA0 port of the CPU and is connected with GND of the CPU through a pull-down resistor R3; the output end of the first optical coupler G1 is connected in parallel with a freewheeling diode D1.
A first-gear switch K1 and a current-limiting resistor R4 are connected in series between the anode of a storage battery and the input anode of a second optocoupler G2, the input cathode of the second optocoupler G2 is connected with the cathode of the storage battery, a pull-down resistor R5 is connected between the input anode and the input cathode of the second optocoupler G2, the collector of the output end of the second optocoupler G2 is connected with a +5V power supply of the CPU, the emitter of the output end of the second optocoupler G2 is connected with the PA1 port of the CPU and is connected with the GND of the CPU through a pull-down resistor R6; and the output end of the second optical coupler G2 is connected with a freewheeling diode D2 in parallel.
A two-gear switch K2 and a current-limiting resistor R7 are connected in series between the anode of a storage battery and the input anode of a third optocoupler G3, the input cathode of the third optocoupler G3 is connected with the cathode of the storage battery, a pull-down resistor R8 is connected between the input anode and the input cathode of the third optocoupler G3, the collector of the output end of the third optocoupler G3 is connected with a +5V power supply of the CPU, the emitter of the output end of the third optocoupler G3 is connected with the PA2 port of the CPU and is connected with the GND of the CPU through a pull-down resistor R9; and the output end of the third optical coupler G3 is connected with a freewheeling diode D3 in parallel.
A third-gear switch K3 and a current-limiting resistor R10 are connected in series between the anode of a storage battery and the input anode of a fourth optocoupler G4, the input cathode of the fourth optocoupler G4 is connected with the cathode of the storage battery, a pull-down resistor R11 is connected between the input anode and the input cathode of the fourth optocoupler G4, the collector of the output end of the fourth optocoupler G4 is connected with a +5V power supply of the CPU, the emitter of the output end of the fourth optocoupler G4 is connected with the PA3 port of the CPU and is connected with the GND of the CPU through a pull-down resistor R12; the output end of the fourth optical coupler G4 is connected in parallel with a freewheeling diode D4.
A four-gear switch K4 and a current-limiting resistor R13 are connected in series between the anode of a storage battery and the input anode of a fifth optocoupler G5, the input cathode of the fifth optocoupler G5 is connected with the cathode of the storage battery, a pull-down resistor R14 is connected between the input anode and the input cathode of the fifth optocoupler G5, the collector of the output end of the fifth optocoupler G5 is connected with a +5V power supply of the CPU, the emitter of the output end of the fifth optocoupler G5 is connected with a PA4 port of the CPU and is connected with GND of the CPU through a pull-down resistor R15; and the output end of the fifth optical coupler G5 is connected with a freewheeling diode D5 in parallel.
A gear shifting handle with five gears is used as a gear shifting signal input element, the working voltage of a gear switch is +24V, the working voltage of a control system CPU is +5V, high-voltage and low-voltage isolation is performed by adopting a light coupler, and the light couplers from the first light coupler G1 to the fifth light coupler G5 can adopt PAB 817.
When the gear shifting handle is shifted to the first gear, the automatic gear switch K0 and the first gear switch K1 are closed, the other gear switches are all in an off state, the PA0 of the CPU is logic '1', the PA1 is logic '1', the PA2 is logic '0', the PA3 is logic '0', the PA4 is logic '0', the duty ratio output by the pulse width modulation signal output end CPU-PWM1 of the CPU is 1/4, and the current of the corresponding excitation coil LX of the eddy current retarder is 37A.
When the gear shifting handle is shifted to the second gear, the automatic gear switch K0, the first gear switch K1 and the second gear switch K2 are closed, the other gear switches are all in an off state, the PA0 of the CPU is logic '1', the PA1 is logic '1', the PA2 is logic '1', the PA3 is logic '0', the PA4 is logic '0', the duty ratio output by the pulse width modulation signal output end of the CPU-PWM1 is 2/4, and the current of the corresponding exciting coil LX of the eddy current retarder is 74A.
When the gear shifting handle is shifted to a third gear, the automatic gear switch K0, the first gear switch K1, the second gear switch K2 and the third gear switch K3 are closed, the fourth gear switch K4 is in an off state, the PA0 of the CPU is logic '1', the PA1 is logic '1', the PA2 is logic '1', the PA3 is logic '1', the PA4 is logic '0', the duty ratio output by the pulse width modulation signal output end of the CPU-PWM1 is 3/4, and the current of the corresponding excitation coil LX of the eddy current retarder is 101A.
When the gear shifting handle is shifted to a fourth gear, the automatic gear switch K0, the first gear switch K1, the second gear switch K2, the third gear switch K3 and the fourth gear switch K4 are all closed, the PA0 of the CPU is logic '1', the PA1 is logic '1', the PA2 is logic '1', the PA3 is logic '1', the PA4 is logic '1', the duty ratio output by the pulse width modulation signal output end of the CPU-PWM1 is 4/4, and the current of the corresponding excitation coil LX of the eddy current retarder is 148A.
When the vehicle runs on a long slope, the gear shifting handle can be shifted to an automatic gear when the vehicle speed is more than 10km/h, the automatic gear switch K0 is closed, and other gear switches are in an off state; the pin PA0 is changed from logic '0' to '1', the PA1 is logic '0', the PA2 is logic '0', the PA3 is logic '0', the PA4 is logic '0', the cruise control mode is started, the CPU reads the vehicle running speed value, the duty ratio of the PWM1 is adjusted by using a PID algorithm, and the duty ratios of the IGBT1 and the IGBT2 to IGBTn are adjusted, so that the vehicle running speed is constant. In the automatic gear mode, the duty ratio output by a pulse width modulation signal output end CPU-PWM1 is larger than the duty ratio of the first gear and smaller than or equal to the duty ratio of the fourth gear.
As shown in fig. 2 and 3, the positive electrode of the storage battery is sequentially connected in series with the thermistor RM and the diode D6 and then connected with the voltage input end U1-VIN of the voltage-reducing chip i U1, the bypass capacitor pin i U1-VC of the voltage-reducing chip i U1 is connected with the voltage input end U1-VIN through the capacitor C2, the piezoresistor YM is connected in series between the thermistor RM and the negative electrode of the storage battery, the freewheel diode D7 and the capacitor C1 are connected in parallel between the voltage input end U1-VIN of the voltage-reducing chip i U1 and the negative electrode of the storage battery, and the ground pin i U1-GND of the voltage-reducing chip i U1 is connected with the negative electrode of the storage battery; a voltage output end I U1-SW of the voltage reduction chip I U1 is connected with a CPU-GND through an inductor L2 and a sliding rheostat I HR1 in sequence, the inductor L2 provides a +5V power supply for the CPU through a pin between the sliding rheostat I HR1, and the middle end of the sliding rheostat I HR1 is connected with a feedback pin I U1-FB of the voltage reduction chip I U1; a freewheeling diode D8 is connected between a voltage output end U1-SW of the first voltage reduction chip U1 and the CPU-GND, and a capacitor C3 and a capacitor C4 are connected between the lower end of the inductor L2 and the CPU-GND in parallel.
A voltage input end two U2-VIN of the voltage reduction chip II U2 is connected with a voltage input end one U1-VIN of the voltage reduction chip I U1 in parallel, a bypass capacitor pin II U2-VC of the voltage reduction chip II U2 is connected with a voltage input end two U2-VIN of the voltage reduction chip II U2 through a capacitor C5, and a grounding pin II U2-GND of the voltage reduction chip II U2 is connected with the cathode of the storage battery; a voltage output end two U2-SW of the voltage reduction chip two U2 is connected with the cathode of the storage battery through an inductor L3 and a sliding rheostat two HR2 in sequence, the inductor L3 provides a +15V power supply for the retarder driving module U3 through a pin between the sliding rheostat two HR2, and the middle end of the sliding rheostat two HR2 is connected with a feedback pin two U2-FB of the voltage reduction chip two U2; a freewheeling diode D9 is connected between a voltage output end two U2-SW of the second voltage reduction chip U2 and the cathode of the storage battery, a capacitor C6 and a capacitor C7 are connected between the lower end of the inductor L3 and the cathode of the storage battery in parallel, and XL4016 modules are adopted for the first voltage reduction chip U1 and the second voltage reduction chip U2.
In the utility model, the power supply voltage for the CPU is +5V, and the power supply voltage for the driving module is + 15V; the maximum current of the excitation coil LX of the eddy current retarder exceeds 100A, so that the end voltage of the storage battery is reduced more, and the end voltage is unstable. The thermistor RM is a positive temperature coefficient, so that the impact of the voltage on the input voltage of the XL4016 module when the terminal voltage of the storage battery is greatly changed can be effectively buffered; the piezoresistor YM can further buffer the impact of overhigh self-induced electromotive force generated by the exciting coil LX of the eddy current retarder on the XL4016 module when the IGBT is turned off; when the terminal voltage of the storage battery is reduced to be lower than the allowable input voltage of the XL4016 module, the diode D6 can effectively prevent the current from flowing backwards; the capacitor C1 acts as a voltage regulator, keeping the input voltage of the XL4016 module higher than the minimum allowable input voltage for a long period of time.
The voltage output end U1-SW of the voltage reduction chip I U1 can accurately output +5V voltage for the CPU to use through the resistance value adjustment of the slide rheostat I HR 1. The inductor L2, the capacitor C3 and the capacitor C4 form a filter circuit and a voltage stabilizing circuit at the output end of the voltage reduction chip I U1, so that the +5V voltage used by the CPU can be more stable; when the voltage of the CPU-GND suddenly rises, the freewheeling diode D8 freewheels.
The voltage output end two U2-SW of the voltage reduction chip two U2 can accurately output +15V voltage for each driving module to use through the resistance value adjustment of the sliding rheostat two HR 2. The inductor L3, the capacitor C6 and the capacitor C7 form a filter circuit and a voltage stabilizing circuit at the output end of the second buck chip U2, so that the voltage of +15V for each driving module can be more stable, and when the voltage of the cathode of the storage battery suddenly rises, the freewheeling diode D9 freewheels.
The negative pole of the storage battery is connected with the CPU-GND through the inductor L1, so that the influence of the change of the terminal voltage of the storage battery on the voltage used by the CPU can be reduced.
As shown in FIG. 4, the speed signal output end of a speed sensor S1 of the automobile is connected with the speed signal input end PJ6 of the CPU through a current limiting resistor R16, a pull-up resistor R17 is connected in series between the speed signal input end PJ6 and the power supply of the CPU +5V, the grounding end of the speed sensor S1 is connected with the CPU-GND, and a capacitor C8 is arranged between the speed signal input end PJ6 of the CPU and the CPU-GND. The utility model discloses a speed signal of the speed of a motor vehicle that gearbox speed sensor S1 exported detects the signal as retarber control system' S speed, and CPU utilizes the PJ6 mouth that has the outside function of interrupting to read hall signal value, provides speed signal for the mode of cruising.
As shown in fig. 5, a coolant temperature sensor T1 is installed in the coolant flow channel 1C of the eddy current retarder stator, the temperature signal output end of the coolant temperature sensor T1 is connected with the temperature signal input end PAD0 of the CPU, a pull-up resistor R18 is connected in series between the temperature signal input end PAD0 and the CPU +5V power supply, the grounding end of the coolant temperature sensor T1 is connected with the negative electrode of the battery, and a capacitor C9 is arranged between the temperature signal input end PAD0 of the CPU and the negative electrode of the battery. T1 of the coolant temperature sensor is a negative temperature coefficient, the resistance value at 100 ℃ is 4.52k omega, and the resistance value at 20 ℃ is 42.16k omega; the CPU reads the PAD0 value, and through interpolation, the stator cooling liquid temperature value of the retarder can be calculated.
As shown in fig. 2 and fig. 6, the eddy current retarder system may share a CPU of the vehicle control system, or may use the CPU alone, where the CPU alone may use an MC9S12XS128MAA single chip microcomputer, or may use a single chip microcomputer with another name, and herein, only the MC9S12XS128MAA single chip microcomputer is taken as an example. A pulse width modulation signal output end CPU-PWM1 of the CPU is connected with an input end of a sixth optical coupler G6, an output end of the sixth optical coupler G6 is connected with a control pulse input end U3-IN of a retarder drive module U3, a drive pulse output end U3-HO of the retarder drive module is connected with the positive pole of a storage battery through a current limiting resistor XLR1, XLR 2-XLRn and excitation drive IGBTn 1, IGBTn 2-IGBTn grids, the collectors of the excitation drive IGBT1, the IGBT 2-IGBTn are connected with the positive pole of the storage battery through a fuse RX, and an electric eddy current retarder LX is connected between the emitters of the excitation drive IGBT1, the IGBT 2-IGBTn and the negative pole of the storage battery; a plurality of excitation unit freewheeling diodes EJG1, EJG2 to EJGn connected in parallel with each other are connected between the emitters of the excitation drive IGBTs 1, IGBTs 2 to IGBTn and the negative electrode of the storage battery. The excitation drive IGBT1, the IGBTs 2 to IGBTn are connected in parallel with each other, and the excitation unit freewheel diodes EJG1, EJG2 to EJGn are connected in parallel with each other.
The maximum working current of the excitation coil LX of the eddy current retarder exceeds 100A and even can reach 150A, and although the rated working current of a single IGBT can reach 150A, the heat dissipation of the IGBT in practical application cannot reach the optimal state; the pins of the IGBT cannot bear large current for a long time; the excessive current causes the internal resistance of the IGBT to generate heat seriously. The heat generated during the turn-on and turn-off of the IGBT seriously affects the safe operation of the controller.
To the eddy current retarder in the course of the work, eddy current retarder excitation coil LX's operating voltage is lower, the higher problem of operating current, the utility model discloses a plurality of parallelly connected IGBT1, IGBT2 to IGBTn drive eddy current retarder's eddy current retarder excitation coil LX each other to adopt a plurality of parallelly connected excitation unit freewheeling diodes EJG1, EJG2 to EJGn of each other to carry out the afterflow. When the IGBT1, the IGBT2 to IGBTn are turned off, the self-induction current generated by the self-induced electromotive force of the eddy current retarder excitation coil LX may be consumed inside the eddy current retarder excitation coil LX through the excitation unit freewheel diodes EJG1, EJG2 to EJGn.
A duty ratio signal output by a CPU-PWM1 (pulse width modulation signal output end of the CPU) is isolated by a high voltage and a low voltage of a sixth optical coupler G6 and is sent to a control pulse input end U3-IN of a retarder driving module U3, the duty ratio signal is output by a driving pulse output end U3-HO after being amplified by the retarder driving module U3, and the duty ratios of the IGBT1, the IGBT2 and the IGBTn are controlled after current limiting by current limiting resistors XLR1 and XLR2 to XLRn, so that the current regulation of an excitation coil LX of the eddy current retarder is realized.
A pulse width modulation signal output end of the CPU, namely a CPU-PWM1, is connected with an input anode of a sixth optocoupler G6 through a current-limiting resistor R19, an input cathode of the sixth optocoupler G6 is connected with a CPU-GND, and a pull-down resistor R20 is connected between the input anode and the input cathode of the sixth optocoupler G6; the collector of the output end of the sixth optical coupler G6 is connected with a +15V power supply, the emitter of the output end of the sixth optical coupler G6 is connected with the control pulse input end U3-IN of the retarder driving module U3, the control pulse input end U3-IN is connected with the cathode of the storage battery through a pull-down resistor R21, and the output end of the sixth optical coupler G6 is connected with a freewheeling diode D10 IN parallel.
The operating power supply end U3-Vcc of the retarder driving module U3 is connected with +15V power supply, the input ground end U3-COM of the retarder driving module U3 is connected with the cathode of the storage battery and is connected with +15V power supply through a capacitor C10, the upper end of the eddy current retarder excitation coil LX is connected with the output stage reference ground end U3-Vs, the output stage reference ground end U3-Vs is connected with the output stage operating power supply end U3-VB through a capacitor C11, and the output stage operating power supply end U3-VB is connected with +15V power supply through a diode D11; two ends of the excitation coil LX of the eddy current retarder are connected in series with a resistor R22 and a capacitor C12.
A duty ratio signal output by a CPU-PWM1 at a pulse width modulation signal output end of the CPU is limited by a current limiting resistor R19 and then is sent to an input end of a sixth optical coupler G6, when a pull-down resistor R20 ensures that the CPU-PWM1 outputs a logic level '0', the level of the input end of the sixth optical coupler G6 is also logic '0', and a light-emitting diode ensures that the light-emitting diode can be reliably cut off; when the voltage at the control pulse input end U3-IN of the retarder driving module U3 suddenly rises, the freewheeling diode D10 freewheels; the capacitor C10 is used as a voltage stabilizing capacitor, and the capacitor C11 and the diode D11 form a bootstrap circuit to generate VB voltage; the resistor R22 and the capacitor C12 form a first energy storage circuit. After the retarder driving module U3 amplifies the duty ratio signal input by the control pulse input end U3-IN, the same duty ratio is output by the driving pulse output end U3-HO, and the on-off of the IGBTn, the IGBT1 and the IGBT2 are controlled.
As shown in fig. 6, a normally open contact of a relay JD1 is connected between the collector and emitter of each excitation drive IGBT, a coil of the relay JD1 is connected between the positive and negative electrodes of the battery and a temperature controlled switch WK is connected in series, and the temperature controlled switch WK is mounted on the circuit board. When the temperature of the circuit board exceeds a set value, for example, exceeds 120 ℃, the normally open type temperature controlled switch WK is closed, the coil of the relay JD1 is energized to close the normally open contact, and the voltage difference between the collector and the emitter of the IGBT1, the IGBT2 to the IGBTn is reduced to 0V, so that the temperature of the circuit board is reduced.
A detection branch is connected between a coil of the relay JD1 and the temperature-controlled switch WK, the detection branch comprises a detection resistor R31 and a detection resistor R32 which are connected in series, the detection resistor R31 and the detection resistor R32 are connected with a PAD1 port of the CPU, and the lower end of the detection resistor R32 is connected with the CPU-GND. When the temperature-controlled switch WK is closed, the voltage value between the detection resistor R31 and the detection resistor R32 changes, the PAD1 port of the CPU receives a signal that the circuit board is overheated, the CPU enables the duty ratio output by a pulse width modulation signal output end CPU-PWM1 to be 0, and the IGBT1, the IGBT2 to the IGBTn stop working, so that the circuit board is further protected.
As shown in fig. 7, a pulse width modulation signal output end of the CPU, i.e., three CPU-PWM3, is connected to an input positive electrode of a seventh optocoupler G7 through a current limiting resistor R23, an input negative electrode of the seventh optocoupler G7 is connected to the CPU-GND, and a pull-down resistor R24 is connected between the input positive electrode and the input negative electrode of the seventh optocoupler G7; the collector of the output end of the seventh optical coupler G7 is connected with a +15V power supply, the emitter of the output end of the seventh optical coupler G7 is connected with the control pulse input end U4-IN of the brake lamp driving module U4, the control pulse input end U4-IN is connected with the cathode of the storage battery through a pull-down resistor R25, and the output end of the seventh optical coupler G7 is connected with a freewheeling diode D12 IN parallel.
The working power supply end U4-Vcc of the brake lamp driving module U4 is connected with a +15V power supply, the input ground end U4-COM of the brake lamp driving module U4 is connected with the cathode of the storage battery and is connected with the +15V power supply through a capacitor C13, the upper end of the brake lamp LP1 is connected with the output stage reference ground end U4-Vs, the output stage reference ground end U4-Vs is connected with the output stage working power supply end U4-VB through a capacitor C14, and the output stage working power supply end U4-VB is connected with the +15V power supply through a diode D13; the driving pulse output end U4-HO of the brake lamp driving module U4 is connected with the grid electrode of the brake lamp driving IGBTn +1 through a current-limiting resistor XLRn +1, the collector electrode of the brake lamp driving IGBTn +1 is connected with the anode of the storage battery, and the brake lamp LP1 is connected between the emitter electrode of the brake lamp driving IGBTn +1 and the cathode of the storage battery; a brake unit freewheeling diode EJGn +1 is connected between the emitting electrode of the brake lamp driving IGBTn +1 and the cathode of the storage battery, and a resistor R26 and a capacitor C15 are connected in series between the two ends of the brake lamp LP 1.
The vehicle is usually provided with six brake lights, the total power is 144W, and the total rated working current is 4A. When braking, the brake gear switch is shifted to enable a pin PA0 of the CPU to be changed into logic '1', a pulse width modulation signal output end three CPU-PWM3 of the CPU outputs a 4/4 duty ratio signal, the current is limited by a current limiting resistor R23 and then is sent to an input end of a seventh optical coupler G7, a pull-down resistor R24 ensures that when the CPU-PWM3 outputs logic level '0', the level of the input end of the seventh optical coupler G7 is also logic '0', and a light-emitting diode can be reliably cut off; when the voltage at the control pulse input terminal U4-IN of the brake lamp driving module U4 suddenly rises, the freewheeling diode D12 freewheels. The capacitor C13 is used as a voltage stabilizing capacitor, and the capacitor C14 and the diode D13 form a bootstrap circuit to generate VB voltage; the resistor R26 and the capacitor C15 form a second energy storage circuit.
Through the isolation of the seventh optocoupler G7, a 4/4 duty ratio signal is sent to a control pulse input end U4-IN of a brake lamp driving module U4, amplified by the brake lamp driving module U4, and then output a 4/4 duty ratio signal through a driving pulse output end U4-HO to control IGBTn +1 to be switched on, so that the brake lamp is lightened. IGBTn +1 can be NPN type IGBT tube with rated working current of 40A.
As shown in fig. 8, a pulse width modulation signal output end five CPU-PWM5 of the CPU is connected to an input positive electrode of an eighth optocoupler G8 through a current limiting resistor R27, an input negative electrode of the eighth optocoupler G8 is connected to the CPU-GND, and a pull-down resistor R28 is connected between the input positive electrode and the input negative electrode of the eighth optocoupler G8; the collector of the output end of the eighth optical coupler G8 is connected with a +15V power supply, the emitter of the output end of the eighth optical coupler G8 is connected with the control pulse input end U5-IN of the motor driving module U5, the control pulse input end U5-IN is connected with the cathode of the storage battery through a pull-down resistor R29, and the output end of the eighth optical coupler G8 is connected with a freewheeling diode D14 IN parallel.
The working power supply end U5-Vcc of the motor driving module U5 is connected with a +15V power supply, the input ground end U5-COM of the motor driving module U5 is connected with the cathode of the storage battery and is connected with a +15V power supply through a capacitor C16, the upper end of a cooling liquid pump motor M1 is connected with an output-level reference ground end U5-Vs, the output-level reference ground end U5-Vs is connected with an output-level working power supply end U5-VB through a capacitor C17, and the output-level working power supply end U5-VB is connected with the +15V power supply through a diode D15; a driving pulse output end U5-HO of the motor driving module U5 is connected with a grid electrode of a motor driving IGBT through a current limiting resistor XLRn +2, a collector electrode of the motor driving IGBT is connected with the anode of a storage battery, and a cooling liquid pump motor M1 and a fan motor M2 are connected between an emitter electrode of the motor driving IGBT and the cathode of the storage battery in parallel; a motor unit freewheeling diode EJGn +2 is connected between the emitter of the motor drive IGBT and the cathode of the storage battery, and a resistor R30 and a capacitor C18 are connected between the two ends of a cooling liquid pump motor M1 in series.
The rated power of the cooling liquid pump motor M1 is about 120W, and the rated working current is 5A; the rated power of the fan motor M2 is about 72W, and the rated working current is 3A; the IGBTn +2 can be selected from NPN type IGBT tubes with rated working current of 80A.
After the automobile is started, a pulse width modulation signal output end of a CPU (Central processing Unit) -PWM (pulse width modulation) 5 outputs a 4/4 duty ratio signal, the current is limited by a current limiting resistor R27 and then is sent to an input end of an eighth optocoupler G8, when a pull-down resistor R28 ensures that the CPU-PWM5 outputs logic level '0', the level of the input end of the eighth optocoupler G8 is also logic '0', and a light-emitting diode ensures that the light-emitting diode can be reliably cut off; when the voltage of the control pulse input end U5-IN of the motor driving module U5 suddenly rises, the freewheeling diode D14 carries out freewheeling; the capacitor C16 is used as a voltage stabilizing capacitor, and the capacitor C17 and the diode D15 form a bootstrap circuit to generate VB voltage; the resistor R30 and the capacitor C18 form a third energy storage circuit. Through the isolation of the eighth optocoupler G8, a 4/4 duty ratio signal is sent to a control pulse input end U5-IN of a motor driving module U5, amplified by the motor driving module U5, and then output a 4/4 duty ratio signal through a driving pulse output end U5-HO to control IGBTn +2 to be switched on, so that a cooling liquid pump motor M1 and a fan motor M2 are started.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention. In addition to the above embodiments, the present invention may have other embodiments. All the technical solutions formed by adopting equivalent substitutions or equivalent transformations fall within the protection scope claimed by the present invention. The undescribed technical features of the present invention can be realized by or using the prior art, and are not described herein again.

Claims (8)

1. The utility model provides an eddy current retarder control system for car, includes CPU, its characterized in that: a first pulse width modulation signal output end (CPU-PWM1) of the CPU is connected with an input end of a sixth optical coupler (G6), an output end of the sixth optical coupler (G6) is connected with a control pulse input end (U3-IN) of a retarder driving module (U3), and driving pulse output ends (U3-HO) of the retarder driving module are respectively connected with grids of the excitation driving IGBTs; the collector of each excitation drive IGBT is connected with the positive electrode of the storage battery, and the excitation coil (LX) of the eddy current retarder is connected between the emitter of each excitation drive IGBT and the negative electrode of the storage battery; a plurality of excitation unit freewheeling diodes which are mutually connected in parallel are connected between the emitter of each excitation driving IGBT and the cathode of the storage battery.
2. The eddy current retarder control system for the automobile according to claim 1, wherein: the gear shifting handle of the eddy current retarder is provided with an automatic gear switch (K0), a first gear switch (K1), a second gear switch (K2), a third gear switch (K3) and a fourth gear switch (K4), the automatic gear switch (K0) is connected in series with the input end of a first optical coupler (G1), and the output end of the first optical coupler (G1) is connected with the PA0 port of a CPU; the one-gear switch (K1) is connected in series with the input end of the second optocoupler (G2), and the output end of the second optocoupler (G2) is connected with the PA1 port of the CPU; the second-order switch (K2) is connected in series with the input end of a third optical coupler (G3), and the output end of the third optical coupler (G3) is connected with the PA2 port of the CPU; the three-gear switch (K3) is connected in series with the input end of the fourth optocoupler (G4), and the output end of the fourth optocoupler (G4) is connected with the PA3 port of the CPU; the four-gear switch (K4) is connected in series with the input end of the fifth optocoupler (G5), and the output end of the fifth optocoupler (G5) is connected with the PA4 port of the CPU.
3. The eddy current retarder control system for the automobile according to claim 2, wherein: the positive electrode of the storage battery is sequentially connected with a thermistor (RM) and a diode D6 in series and then connected with a voltage input end I (U1-VIN) of a voltage reduction chip I (U1), a voltage sensitive resistor (YM) is connected between the thermistor (RM) and the negative electrode of the storage battery in series, and a freewheeling diode D7 and a capacitor C1 are connected between the voltage input end I (U1-VIN) of the voltage reduction chip I (U1) and the negative electrode of the storage battery in parallel; a first voltage output end (U1-SW) of the first voltage reduction chip (U1) is connected with a CPU-GND through a first sliding rheostat (HR1), a pin at the upper end of the first sliding rheostat (HR1) provides a +5V power supply for the CPU, and the middle end of the first sliding rheostat (HR1) is connected with a first feedback pin (U1-FB) of the first voltage reduction chip (U1); a voltage input end II (U2-VIN) of the voltage reduction chip II (U2) is connected with a voltage input end I (U1-VIN) of the voltage reduction chip I (U1) in parallel, a voltage output end II (U2-SW) of the voltage reduction chip II (U2) is connected with the cathode of the storage battery through a sliding rheostat II (HR2), the upper end of the sliding rheostat II (HR2) provides +15V power for each driving module, and the middle end of the sliding rheostat II (HR2) is connected with a feedback pin II (U2-FB) of the voltage reduction chip II (U2); the voltage reduction chip I (U1) and the voltage reduction chip II (U2) both adopt XL4016 modules, and the negative electrode of the storage battery is connected with the CPU-GND through an inductor L1.
4. The eddy current retarder control system for the automobile according to claim 1, wherein: a first pulse width modulation signal output end (CPU-PWM1) of the CPU is connected with an input anode of a sixth optocoupler (G6) through a current-limiting resistor R19, an input cathode of the sixth optocoupler (G6) is connected with the CPU-GND, and a pull-down resistor R20 is connected between the input anode and the input cathode of the sixth optocoupler (G6); the collector of the output end of a sixth optical coupler (G6) is connected with a +15V power supply, the emitter of the output end of the sixth optical coupler (G6) is connected with the control pulse input end (U3-IN) of a retarder driving module (U3), the control pulse input end (U3-IN) is connected with the cathode of a storage battery through a pull-down resistor R21, and the output end of the sixth optical coupler (G6) is connected with a freewheeling diode D10 IN parallel; the working power supply end (U3-Vcc) of a retarder driving module (U3) is connected with a +15V power supply, the input ground end (U3-COM) of the retarder driving module (U3) is connected with the cathode of a storage battery and is connected with the +15V power supply through a capacitor C10, the upper end of an eddy current retarder excitation coil (LX) is connected with an output stage reference ground end (U3-Vs), the output stage reference ground end (U3-Vs) is connected with the output stage working power supply end (U3-VB) through a capacitor C11, and the output stage working power supply end (U3-VB) is connected with the +15V power supply through a diode D11; two ends of an excitation coil (LX) of the eddy current retarder are connected in series with a resistor R22 and a capacitor C12.
5. The eddy current retarder control system for the automobile according to claim 1, wherein: a normally open contact of a relay (JD1) is connected between a collector and an emitter of each excitation drive IGBT, a coil of the relay (JD1) is connected between the anode and the cathode of the storage battery and is connected with a temperature control switch (WK) in series, and the temperature control switch (WK) is installed on a circuit board; a detection branch circuit is connected between a coil of the relay (JD1) and the temperature-controlled switch (WK), the detection branch circuit comprises a detection resistor R31 and a detection resistor R32 which are connected in series, the space between the detection resistor R31 and the detection resistor R32 is connected with a PAD1 port of the CPU, and the lower end of the detection resistor R32 is connected with the CPU-GND.
6. The eddy current retarder control system for the automobile according to claim 1, wherein: a third pulse width modulation signal output end (CPU-PWM3) of the CPU is connected with an input anode of a seventh optocoupler (G7) through a current-limiting resistor R23, an input cathode of the seventh optocoupler (G7) is connected with the CPU-GND, and a pull-down resistor R24 is connected between the input anode and the input cathode of the seventh optocoupler (G7); the collector of the output end of the seventh optocoupler (G7) is connected with a +15V power supply, the emitter of the output end of the seventh optocoupler (G7) is connected with the control pulse input end (U4-IN) of the brake lamp driving module (U4), the control pulse input end (U4-IN) is connected with the cathode of the storage battery through a pull-down resistor R25, and the output end of the seventh optocoupler (G7) is connected with a freewheeling diode D12 IN parallel; the working power supply end (U4-Vcc) of the brake lamp driving module (U4) is connected with a +15V power supply, the input ground end (U4-COM) of the brake lamp driving module (U4) is connected with the cathode of the storage battery and is connected with the +15V power supply through a capacitor C13, the upper end of the brake lamp (LP1) is connected with the output stage reference ground end (U4-Vs), the output stage reference ground end (U4-Vs) is connected with the output stage working power supply end (U4-VB) through a capacitor C14, and the output stage working power supply end (U4-VB) is connected with the +15V power supply through a diode D13; the driving pulse output end (U4-HO) of the brake lamp driving module (U4) is connected with the grid electrode of the brake lamp driving IGBTn +1 through a current limiting resistor XLRn +1, the collector electrode of the brake lamp driving IGBTn +1 is connected with the anode of the storage battery, and the brake lamp (LP1) is connected between the emitter electrode of the brake lamp driving IGBTn +1 and the cathode of the storage battery; a brake unit freewheeling diode EJGn +1 is connected between the emitting electrode of the brake lamp driving IGBTn +1 and the negative electrode of the storage battery, and a resistor R26 and a capacitor C15 are connected between the two ends of the brake lamp (LP1) in series.
7. The eddy current retarder control system for the automobile according to claim 1, wherein: a pulse width modulation signal output end five (CPU-PWM5) of the CPU is connected with an input anode of an eighth optocoupler (G8) through a current limiting resistor R27, an input cathode of the eighth optocoupler (G8) is connected with the CPU-GND, and a pull-down resistor R28 is connected between the input anode and the input cathode of the eighth optocoupler (G8); the collector of the output end of the eighth optocoupler (G8) is connected with a +15V power supply, the emitter of the output end of the eighth optocoupler (G8) is connected with a control pulse input end (U5-IN) of the motor driving module (U5), the control pulse input end (U5-IN) is connected with the cathode of the storage battery through a pull-down resistor R29, and the output end of the eighth optocoupler (G8) is connected with a freewheeling diode D14 IN parallel; the working power supply end (U5-Vcc) of the motor driving module (U5) is connected with a +15V power supply, the input ground end (U5-COM) of the motor driving module (U5) is connected with the cathode of the storage battery and is connected with the +15V power supply through a capacitor C16, the upper end of the cooling liquid pump motor (M1) is connected with the output stage reference ground end (U5-Vs), the output stage reference ground end (U5-Vs) is connected with the output stage working power supply end (U5-VB) through a capacitor C17, and the output stage working power supply end (U5-VB) is connected with the +15V power supply through a diode D15; a driving pulse output end (U5-HO) of the motor driving module (U5) is connected with a grid electrode of a motor driving IGBT through a current limiting resistor XLRn +2, a collector electrode of the motor driving IGBT is connected with the anode of a storage battery, and a cooling liquid pump motor (M1) and a fan motor (M2) are connected between an emitter electrode of the motor driving IGBT and the cathode of the storage battery in parallel; a motor unit freewheeling diode EJGn +2 is connected between the emitter of the motor drive IGBT and the cathode of the storage battery, and a resistor R30 and a capacitor C18 are connected between the two ends of a cooling liquid pump motor (M1) in series.
8. The eddy current retarder control system for the automobile according to claim 1, wherein: the speed signal output end of a speed sensor (S1) of a gearbox of an automobile is connected with the speed signal input end PJ6 of a CPU (Central processing Unit) through a current limiting resistor R16, a pull-up resistor R17 is connected in series between the speed signal input end PJ6 and a CPU +5V power supply, the grounding end of the speed sensor (S1) of the gearbox is connected with a CPU-GND (Central processing Unit-ground), and a capacitor C8 is arranged between the speed signal input end PJ6 of the CPU and the CPU-GND; a cooling liquid flow channel (1C) of a stator of the eddy current retarder is internally provided with a cooling liquid temperature sensor (T1), a temperature signal output end of the cooling liquid temperature sensor (T1) is connected with a temperature signal input end PAD0 of a CPU, a pull-up resistor R18 is connected between the temperature signal input end PAD0 and a CPU +5V power supply in series, a grounding end of the cooling liquid temperature sensor (T1) is connected with the negative electrode of a storage battery, and a capacitor C9 is arranged between the temperature signal input end PAD0 of the CPU and the negative electrode of the storage battery.
CN201921531147.8U 2019-09-16 2019-09-16 Electric eddy speed damper control system for automobile Active CN210526310U (en)

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