CN210517765U - NMOS transistor-based low-end drive output short-circuit protection circuit - Google Patents
NMOS transistor-based low-end drive output short-circuit protection circuit Download PDFInfo
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- CN210517765U CN210517765U CN201921251790.5U CN201921251790U CN210517765U CN 210517765 U CN210517765 U CN 210517765U CN 201921251790 U CN201921251790 U CN 201921251790U CN 210517765 U CN210517765 U CN 210517765U
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Abstract
The embodiment of the utility model relates to a low side drive output short-circuit protection circuit based on NMOS pipe, the control signal input end is connected to one end of first resistance R1, and the base of second triode T2 is connected to the other end; the emitter of the second triode T2 is grounded, and the collector of the second triode T2 is connected in series with the fifth sampling resistor R9 to the base of the first triode T1; the emitter of the first triode T1 is connected with the power supply, and the collector of the first triode T1 is connected with one end of the fourth sampling resistor R8; the other end of the fourth sampling resistor R8 is respectively connected with the grid of the NMOS transistor Q1 and the collector of the third triode T3; the emitter of the third triode T3 is grounded, and the base of the third triode T3 is connected in series with the second resistor R2 and the source of the NMOS tube Q1; the first sampling resistor R5 is connected in series between the source of the NMOS transistor Q1 and the ground; the drain electrode of the NMOS tube Q1 is connected with a load in series and is connected with a power supply, and the drain electrode of the NMOS tube Q1 is connected with a second sampling resistor R6 in series to an acquisition signal output end; the third sampling resistor R7 is connected in series between the collected signal output terminal and ground.
Description
Technical Field
The utility model relates to a circuit protection technical field especially relates to a low side drive output short-circuit protection circuit based on NMOS pipe.
Background
In a circuit using a field effect transistor (MOS) as a low-side switch, the MOS can avoid the burning phenomenon through short-circuit protection, but the cost is higher. And the protection circuit built by adopting the discrete elements has the advantages of complex circuit design, difficult debugging, no support for the control of high-speed Pulse Width Modulation (PWM) and low protection current precision. And when the drive output load is short-circuited, the drive circuit cannot be timely closed, so that the output drive is discontinuously started, and the MOS tube can be impacted by continuous large current to damage the circuit.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a low side drive output short-circuit protection circuit based on NMOS pipe, guaranteeing under the low-cost condition, simplifying the circuit, making the circuit easily debug to add the state monitoring and monitor the state of NMOS, close output control after monitoring to unusual, improve short-circuit protection circuit's reliability and switching frequency.
Therefore, the embodiment of the utility model provides a low side drive output short-circuit protection circuit based on NMOS pipe, low side drive output short-circuit protection circuit includes: the sampling circuit comprises a first resistor R1, a second resistor R2, a first sampling resistor R5, a second sampling resistor R6, a third sampling resistor R7, a fourth sampling resistor R8, a fifth sampling resistor R9, a first triode T1, a second triode T2, a third triode T3 and an NMOS tube Q1;
one end of the first resistor R1 is connected with a control signal input end, and the other end of the first resistor R1 is connected with the base electrode of the second triode T2; the emitter of the second triode T2 is grounded, and the collector of the second triode T2 is connected to one end of the fifth sampling resistor R9; the other end of the fifth sampling resistor R9 is connected with the base of the first triode T1; the emitter of the first triode T1 is connected with a power supply, and the collector of the first triode T1 is connected with one end of the fourth sampling resistor R8; the other end of the fourth sampling resistor R8 is respectively connected with the grid of the NMOS transistor Q1 and the collector of the third triode T3; the emitter of the third triode T3 is grounded, and the base of the third triode T3 is connected with one end of the second resistor R2; the other end of the second resistor R2 is connected with the source electrode of the NMOS transistor Q1; the first sampling resistor R5 is connected in series between the source of the NMOS transistor Q1 and the ground; the drain electrode of the NMOS tube Q1 is connected with a load in series and the drain electrode of the NMOS tube Q1 is connected with the second sampling resistor R6 in series to a collected signal output end; the third sampling resistor R7 is connected in series between the collected signal output end and the ground.
Preferably, the output short-circuit protection circuit further includes:
a third resistor R3 and a fourth resistor R4;
one end of the second resistor R2 is connected with one end of the third resistor R3, and the other end of the third resistor R3 is connected with the source electrode of the NMOS transistor Q1;
the other end of the second resistor R2 is also connected in series with the fourth resistor R4 and grounded.
Preferably, the output short-circuit protection circuit further comprises a zener diode D1;
the cathode of the zener diode D1 is connected to the collector of the third transistor T3, and the anode of the zener diode D1 is connected to ground.
Preferably, the first transistor T1 is a PNP transistor;
the second transistor T2 and the third transistor T3 are NPN transistors.
The embodiment of the utility model provides a low side drive output short-circuit protection circuit based on NMOS pipe, circuit structure is simple, easy debugging, and the protection current precision is high, supports high-speed PWM control simultaneously. The embodiment of the utility model provides an utilize the collection of NMOS pipe back-end current sampling resistance realization short circuit threshold value to set for to add the state detection and monitor the NMOS state, can close output control after monitoring to unusual, reach reliability, reduce cost, the purpose that improves short-circuit protection circuit, improve switching frequency.
Drawings
Fig. 1 is a circuit structure diagram of a low side driving output short circuit protection circuit based on an NMOS transistor according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and examples.
The embodiment of the utility model provides a low side drive output short-circuit protection circuit based on NMOS pipe, as shown in FIG. 1, low side drive output short-circuit protection circuit includes: the circuit comprises a first resistor R1, a second resistor R2, a first sampling resistor R5, a second sampling resistor R6, a third sampling resistor R7, a fourth sampling resistor R8, a fifth sampling resistor R9, a first triode T1, a second triode T2, a third triode T3 and an NMOS tube Q1.
One end of the first resistor R1 is connected to the control signal input terminal, and the effective control signal inputted from the control signal input terminal is used to make the acquisition signal output terminal of the low-side driving output short-circuit protection circuit output a stable low level. The other end of the first resistor R1 is connected with the base of a second triode T2; the first resistor R1 is used for limiting the current of the base electrode of the second triode T2, and the control signal end or the second triode T2 is prevented from being burnt during driving; the signal acquisition port can also adopt a PWM acquisition port or an AD acquisition port.
An emitter of the second triode T2 is grounded, and a collector of the second triode T2 is connected with one end of the fifth sampling resistor R9; the other end of the fifth sampling resistor R9 is connected with the base of the first triode T1; when the control signal is active, the collector of the second transistor T2 and the emitter of the second transistor T2 are connected to ground, and the base of the corresponding first transistor T1 is at low level; the fifth sampling resistor R9 is a current limiting resistor at the base of the first transistor T1, and prevents the first transistor T1 or the second transistor T2 from being burned out when the control signal is valid. In a specific circuit application, the first transistor T2 may not be limited to be implemented by a transistor, but may be replaced by another method such as a MOS transistor.
The emitter of the first triode T1 is connected with the power supply, and the collector of the first triode T1 is connected with one end of the fourth sampling resistor R8; the first transistor T1 is used to turn on the NMOS transistor Q1 by turning on the second transistor T2 and the first transistor T1 when the control signal is asserted, so that the gate of the NMOS transistor Q1 is set to the high level VBAT. In a specific circuit application, the first transistor T1 may not be limited to be implemented by a transistor, but may be replaced by another method such as a MOS transistor.
The other end of the fourth sampling resistor R8 is respectively connected with the grid of the NMOS tube Q1 and the collector of the third triode T3; the fourth sampling resistor R8 is used to provide current limiting for the gate of the NMOS transistor Q1, provide current limiting for the conduction of the zener diode D1, and provide current limiting for the collector and emitter of the third transistor T3 when the third transistor T3 is turned on.
The drain electrode of the NMOS tube Q1 is connected with a load in series and the drain electrode of the NMOS tube Q1 is connected with the second sampling resistor R6 in series to the acquisition signal output end; the NMOS tube Q1 is used for driving a switch circuit of a load;
the first sampling resistor R5 is connected in series between the source of the NMOS transistor Q1 and the ground; a threshold voltage value V can be preset and compared with a voltage value V generated when the voltage value V passes through the first sampling resistor R5R5Make a comparison once VR5>And V, indicating that the current short-circuit current is larger than a preset short-circuit current threshold value. The magnitude of the short-circuit current threshold can be adjusted by adjusting the resistance of the first sampling resistor R5.
The emitter of the third triode T3 is grounded, and the base of the third triode T3 is connected with one end of the second resistor R2; the other end of the second resistor R2 is connected with the source electrode of the NMOS transistor Q1; the second resistor R2 acts as a current limiting resistor at the base of the third transistor T3, providing operating current to the base of the third transistor T3.
In order to limit the gate voltage of the third transistor T3, a third resistor R3 and a fourth resistor R4 are connected behind the gate of T3 to form a voltage divider circuit. In a specific implementation, the voltage dividing circuit is composed of a third resistor R3 and a fourth resistor R4, one end of the second resistor R2 is connected with one end of the third resistor R3, and the other end of the third resistor R3 is connected with the source of the NMOS transistor Q1; the other end of the second resistor R2 is connected in series with the fourth resistor R4 and is grounded.
The voltage division circuit formed by the third resistor R3 and the fourth resistor R4 can realize the voltage division of VR5Voltage division acquisition is carried out, and the limitation of different short-circuit currents can be realized by adjusting the resistance values of the third resistor R3 and the fourth resistor R4; the voltage dividing circuit formed by the third resistor R3 and the fourth resistor R4 can be properly adjusted or even deleted according to the size of the first sampling resistor R5 and the size of the short-circuit current.
Under the condition that the short-circuit current passing through the first sampling resistor R5 exceeds a certain limit value, after the short-circuit current is divided by the third resistor R3 and the fourth resistor R4, the gate voltage of the third triode T3 exceeds the opening voltage of the T3, so that the third triode T3 is opened, the gate level of the NMOS tube Q1 is pulled down to the ground, and the purpose of closing the NMOS tube Q1 is achieved.
Preferably, the output short-circuit protection circuit may further include a zener diode D1; the negative electrode of the voltage-stabilizing diode D1 is connected with the collector electrode of the third triode T3, and the positive electrode of the voltage-stabilizing diode D1 is connected with the ground; the voltage stabilizing diode is used for protecting the grid electrode of the NMOS tube Q1, and when the power supply voltage is too high and the control signal is effective, the grid electrode voltage of the NMOS tube Q1 can be clamped to a safe voltage range; whether the voltage stabilizing diode D1 is used or not can be determined according to the withstand voltage value of the grid electrode of the NMOS tube Q1, and a voltage dividing resistor consisting of a proper resistor and the fourth sampling resistor R8 can be selected to replace the voltage stabilizing diode D1; for example, if the gate withstand voltage of the NMOS transistor Q1 is 20V and the turn-on threshold is 4V, the zener diode D1 may be 10V.
The drain of the NMOS transistor Q1 is also connected in series with a voltage divider circuit for collecting the output of the signal. The voltage division circuit specifically comprises a second sampling resistor R6 and a third sampling resistor R7.
The drain of the NMOS transistor Q1 is connected in series with the second sampling resistor R6 to the acquisition signal output end, and the third sampling resistor R7 is connected in series between the acquisition signal output end and the ground. The voltage of the drain electrode of the NMOS tube Q1 can be directly collected through a voltage division circuit consisting of the second sampling resistor R6 and the third sampling resistor R7 and output as a collected signal, so that the state of the NMOS tube Q1 can be judged through the collected signal, and the judgment of the load state is realized through judging the state of the NMOS tube Q1.
In the specific circuit of this embodiment, the first transistor T1 is a PNP transistor; the second transistor T2 and the third transistor T3 are NPN transistors.
The circuit structure of the present invention is explained above, and how the low side driving output protection circuit based on the NMOS transistor realizes the working principle of the output protection circuit is explained below.
When the control signal is in a low level state, the first triode T1, the second triode T2, the third triode T3 and the NMOS transistor Q1 are all in a closed state, and the acquisition signal end acquires a stable high level.
When the control signal is active at a high level, the collector and the emitter of the second triode T2 are connected to ground, the second triode T2 is turned on, the collector and the emitter of the second triode are turned on, the base of the first triode T1 is at a low level, the first triode T1 is also controlled to be turned on, the collector of the first triode T1 outputs a power supply voltage, the power supply voltage is limited by a fourth sampling resistor R8, the voltage of a voltage stabilizing diode D1 is stabilized and then acts on the gate of an NMOS transistor Q1, and the NMOS transistor Q1 is controlled to be turned on. The load current passes through a first sampling resistor R5 and to ground. The acquisition signal is acquired at a stable low level.
When the current output terminal (i.e., the drain of the NMOS transistor Q1) is shorted to the power supply, the drain current I of the NMOS transistor Q1 increases sharply. Because the utility model discloses third resistance R3 and fourth resistance R4 adopt kilo ohm level resistance in the circuit, and first sampling resistance R5 adopts milli ohm level resistance, so there is not the reposition of redundant personnel in NMOS pipe Q1's drain current I. Therefore, the current passing through the first sampling resistor R5 is I as well as the current of the NMOS transistor Q1. VR5R5 whenWhen I R5R 4/(R3+ R4) ═ 0.7V, the third transistor T3 is turned on, its emitter and collector are connected, i.e., the gate of the NMOS transistor Q1 is grounded, and the NMOS transistor Q1 is turned off. After the NMOS transistor Q1 is turned off, the short-circuit current decreases rapidly, and the third transistor T3 is also correspondingly turned off rapidly, and then the NMOS transistor Q1 is turned on again. In this way, in dynamic balance, the short-circuit current flowing through the NMOS transistor Q1 is always a periodic current from 0 to I, and the acquisition signal can acquire a PWM signal of a stable period, and at this time, it is determined that the power supply is short-circuited. When the power supply is judged to be short-circuited, the drive can be closed by controlling a control signal output to the circuit, so that the safety of the circuit is protected.
The utility model discloses an output protection circuit who uses the NMOS pipe to compare with current mode as the circuit of low side switch, the utility model discloses an output protection circuit who uses the NMOS pipe to realize still supporting fast-speed PWM control with the isolation of normal control logic as the circuit of low side switch, circuit design is simple, does not need anti-logic. The acquisition setting of the short-circuit threshold is realized by using the current sampling resistor at the back stage of the MOS, the state detection is added to monitor the state of the NMOS tube, and once the abnormal state is monitored, the control signal is closed, so that the reliability of the protection circuit is improved, the cost is reduced, and the switching frequency is improved.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (4)
1. A low-side driving output short-circuit protection circuit based on an NMOS tube is characterized by comprising: the sampling circuit comprises a first resistor R1, a second resistor R2, a first sampling resistor R5, a second sampling resistor R6, a third sampling resistor R7, a fourth sampling resistor R8, a fifth sampling resistor R9, a first triode T1, a second triode T2, a third triode T3 and an NMOS tube Q1;
one end of the first resistor R1 is connected with a control signal input end, and the other end of the first resistor R1 is connected with the base electrode of the second triode T2; the emitter of the second triode T2 is grounded, and the collector of the second triode T2 is connected to one end of the fifth sampling resistor R9; the other end of the fifth sampling resistor R9 is connected with the base of the first triode T1; the emitter of the first triode T1 is connected with a power supply, and the collector of the first triode T1 is connected with one end of the fourth sampling resistor R8; the other end of the fourth sampling resistor R8 is respectively connected with the grid of the NMOS transistor Q1 and the collector of the third triode T3; the emitter of the third triode T3 is grounded, and the base of the third triode T3 is connected with one end of the second resistor R2; the other end of the second resistor R2 is connected with the source electrode of the NMOS transistor Q1; the first sampling resistor R5 is connected in series between the source of the NMOS transistor Q1 and the ground; the drain electrode of the NMOS tube Q1 is connected with a load in series and the drain electrode of the NMOS tube Q1 is connected with the second sampling resistor R6 in series to a collected signal output end; the third sampling resistor R7 is connected in series between the collected signal output end and the ground.
2. The low side drive output short circuit protection circuit of claim 1, further comprising: a third resistor R3 and a fourth resistor R4;
one end of the second resistor R2 is connected with one end of the third resistor R3, and the other end of the third resistor R3 is connected with the source electrode of the NMOS transistor Q1;
the other end of the second resistor R2 is also connected in series with the fourth resistor R4 and grounded.
3. The low side driven output short circuit protection circuit according to claim 1, further comprising a zener diode D1;
the cathode of the zener diode D1 is connected to the collector of the third transistor T3, and the anode of the zener diode D1 is connected to ground.
4. The low side driver output short circuit protection circuit according to claim 1, wherein the first transistor T1 is a PNP transistor; the second transistor T2 and the third transistor T3 are NPN transistors.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921251790.5U CN210517765U (en) | 2019-08-02 | 2019-08-02 | NMOS transistor-based low-end drive output short-circuit protection circuit |
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| CN201921251790.5U CN210517765U (en) | 2019-08-02 | 2019-08-02 | NMOS transistor-based low-end drive output short-circuit protection circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112019003A (en) * | 2020-08-18 | 2020-12-01 | 重庆智行者信息科技有限公司 | Load driving circuit with full diagnosis function built by discrete components |
| CN113067563A (en) * | 2021-03-15 | 2021-07-02 | 重庆智行者信息科技有限公司 | PWM signal output and diagnostic circuit |
-
2019
- 2019-08-02 CN CN201921251790.5U patent/CN210517765U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112019003A (en) * | 2020-08-18 | 2020-12-01 | 重庆智行者信息科技有限公司 | Load driving circuit with full diagnosis function built by discrete components |
| WO2022037482A1 (en) * | 2020-08-18 | 2022-02-24 | 重庆兰德适普信息科技有限公司 | Load driving circuit having full-diagnosis function and built by using discrete element |
| CN113067563A (en) * | 2021-03-15 | 2021-07-02 | 重庆智行者信息科技有限公司 | PWM signal output and diagnostic circuit |
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Address after: B4-006, maker Plaza, 338 East Street, Huilongguan town, Changping District, Beijing 100096 Patentee after: Beijing Idriverplus Technology Co.,Ltd. Address before: B4-006, maker Plaza, 338 East Street, Huilongguan town, Changping District, Beijing 100096 Patentee before: Beijing Idriverplus Technology Co.,Ltd. |