CN210515262U - Digital processing acquisition card based on programmable chip - Google Patents
Digital processing acquisition card based on programmable chip Download PDFInfo
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- CN210515262U CN210515262U CN201922077686.5U CN201922077686U CN210515262U CN 210515262 U CN210515262 U CN 210515262U CN 201922077686 U CN201922077686 U CN 201922077686U CN 210515262 U CN210515262 U CN 210515262U
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Abstract
The utility model relates to computer information processing field especially relates to a digital processing collection card based on chip able to programme, including collection signal channel, power amplifier circuit, the state switch circuit of connecting the collection signal port, be used for programmable control's chip able to programme, converter, collection signal channel, power amplifier circuit, state switch circuit, chip able to programme electric connection in proper order, chip able to programme is connected with the converter electricity, converter be connected with the power amplifier circuit electricity. After receiving input acquisition signals through the two data acquisition signal channels, the switching selection output of the input signals can be realized through the control of the programmable chip, thereby enriching and enhancing the functions of the existing digital processing acquisition card; the utility model discloses can also adjust signal acquisition's passageway quantity in a flexible way and can switch on through programming chip control selectivity.
Description
Technical Field
The utility model relates to a computer information processing field, in particular to digital processing acquisition card based on chip able to programme.
Background
The digital processing acquisition card mainly refers to an acquisition device which captures external analog signals such as photoelectricity, video and audio and digitally guides the analog signals into a computer for digital processing, and mainly uses an image acquisition card, a video acquisition card, an audio acquisition card (such as a sound card), a data acquisition card and the like. Is a device that can acquire, quantize, and encode analog video signals. The digital processing acquisition card in the prior art has a single function, and lacks a technology or a technical scheme which can acquire multiple paths of signals and is convenient for controlling switching output on hardware.
SUMMERY OF THE UTILITY MODEL
The utility model discloses an above-mentioned technical problem is solved through following technical scheme:
the digital processing acquisition card based on the programmable chip comprises an acquisition signal channel, a power amplifier circuit, a state switch circuit, a programmable chip and a current transformer, wherein the acquisition signal channel, the power amplifier circuit, the state switch circuit and the programmable chip are connected with an acquisition signal port, the programmable chip is used for programmable control, the programmable chip is electrically connected with the current transformer, and the current transformer is electrically connected with the power amplifier circuit.
Furthermore, the state switch circuit adopts an 8-pin integrated circuit switch, the signal acquisition channel comprises two signal acquisition channels, the power amplifier circuit comprises two power amplifier circuits, and the signal acquisition channels are divided into a positive electrode and a negative electrode.
Furthermore, the positive electrode of the first acquisition signal channel is connected with the 1 st coupling piece and the 1 st voltage regulating piece, the other ends of the 1 st coupling piece and the 1 st voltage regulating piece are grounded, the negative electrode of the first acquisition signal channel is connected with the 2 nd coupling piece and the 1 st rectifying piece, the other end of the 1 st rectifying piece is connected with the 2 nd voltage regulating piece, the other end of the 2 nd voltage regulating piece is connected with a direct current power supply, the other end of the 2 nd coupling piece is connected with the 3 rd coupling piece and the input end of a first power amplification circuit, the other end of the 3 rd coupling piece is connected with the 3 rd voltage regulating piece, the grounding pin of the first power amplification circuit is grounded, the output end of the first power amplification circuit is connected with the other end of the 3 rd voltage regulating piece, the 2 nd rectifying piece and the 5 th coupling piece, the other end of the 2 nd rectifying piece is connected with the emitter and the 4 th coupling piece; the positive pole of the second signal acquisition channel is connected with the 7 th coupling piece and the 4 th voltage regulating piece, the other ends of the 7 th coupling piece and the 4 th voltage regulating piece are grounded, the negative pole of the second signal acquisition channel is connected with the 4 th rectifying piece and the 8 th coupling piece, the other end of the 4 th rectifying piece is connected with the 5 th voltage regulating piece, the other end of the 5 th voltage regulating piece is connected with a direct current power supply, the other end of the 8 th coupling piece is connected with the 9 th coupling piece and the input end of a second power amplification circuit, the other end of the 9 th coupling piece is connected with the 6 th voltage regulating piece, the grounding pin of the second power amplification circuit is grounded, the output end of the second power amplification circuit is connected with the other end of the 6 th voltage regulating piece, the 3 rd rectifying piece and the 10 th coupling piece, the other end of the 3 rd rectifying piece is connected with the emitter of the 1 st current.
Further, the coupling piece adopts a capacitance element, the voltage regulating piece adopts a resistance element, the rectifying piece adopts an inductance element, and the current transforming piece adopts a triode.
Further, a 3 rd pin of the programmable chip is connected with a 14 th coupling element and a clock circuit, the other end of the 14 th coupling element is grounded, the other end of the clock circuit is connected with a 15 th coupling element and a 4 th pin of the programmable chip, the other end of the 15 th coupling element is grounded, a 12 th pin of the programmable chip is grounded, a 26 th pin of the programmable chip is connected with an 8 th voltage regulating element, a base of a 1 st current transformer and a 10 th voltage regulating element, the other end of the 8 th voltage regulating element is connected with a direct current voltage, a collector of the 1 st current transformer is connected with the direct current voltage, the other end of the 10 th voltage regulating element is connected with a base of a 3 rd current transformer, an emitter of the 3 rd current transformer is grounded, a collector of the 3 rd current transformer is connected with a 9 th voltage regulating element and a base of a 2 nd current transformer, the other end of the 9 th voltage regulating element is connected with the direct current voltage, a collector of the 2 nd current transformer, the 31 th pin of the programmable chip is connected with the 7 th voltage regulating piece and the negative electrode of the electrolytic 12 th coupling piece, the other end of the 7 th voltage regulating piece is connected with the 13 th coupling piece and grounded, and the positive electrode of the electrolytic 12 th coupling piece is connected with direct current voltage and the other end of the 13 th coupling piece; the 1 st pin of the state switch circuit is connected with direct current voltage, the 4 th pin of the state switch circuit is connected with the 6 th coupling piece, and the other end of the 6 th coupling piece outputs a switched signal.
Furthermore, the programmable chip adopts a singlechip.
Advantageous effects
The utility model can realize the switching and selective output of the input signals through the control of the programmable chip after the two data acquisition signal channels receive the input acquisition signals, thereby enriching and enhancing the functions of the existing digital processing acquisition card; the utility model discloses can also adjust signal acquisition's passageway quantity in a flexible way and can switch on through programming chip control selectivity.
Drawings
Fig. 1 is a circuit connection block diagram of the present invention.
Fig. 2 is a schematic diagram of a part of the circuit connection of the present invention, and is specifically a schematic diagram of the connection of the programmable chip and the status switch circuit and the coupling/connection of the status switch circuit and the signal input/output terminal.
Fig. 3 is a schematic diagram of a part of the circuit connection of the present invention, and in particular, a schematic diagram of the programmable chip connected to the converter to control the input/output.
Detailed Description
Digital processing collecting card based on programmable chip, as figure 1, the utility model discloses a connect collection signal port's collection signal channel, power amplifier circuit, state switch circuit, be used for programmable control's programmable chip, converter, collection signal channel, power amplifier circuit, state switch circuit, programmable chip be electric connection in proper order, programmable chip is connected with the converter electricity, converter and power amplifier circuit electricity be connected.
As shown in fig. 2, the state switch circuit E adopts an 8-pin integrated circuit switch, the signal acquisition channel includes two signal acquisition channels, the power amplifier circuit includes two power amplifier circuits, and the signal acquisition channels are divided into a positive electrode and a negative electrode.
As shown in fig. 2-3, the positive pole of the first collecting signal channel a is connected with the 1 st coupling element and the 1 st voltage regulating element, the other ends of the 1 st coupling element and the 1 st voltage regulating element are grounded, the negative pole of the first collecting signal channel a is connected with the 2 nd coupling element and the 1 st rectifying element, the other end of the 1 st rectifying element is connected with the 2 nd voltage regulating element, the other end of the 2 nd voltage regulating element is connected with the direct current power supply, the other end of the 2 nd coupling element is connected with the 3 rd coupling element, the input end of a first power amplifier circuit C, the other end of a 3 rd coupling piece is connected with a 3 rd voltage regulating piece, the grounding pin of the first power amplifier circuit C is grounded, the output end of the first power amplifier circuit C is connected with the other end of the 3 rd voltage regulating piece, a 2 nd rectifying piece and a 5 th coupling piece, the other end of the 2 nd rectifying piece is connected with an emitter of a 2 nd converting piece G and the 4 th coupling piece, the other end of the 4 th coupling piece is grounded, and the other end of the 5 th coupling piece is connected with the 5 th pin of a state switching circuit; the positive pole of the second signal collecting channel B is connected with the 7 th coupling piece and the 4 th voltage regulating piece, the other ends of the 7 th coupling piece and the 4 th voltage regulating piece are grounded, the negative pole of the second signal collecting channel B is connected with the 4 th rectifying piece and the 8 th coupling piece, the other end of the 4 th rectifying piece is connected with the 5 th voltage regulating piece, the other end of the 5 th voltage regulating piece is connected with a direct current power supply, the other end of the 8 th coupling piece is connected with the 9 th coupling piece and the input end of a second power amplifier circuit D, the other end of the 9 th coupling piece is connected with the 6 th voltage regulating piece, the grounding pin of the second power amplifier circuit D is grounded, the output end of the second power amplifier circuit D is connected with the other end of the 6 th voltage regulating piece, the 3 rd rectifying piece and the 10 th coupling piece, the other end of the 3 rd rectifying piece is connected with the emitter of the 1 st current converting.
The coupling piece adopts a capacitance element, the voltage regulating piece adopts a resistance element, the rectifying piece adopts an inductance element, and the current transforming piece G adopts a triode.
As shown in fig. 3, the 3 rd pin of the programmable chip F is connected to the 14 th coupling element and the clock circuit, the other end of the 14 th coupling element is connected to the ground, the other end of the clock circuit is connected to the 15 th coupling element and the 4 th pin of the programmable chip F, the other end of the 15 th coupling element is connected to the ground, the 12 th pin of the programmable chip F is connected to the ground, the 26 th pin of the programmable chip F is connected to the 8 th voltage regulator, the base of the 1 st current transformer G and the 10 th voltage regulator, the other end of the 8 th voltage regulator is connected to the dc voltage, the collector of the 1 st current transformer G is connected to the dc voltage, the other end of the 10 th voltage regulator is connected to the base of the 3 rd current transformer G, the emitter of the 3 rd current transformer G is connected to the ground, the collector of the 3 rd current transformer G is connected to the 9 th voltage regulator and the base of the 2 nd current transformer G, the collector of the 2 nd current transformer G is, the pin 28 of the programmable chip F is connected with direct-current voltage, the pin 31 of the programmable chip F is connected with a 7 th voltage regulating piece and electrically connected with the negative electrode of a 12 th coupling piece, the other end of the 7 th voltage regulating piece is connected with a 13 th coupling piece and grounded, the positive electrode of the 12 th coupling piece is connected with the direct-current voltage, and the other end of the 13 th coupling piece is electrolyzed; the 1 st pin of the state switch circuit E is connected with direct-current voltage, the 4 th pin of the state switch circuit E is connected with the 6 th coupling piece, and the other end of the 6 th coupling piece outputs a switched signal; the programmable chip F adopts a singlechip.
In implementation, after the first or second acquisition signal channel receives an input acquisition signal, the first or second power amplification circuit receives the signal, amplifies the signal and inputs the amplified signal to the 5 th or 8 th pin input pin of the state switch circuit; when the 27 th pin of the programmable chip outputs high level, the state switch circuit is switched to the 8 th pin, the 8 th pin and the 4 th pin are communicated, and a signal input into the 8 th pin is output through the 4 th pin; and the 27 th pin of the programmable chip outputs low level, the state switch circuit is switched to the 5 th pin to communicate the 5 th pin and the 4 th pin, and the signal input into the 5 th pin is output through the 4 th pin. When the 26 th pin of the programmable chip outputs high level, the 1 st converter is switched on, the second power amplifier circuit is powered through the current collecting electrode of the 1 st converter, the second power amplifier circuit works normally, the 3 rd converter is switched on, the current collecting electrode of the 3 rd converter is at low level, the 2 nd converter is switched off, the power supply to the first power amplifier circuit is stopped, and the first power amplifier circuit stops working. When the 26 th pin of the programmable chip outputs low level, the 1 st converter is cut off, the power supply to the second power amplifier circuit is stopped, the second power amplifier circuit stops working, the 3 rd converter is cut off, the collector of the 3 rd converter has high level, the 2 nd converter is conducted, the power supply to the first power amplifier circuit is carried out through the emitter of the 2 nd converter, and the first power amplifier circuit normally works; in implementation, after receiving an input acquisition signal through the first or second acquisition signal channel, switching and selective output of the input signal can be finally realized through the control of the programmable chip, so that the functions of the existing digital processing acquisition card are enriched and enhanced; in the concrete implementation of course, foretell two collection signal channel can also be expanded more, so the utility model discloses can adjust signal acquisition's passageway quantity in a flexible way and can switch on through programming chip control selectivity.
Claims (6)
1. The digital processing acquisition card based on the programmable chip is characterized by comprising an acquisition signal channel, a power amplifier circuit, a state switch circuit, a programmable chip and a current transformer, wherein the acquisition signal channel, the power amplifier circuit, the state switch circuit and the programmable chip are connected with an acquisition signal port, the programmable chip and the current transformer are electrically connected in sequence, and the current transformer is electrically connected with the power amplifier circuit.
2. The programmable chip-based digital processing acquisition card according to claim 1, wherein the state switch circuit is an 8-pin integrated circuit switch, the acquisition signal path comprises two acquisition signal paths, the power amplifier circuit comprises two power amplifier circuits, and the acquisition signal paths are divided into a positive electrode and a negative electrode.
3. The programmable chip-based digital processing acquisition card according to claim 2, wherein the positive terminal of the first acquisition signal channel is connected to the 1 st coupling element and the 1 st voltage-regulating element, the other terminals of the 1 st coupling element and the 1 st voltage-regulating element are grounded, the negative terminal of the first acquisition signal channel is connected to the 2 nd coupling element and the 1 st rectifying element, the other terminal of the 1 st rectifying element is connected to the 2 nd voltage-regulating element, the other terminal of the 2 nd voltage-regulating element is connected to the DC power supply, the other terminal of the 2 nd coupling element is connected to the 3 rd coupling element and the input terminal of the first power amplifier circuit, the other terminal of the 3 rd coupling element is connected to the 3 rd voltage-regulating element, the ground pin of the first power amplifier circuit is grounded, the output terminal of the first power amplifier circuit is connected to the other terminal of the 3 rd voltage-regulating element, the 2 nd rectifying element and the 5 th coupling element, the other terminal, the other end of the 5 th coupling piece is connected with a 5 th pin of the state switch circuit; the positive pole of the second signal acquisition channel is connected with the 7 th coupling piece and the 4 th voltage regulating piece, the other ends of the 7 th coupling piece and the 4 th voltage regulating piece are grounded, the negative pole of the second signal acquisition channel is connected with the 4 th rectifying piece and the 8 th coupling piece, the other end of the 4 th rectifying piece is connected with the 5 th voltage regulating piece, the other end of the 5 th voltage regulating piece is connected with a direct current power supply, the other end of the 8 th coupling piece is connected with the 9 th coupling piece and the input end of a second power amplification circuit, the other end of the 9 th coupling piece is connected with the 6 th voltage regulating piece, the grounding pin of the second power amplification circuit is grounded, the output end of the second power amplification circuit is connected with the other end of the 6 th voltage regulating piece, the 3 rd rectifying piece and the 10 th coupling piece, the other end of the 3 rd rectifying piece is connected with the emitter of the 1 st current.
4. The programmable chip-based digital processing acquisition card according to claim 3, wherein said coupling element is a capacitive element, said voltage regulator is a resistive element, said rectifier is an inductive element, and said current transformer is a triode.
5. The programmable chip-based digital processing acquisition card according to claim 4, wherein the programmable chip has pin 3 connected to the 14 th coupling element and the clock circuit, the other end of the 14 th coupling element is connected to ground, the other end of the clock circuit is connected to the 15 th coupling element and the 4 th pin of the programmable chip, the other end of the 15 th coupling element is connected to ground, the 12 th pin of the programmable chip is connected to ground, the 26 th pin of the programmable chip is connected to the 8 th voltage regulator, the base of the 1 st current transformer and the 10 th voltage regulator, the other end of the 8 th voltage regulator is connected to DC voltage, the collector of the 1 st current transformer is connected to DC voltage, the other end of the 10 th voltage regulator is connected to the base of the 3 rd current transformer, the emitter of the 3 rd current transformer is connected to ground, the collector of the 3 rd current transformer is connected to the base of the 9 th voltage regulator and the 2 nd current transformer, the collector of the 2 nd current transformer, the 27 th pin of the programmable chip is connected with the 2 nd pin of the state switching circuit, the 28 th pin of the programmable chip is connected with direct current voltage, the 31 th pin of the programmable chip is connected with the 7 th voltage-regulating piece and the negative electrode of the electrolytic 12 th coupling piece, the other end of the 7 th voltage-regulating piece is connected with the 13 th coupling piece and grounded, and the positive electrode of the electrolytic 12 th coupling piece is connected with the direct current voltage and the other end of the 13 th coupling piece; the 1 st pin of the state switch circuit is connected with direct current voltage, the 4 th pin of the state switch circuit is connected with the 6 th coupling piece, and the other end of the 6 th coupling piece outputs a switched signal.
6. The digital processing acquisition card based on programmable chip according to claim 1 or 5, wherein said programmable chip is a single chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922077686.5U CN210515262U (en) | 2019-11-27 | 2019-11-27 | Digital processing acquisition card based on programmable chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922077686.5U CN210515262U (en) | 2019-11-27 | 2019-11-27 | Digital processing acquisition card based on programmable chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210515262U true CN210515262U (en) | 2020-05-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922077686.5U Active CN210515262U (en) | 2019-11-27 | 2019-11-27 | Digital processing acquisition card based on programmable chip |
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|---|---|
| CN (1) | CN210515262U (en) |
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- 2019-11-27 CN CN201922077686.5U patent/CN210515262U/en active Active
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