Switching circuit for subway equipment
Technical Field
The utility model relates to a communication system's on & off circuit, in particular to a switch circuit for subway equipment.
Background
In the modern society with more and more congestion ground traffic, subway construction is rising in various large and medium-sized cities, and urban rail traffic construction in China is rapid. At present, 28 cities in the whole country have urban rail transit operation or are under construction, wherein 12 cities have urban rail transit operation lines, and the mileage of the operation lines in the last twelve and five cities is estimated to reach 3000 kilometers in 28 cities. The subway control equipment uses high voltage power supply, uses the key switch to control all equipment, and unified confession, outage.
At present, mechanical switches such as a ship-shaped switch or a button switch are used for connecting a general subway device with a power supply, and the on-off operation needs to be realized by manually shifting the mechanical switches. If the equipment program is suddenly powered off in the running process, the subway equipment can not be started easily.
Disclosure of Invention
For the development that adapts to prior art, the utility model provides a switch circuit for subway equipment. The soft key shutdown function of the subway equipment is designed, so that when the single chip microcomputer detects that the key is pressed down, the main CPU control circuit is informed to shut down the application program, and then the down-counting shutdown is carried out, and the problem caused by sudden power failure in the running process of the equipment program is effectively avoided. The utility model discloses realize soft button controlgear switching on and shutting down to the on & off state that can the recording equipment.
The utility model discloses a realize that the technical scheme that above-mentioned purpose was taken is: a switch circuit for subway equipment, characterized in that: the key is connected with the power supply control circuit, the power supply control circuit is connected with the power supply circuit, the power supply circuit is in bidirectional connection with the single chip microcomputer circuit, the power supply control circuit is in bidirectional connection with the single chip microcomputer circuit, and the single chip microcomputer circuit is in bidirectional connection with the main CPU control circuit.
The single chip circuit of the utility model adopts ATmega8L chip N1, the power control circuit adopts UMX1N chip N2, the power supply circuit adopts 78M05 voltage stabilizer N3, LM1117-3.3 three-terminal linear voltage stabilizer N4; the 1 end of the key XS1 is connected with one end of the capacitor C2 and then grounded, and the 2 end of the key XS1 is connected with one end of the resistor R4 and then connected to the POWER-on/off key detection POWER _ TEST end; the other end of the resistor R4 is connected with one end of a resistor R3 and a pin G of an MOS transistor VT1, the other end of the resistor R3 is connected with a pin S of an MOS transistor VT1 and then is connected with an external 13.8V direct-current power supply, a pin D of the MOS transistor VT1 outputs VDD13.8V power supply, meanwhile, the pin G of the MOS transistor VT1 is connected with the other end of the capacitor C2 and one end of a resistor R5, and the other end of the resistor R5 is connected with a pin 6 of a chip N2; a pin 5 of the chip N2 is connected with one end of a resistor R6 and one end of a resistor R9, the other end of the resistor R6 is connected to a pin 1 of the chip N1, the other end of the resistor R9 is grounded, a pin 4 of the chip N2 is grounded, a pin 1 of the chip N2 is connected with one end of the resistor R8 and then grounded, the other end of the resistor R8 is connected with a pin 2 of the chip N2 and one end of a resistor R7, and the other end of the resistor R7 is connected to a pin 2 of the chip N1; the 3 pins of the chip N2 are connected with a POW _ ALL pin of a main CPU control circuit CPU, a VDD3V3_ MCU supplies power for the main CPU control circuit, and meanwhile, a CPU detection pin of the main CPU control circuit is connected to the 9 pins of the chip N1; the pin 3 and the pin 5 of the chip N1 are connected, then the chip N1 is connected with one end of a capacitor C3 and one end of a capacitor C4, the chip N3 and the capacitor C4 are grounded after being connected, the other end of the capacitor C3 and the other end of the capacitor C4 are connected with the pin 4 and the pin 6 of the chip N1, and the chip N3538 and the pin 6 are connected with VDD3V3_ MCU after being connected; a pin 15 of the chip N1 is connected with a pin 5 of the socket XS2, a pin 16 is connected with a pin 4 of the socket XS2, a pin 17 is connected with a pin 3 of the socket XS2, a pin 29 is connected with one end of the capacitor C1 and one end of the resistor R2, a pin 1 of the rear socket XS2 is connected, and a pin 6 of the socket XS2 is grounded; the 21 pin of the chip N1 is grounded, the 18 pin is connected with one end of a capacitor C5 and one end of a capacitor C6 and is connected with the 2 pin of a rear patch socket XS2, the other end of the capacitor C1 is grounded, the other end of a resistor R2 is connected with a VDD3V3_ MCU, and the other end of the capacitor C5 is connected with the other end of the capacitor C6 and then is grounded; the anode of the diode VD1 is connected with the 32 pin of the chip N1 and one end of the resistor R1, and the cathode of the diode VD1 is connected with the POWER-on/off key detection POWER _ TEST end; the other end of the resistor R1 is connected with VDD3V3_ MCU.
The utility model discloses a power supply circuit stabiliser N3's 1 foot connects the one end of electric capacity C7, connects VDD13.8V after connecting, and the other end of electric capacity C7 grounds; a pin 2 of the voltage stabilizer N3 is grounded, a pin 3 is connected with one end of the capacitor C8, and the other end of the capacitor C8 is grounded; meanwhile, a pin 3 of the voltage stabilizer N3 is connected with a pin 3 of the three-terminal linear voltage stabilizer N4, a pin 1 of the terminal linear voltage stabilizer N4 is grounded, and a pin 2 is connected with one end of the capacitor C9 and outputs VDD3V3_ MCU after connection.
The utility model has the advantages that: the subway equipment uses the mechanical switching scheme at present, uses the long press switch button to realize the switch-on and switch-off, can effectually avoid the equipment in operation to fall the unable trouble that starts of power failure suddenly in subway equipment.
Drawings
FIG. 1 is a block diagram of the circuit connection of the present invention;
fig. 2 is a schematic circuit diagram of the present invention.
Detailed Description
The present invention will be further explained with reference to the accompanying drawings.
As shown in fig. 1 and 2, the switch circuit for the subway equipment comprises a single chip microcomputer circuit, a power supply control circuit, a power supply circuit, a main CPU control circuit and a key, wherein the key is connected with the power supply control circuit, the power supply control circuit is connected with the power supply circuit, the power supply circuit is bidirectionally connected with the single chip microcomputer circuit, the power supply control circuit is bidirectionally connected with the single chip microcomputer circuit, and the single chip microcomputer circuit is bidirectionally connected with the main CPU control circuit.
The single chip microcomputer circuit of the design adopts an ATmega8L chip N1, the power supply control circuit adopts a UMX1N chip N2, and the power supply circuit adopts a 78M05 voltage stabilizer N3 and an LM1117-3.3 three-terminal linear voltage stabilizer N4; the 1 end of the key XS1 is connected with one end of the capacitor C2 and then grounded, and the 2 end of the key XS1 is connected with one end of the resistor R4 and then connected to the POWER-on/off key detection POWER _ TEST end; the other end of the resistor R4 is connected with one end of a resistor R3 and a pin G of an MOS tube VT1 (MTD 20P06 HDL), the other end of the resistor R3 is connected with a pin S of the MOS tube VT1 and then is connected with an external 13.8V direct-current power supply, the pin D of the MOS tube VT1 outputs VDD13.8V power supply, meanwhile, the pin G of the MOS tube VT1 is connected with the other end of the capacitor C2 and one end of the resistor R5, and the other end of the resistor R5 is connected with a pin 6 of the chip N2; a pin 5 of the chip N2 is connected with one end of a resistor R6 and one end of a resistor R9, the other end of the resistor R6 is connected to a pin 1 of the chip N1, the other end of the resistor R9 is grounded, a pin 4 of the chip N2 is grounded, a pin 1 of the chip N2 is connected with one end of the resistor R8 and then grounded, the other end of the resistor R8 is connected with a pin 2 of the chip N2 and one end of a resistor R7, and the other end of the resistor R7 is connected to a pin 2 of the chip N1; the 3 pins of the chip N2 are connected with a POW _ ALL pin of a main CPU control circuit CPU, a VDD3V3_ MCU supplies power for the main CPU control circuit, and meanwhile, a CPU detection pin of the main CPU control circuit is connected to the 9 pins of the chip N1; the pin 3 and the pin 5 of the chip N1 are connected, then the chip N1 is connected with one end of a capacitor C3 and one end of a capacitor C4, the chip N3 and the capacitor C4 are grounded after being connected, the other end of the capacitor C3 and the other end of the capacitor C4 are connected with the pin 4 and the pin 6 of the chip N1, and the chip N3538 and the pin 6 are connected with VDD3V3_ MCU after being connected; a pin 15 of the chip N1 is connected with a pin 5 of the socket XS2, a pin 16 is connected with a pin 4 of the socket XS2, a pin 17 is connected with a pin 3 of the socket XS2, a pin 29 is connected with one end of the capacitor C1 and one end of the resistor R2, a pin 1 of the rear socket XS2 is connected, and a pin 6 of the socket XS2 is grounded; the 21 pin of the chip N1 is grounded, the 18 pin is connected with one end of a capacitor C5 and one end of a capacitor C6 and is connected with the 2 pin of a rear patch socket XS2, the other end of the capacitor C1 is grounded, the other end of a resistor R2 is connected with a VDD3V3_ MCU, and the other end of the capacitor C5 is connected with the other end of the capacitor C6 and then is grounded; the anode of the diode VD1 is connected with the 32 pin of the chip N1 and one end of the resistor R1, and the cathode of the diode VD1 is connected with the POWER-on/off key detection POWER _ TEST end; the other end of the resistor R1 is connected with VDD3V3_ MCU.
A pin 1 of a voltage stabilizer N3 of the power supply circuit is connected with one end of a capacitor C7, the connection is connected with VDD13.8V, and the other end of the capacitor C7 is grounded; a pin 2 of the voltage stabilizer N3 is grounded, a pin 3 is connected with one end of the capacitor C8, and the other end of the capacitor C8 is grounded; meanwhile, a pin 3 of the voltage stabilizer N3 is connected with a pin 3 of the three-terminal linear voltage stabilizer N4, a pin 1 of the terminal linear voltage stabilizer N4 is grounded, and a pin 2 is connected with one end of the capacitor C9 and outputs VDD3V3_ MCU after connection.
As shown in fig. 2, the working principle of the present invention is as follows: when a 13.8V direct-current POWER supply is input from the outside of the switch circuit, when a key XS1 is pressed, VDD13.8V starts to supply POWER, a VDD3V3_ MCU of 78M05 voltage stabilizer N3 and LM1117-3.3 three-terminal linear voltage stabilizer N4 works is effective, a main CPU control circuit (the main CPU circuit is a common single-chip microcomputer system, only 'CPU detection' is an IO port, and 'POW _ ALL' is an IO port) and a single-chip microcomputer circuit start to work, when the key pressing is detected by a POWER _ TEST pin of a single-chip microcomputer chip N1, a pin 1 PD 3/INT 1 of the chip N1 is high-level, and a pin 6 of the chip N2 is controlled to be low-level, so that a pin G of an MOS tube VT1 is pulled low, and the normal enabling of the external POWER supply is kept; the 2-pin PD 4/XCK/T0 of the chip N1 is also simultaneously high, the 3-pin level of the control chip N2 is lowered, and the control circuit of the main CPU controls the whole enabling device to start working. When the equipment starts to work, the main CPU control circuit feeds back a CPU detection signal to the chip N1, and the chip N1 judges whether the equipment is started or not through a CPU detection pin; socket XS2 is the programming interface of the single chip.
The design can realize normal shutdown of equipment after the subway equipment presses a switch key for a long time in a startup state, the equipment is powered on and operates when the equipment presses the switch key in the shutdown state for a long time, the circuit can record the startup state before power failure when the equipment is powered off suddenly, the equipment is automatically started after being powered on suddenly if the equipment is in the startup state before the power failure, and the equipment is in the shutdown state after being powered on suddenly if the equipment is normally shutdown before the power failure.