CN210466375U - 4Mbps1553B bus communication board card with PXI specification - Google Patents

Abstract

The utility model provides a 4Mbps1553B bus communication board card of PXI specification, include: the system comprises a PCI bus interface, a PCI-to-PCIe bridge plate, a field programmable device, a 4M1553B transceiver, a high-speed dynamic random access memory, a bus signal acquisition module, an electric signal waveform generation digital-to-analog converter, a bus signal voltage amplitude control module, a signal level converter, a nonvolatile flash memory, a power supply management module and a connector. The 4Mbps1553B bus communication board card with the PXI specification is designed to be the PXI specification, and the board card provides two dual-redundancy 4Mbps1553B channels. The board card adopts Xilinx FPGA as a core processing device to realize an independently researched 4M1553B IP core. The PCI bus is connected with the FPGA through the bridge chip, and data transmission with large data volume is carried out in a DMA mode, so that the message processing capacity and the data transmission bandwidth of a host interface are greatly improved. Two 128MB DDR3 SDRAM onboard are used for buffering 1553B bus messages. The performance and the function of the board card can meet the requirements of the current avionics system.

Description

4Mbps1553B bus communication board card with PXI specification

Technical Field

The utility model relates to an avionics network communication technology field especially relates to a 4Mbps1553B bus communication integrated circuit board of PXI specification.

Background

The MIL-STD-1553B bus is abbreviated as 1553B bus, and the 1553B bus is a time-division command/response type multiplexing data bus in the aircraft. The 1553B bus has the characteristics of determined transmission delay, reliable transmission capability, strong fault-tolerant capability and the like, and is high in communication efficiency and simple and convenient to modify, expand and maintain. The method is widely applied to the fields of aviation, aerospace, ships, missiles and the like.

With the development of aerospace technology, the interactive information data volume of the avionics system is increased day by day, and the development requirement of the avionics system is difficult to meet by the traditional 1553B bus of 1 Mbps. Therefore, a need exists to develop a higher speed 1553B bus, a 1553B bus at 4Mbps, or even a 1553B bus at 10 Mbps. However, at present, no standard communication protocol chip of 4Mbps1553B exists, and domestic 4Mbps1553B bus products are few. Therefore, the development of a 4Mbps1553B bus product has great significance.

Disclosure of Invention

In order to solve current aeronautical equipment to 1553B bus transmission speed's requirement, satisfy avionics system's development demand, the utility model provides a 4Mbps1553B bus communication integrated circuit board of PXI specification, this integrated circuit board adopts discrete circuit to realize the communication electrical standard of 4Mbps1553B bus, designs to PXI specification, can be applied to in all PXI industrial control computers.

The 4Mbps1553B bus communication board card with the PXI specification comprises: the system comprises a PCI bus interface, a PCI-to-PCIe bridge plate, a field programmable device, a 4M1553B transceiver, a high-speed dynamic random access memory, a bus signal acquisition module, an electric signal waveform generation digital-to-analog converter, a bus signal voltage amplitude control module, a signal level converter, a nonvolatile flash memory, a power supply management module and a connector.

The PCI bus interface is connected with a PCI-to-PCIe bridge chip, the PCI-to-PCIe bridge chip is connected with a field programmable device, the PCI-to-PCIe bridge chip realizes the conversion between a PCI bus and a PCIe bus, and the field programmable device realizes a PCIe bus interface.

The field programmable device is connected with a PCI-to-PCIe bridge chip, a 4M1553B transceiver, a high-speed dynamic random access memory, a bus signal acquisition module, an electric signal waveform generation digital-to-analog converter, a bus signal voltage amplitude control module, a signal level converter, a nonvolatile flash memory and a power supply management module to realize overall control.

The 4M1553B transceiver is connected with the field programmable device and the connector, and the two 4M1553B transceivers realize two dual-redundant 4Mbps1553B channels.

The high-speed dynamic random access memory is connected with the field programmable device and is used for realizing the caching of 1553B bus messages.

And the bus signal acquisition module is connected with the field programmable device and the connector, and a 1553B bus signal passing through the connector enters the field programmable device after being processed by the bus signal acquisition module.

The electrical signal waveform generation digital-to-analog converter is connected with the field programmable device and the connector and is used for injecting common-mode voltage or outputting square wave and sine wave waveforms.

And the bus signal voltage amplitude control module is connected with the field programmable device and the 4M1553B transceiver and is used for realizing the control of the voltage amplitude of the 1553B bus signal.

And the signal level converter is connected with the field programmable device and the connector assembly and is used for realizing the input and output of direct current time or the input and output of 1553B channel triggering.

And the nonvolatile flash memory is connected with the field programmable device and used for data storage.

The power management module is connected with a PCI bus interface, a PCI-to-PCIe bridge piece, a field programmable device, a 4M1553B transceiver, a high-speed dynamic random access memory, a bus signal acquisition module, an electric signal waveform generation digital-to-analog converter, a bus signal voltage amplitude control module, a signal level converter, a nonvolatile flash memory and a connector and is used for providing various required voltages for the 4Mbps1553B bus communication board card of the PXI specification.

The connector is connected with a 4M1553B transceiver, a bus signal acquisition module, an electric signal waveform generation digital-to-analog converter and a signal level converter, and is a 1553B bus interface of the 4Mbps1553B bus communication board card of the PXI specification and a connector of the signal level converter.

The 4M1553B transceiver comprises: a 4M1553B transceiver module and a 1553B isolation transformer.

The 4M1553B transceiver module comprises an MOS tube building and transmitting unit and a 485 chip building and receiving unit.

The 4M1553B transceiver module is connected with the 1553B isolation transformer, so that the receiving and sending of 4Mbps1553B bus signals are realized.

The single channel 155B bus has dual redundant buses BUSA and BUSB.

The 4M1553B transceiver consists of two groups of 4M1553B transceiver modules and two 1553B isolation transformers and is used for realizing two dual-redundant 1553B channels.

The utility model has the advantages that: the 4Mbps1553B bus communication board card with the PXI specification is designed to be in the PXI specification, and the board card provides two dual-redundancy 4Mbps1553B channels. The 4Mbps1553B transceiver circuit is built by adopting discrete devices, and the electrical requirements of a 4Mbps1553B bus protocol are met. The board card adopts Xilinx FPGA as a core processing device to realize an independently researched 4M1553B IP core. The PCI bus is connected with the FPGA through the bridge chip, and data transmission with large data volume is carried out in a DMA mode, so that the message processing capacity and the data transmission bandwidth of a host interface are greatly improved. Two 128MB DDR3 SDRAM onboard are used for buffering 1553B bus messages. Meanwhile, the board card also provides a 1553B bus waveform monitoring function, bus signal voltage amplitude adjustment, common-mode voltage injection or electrical signal output of any waveform, direct-current time coding and decoding and temperature monitoring functions. The performance and the function of the board card can meet the requirements of the current avionics system.

The technical solution of the present invention is further described in detail by the accompanying drawings and examples.

Drawings

Fig. 1 is a block diagram of the 4Mbps1553B bus communication board card of the PXI specification provided by the present invention.

Fig. 2 is a block diagram illustrating a 4M1553B transceiver included in a 4Mbps1553B bus communication board according to the PXI standard of the present invention.

Detailed Description

As shown in fig. 1, the present invention provides a block diagram of a 4Mbps1553B bus communication board card with the PXI standard. The 4Mbps1553B bus communication board card with the PXI specification comprises: the system comprises a PCI bus interface 11, a PCI-to-PCIe bridge plate 12, a field programmable device 13, a 4M1553B transceiver 14, a high-speed dynamic random access memory 15, a bus signal acquisition module 16, an electric signal waveform generation digital-to-analog converter 17, a bus signal voltage amplitude control module 18, a signal level converter 19, a nonvolatile flash memory 20, a power management module 21 and a connector 22.

The PCI bus interface 11 is connected with a PCI-to-PCIe bridge chip 12, the PCI-to-PCIe bridge chip 12 is connected with a field programmable device 13, the PCI-to-PCIe bridge chip 12 realizes the conversion between a PCI bus and a PCIe bus, and the field programmable device 13 realizes a PCIe bus interface.

The host interface is a PCI bus interface, the PCI to PCIe bridge chip 12 is realized by a PEX8112 bridge chip, and the host and the 4Mbps1553B bus communication board card of the PXI specification carry out data transmission with large data volume in a DMA (byte memory access) mode, so that the data transmission bandwidth of the host interface is greatly improved.

The field programmable device 13 is connected with a PCI-to-PCIe bridge chip 12, a 4M1553B transceiver 14, a high-speed dynamic random access memory 15, a bus signal acquisition module 16, an electric signal waveform generation digital-to-analog converter 17, a bus signal voltage amplitude control module 18, a signal level converter 19, a nonvolatile flash memory 20 and a power management module 21, and the field programmable device 13 is realized by adopting a Xilinx Artix-7 FPGA and is used as a core processing device to realize overall control.

The 4M1553B transceiver 14 is connected with the field programmable device 13 and the connector 22, and the two 4M1553B transceivers 14 realize two dual-redundant 4Mbps1553B channels. One end of the 4M1553B transceiver 14 is connected with the field programmable device 13, the field programmable device 13 is used for realizing a 4M1553B IP core, 1553B bus signals output and input by the field programmable device 13 are serial Manchester coded signals, and the signals pass through the 4M1553B transceiver 14 and are connected into a 1553B bus system through the connector 22 connected to the other end of the 4M1553B transceiver 14 and a 1553B cable.

The high-speed dynamic random access memory 15 is connected with the field programmable device 13 and is used for realizing the caching of 1553B bus messages; the high-speed dynamic random access memory 15 comprises two 128MB DDR3 SDRAM which are respectively used for bus message caching of two 1553B channels, and the implementation requirements of a multi-channel full-function 1553B protocol are better met.

The bus signal acquisition module 16 is connected with the field programmable device 13 and the connector 22, and comprises two operational amplifiers and a 14-bit high-speed high-precision ADC with a sampling clock of 125MHz, and is used for realizing signal acquisition of 4Mbps1553B bus waveforms. One path of 1553B channel double redundant signals BUSA and BUSB on the connector 22 are respectively connected to two operational amplifiers at the front end of the ADC, two paths of signals passing through the operational amplifiers are respectively connected to two inputs of the ADC, the ADC completes analog-to-digital conversion of the BUSA and BUSB signals, the output of the ADC is connected to the field programmable device 13, and the field programmable device 13 further processes the digital output of the ADC.

The digital-analog converter 17 for generating electric signal waveform is connected with the field programmable device 13 and the connector 22, and comprises a DAC and a drive circuit, wherein the waveform output by the field programmable device 13 is output to the connector 22 through the DAC and the drive circuit, and is used for injecting common-mode voltage or outputting square waves, sine waves and other waveforms.

The bus signal voltage amplitude control module 18 is connected with the field programmable device 13 and the 4M1553B transceiver 14, and comprises a DAC and a driving circuit, and is used for controlling the amplitude of the 1553B bus signal voltage.

And the signal level converter 19 is connected with the field programmable device 13 and the connector 22 and is used for realizing input and output of direct current time or input and output of 1553B channel triggering.

And the nonvolatile flash memory 20 is connected with the field programmable device 13 and is used for storing the FPGA programming file.

The power management module 21 is connected with the PCI bus interface 11, the PCI-to-PCIe bridge piece 12, the field programmable device 13, the 4M1553B transceiver 14, the high-speed dynamic random access memory 15, the bus signal acquisition module 16, the electrical signal waveform generation digital-to-analog converter 17, the bus signal voltage amplitude control module 18, the signal level converter 19, the nonvolatile flash memory 20, and the connector 22, and is used to provide various voltages required by the 4Mbps1553B bus communication board card of the PXI specification.

The connector 22 is connected with the 4M1553B transceiver 14, the bus signal acquisition module 16, the electrical signal waveform generation digital-to-analog converter 17 and the signal level converter 19, and is a connector of the 1553B bus interface and the signal level converter 19 which are external to the 4Mbps1553B bus communication board card of the PXI specification.

As shown in fig. 2, the present invention provides a block diagram of a 4M1553B transceiver included in a 4Mbps1553B bus communication board in the PXI standard. The 4M1553B transceiver 14 includes: a 4M1553B transceiver module 30, a 1553B isolation transformer 40; the 4M1553B transceiver module 30 comprises an MOS tube building and transmitting unit 31 and a 485 chip building and receiving unit 32; the 4M1553B transceiver module 30 is connected with the 1553B isolation transformer 40, so that the receiving and sending of 4Mbps1553B bus signals are realized.

The single channel 155B bus has dual redundant buses BUSA and BUSB. The 4M1553B transceiver 14 is composed of two sets of 4M1553B transceiver modules 30 and two 1553B isolation transformers 40, and is used for realizing two dual redundant 1553B channels.

The MOS tube building and sending unit 31 is realized by adopting a double-MOS tube push-free output structure, has strong driving capability, and realizes output signal swing amplitude control through power supply voltage control of the MOS tube. The 485 chip building and receiving unit 32 is realized by adopting the 485 receiving chip to perform impedance coupling with the output end of the transmitting circuit. The MOS tube building and transmitting unit 31 and the 485 chip building and receiving unit 32 are both connected with the 1553B isolation transformer 40, so that the impedance is stable and good, and the reliability is high.

The utility model has the advantages that: the 4Mbps1553B bus communication board card with the PXI specification is designed to be in the PXI specification, and the board card provides two dual-redundancy 4Mbps1553B channels. The 4Mbps1553B transceiver circuit is built by adopting discrete devices, and the electrical requirements of a 4Mbps1553B bus protocol are met. The board card adopts Xilinx FPGA as a core processing device to realize an independently researched 4M1553B IP core. The PCI bus is connected with the FPGA through the bridge chip, and data transmission with large data volume is carried out in a DMA mode, so that the message processing capacity and the data transmission bandwidth of a host interface are greatly improved. Two 128MB DDR3 SDRAM onboard are used for buffering 1553B bus messages. Meanwhile, the board card also provides a 1553B bus waveform monitoring function, bus signal voltage amplitude adjustment, common-mode voltage injection or electrical signal output of any waveform, direct-current time coding and decoding and temperature monitoring functions. The performance and the function of the board card can meet the requirements of the current avionics system.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the preferred embodiments, those skilled in the art should understand that: the technical solution of the present invention can still be modified or replaced by other equivalent means, and the modified technical solution can not be separated from the spirit and scope of the technical solution of the present invention.

Claims (2)

1. The utility model provides a PXI specification's 4Mbps1553B bus communication integrated circuit board which characterized in that:

the 4Mbps1553B bus communication board card with the PXI specification comprises: the system comprises a PCI bus interface, a PCI-to-PCIe bridge plate, a field programmable device, a 4M1553B transceiver, a high-speed dynamic random access memory, a bus signal acquisition module, an electric signal waveform generation digital-to-analog converter, a bus signal voltage amplitude control module, a signal level converter, a nonvolatile flash memory, a power management module and a connector;

the PCI-to-PCIe bridge chip is connected with a field programmable device, the PCI-to-PCIe bridge chip realizes the conversion between a PCI bus and a PCIe bus, and the field programmable device realizes a PCIe bus interface;

the field programmable device is connected with a PCI-to-PCIe bridge chip, a 4M1553B transceiver, a high-speed dynamic random access memory, a bus signal acquisition module, an electric signal waveform generation digital-to-analog converter, a bus signal voltage amplitude control module, a signal level converter, a nonvolatile flash memory and a power supply management module to realize overall control;

the 4M1553B transceivers are connected with the field programmable device and the socket connector, and the two 4M1553B transceivers realize two dual-redundant 4Mbps1553B channels;

the high-speed dynamic random access memory is connected with the field programmable device and is used for realizing the caching of 1553B bus messages;

the bus signal acquisition module is connected with the field programmable device and the connector, and a 1553B bus signal passing through the connector enters the field programmable device after being processed by the bus signal acquisition module;

the electric signal waveform generation digital-to-analog converter is connected with the field programmable device and the connector and is used for injecting common-mode voltage or outputting square wave and sine wave waveforms;

the bus signal voltage amplitude control module is connected with the field programmable device and the 4M1553B transceiver and is used for realizing control of 1553B bus signal voltage amplitude;

the signal level converter is connected with the field programmable device and the connector assembly and is used for realizing the input and output of direct current time or the input and output of 1553B channel triggering;

the nonvolatile flash memory is connected with the field programmable device and used for data storage;

the power management module is connected with a PCI bus interface, a PCI-to-PCIe bridge plate, a field programmable device, a 4M1553B transceiver, a high-speed dynamic random access memory, a bus signal acquisition module, an electric signal waveform generation digital-to-analog converter, a bus signal voltage amplitude control module, a signal level converter, a nonvolatile flash memory and a connector and is used for providing various required voltages for the 4Mbps1553B bus communication board card in the PXI specification;

the connector is connected with a 4M1553B transceiver, a bus signal acquisition module, an electric signal waveform generation digital-to-analog converter and a signal level converter, and is a 1553B bus interface of the 4Mbps1553B bus communication board card of the PXI specification and a connector of the signal level converter.

2. The PXI-compliant 4Mbps1553B bus communication board as recited in claim 1, wherein:

the 4M1553B transceiver comprises: a 4M1553B transceiver module and a 1553B isolation transformer;

the 4M1553B transceiver module comprises an MOS tube building and transmitting unit and a 485 chip building and receiving unit;

the 4M1553B transceiver module is connected with a 1553B isolation transformer to realize the receiving and sending of 4Mbps1553B bus signals;

the single channel 155B bus has dual redundant buses BUSA and BUSB;

the 4M1553B transceiver consists of two groups of 4M1553B transceiver modules and two 1553B isolation transformers and is used for realizing two dual-redundant 1553B channels.

Images