CN205377911U - 1553B bus communication system - Google Patents
1553B bus communication system Download PDFInfo
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- CN205377911U CN205377911U CN201620088346.6U CN201620088346U CN205377911U CN 205377911 U CN205377911 U CN 205377911U CN 201620088346 U CN201620088346 U CN 201620088346U CN 205377911 U CN205377911 U CN 205377911U
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Abstract
The utility model discloses a 1553B bus communication system, what the line transformer was assembled to its first total line transformer and second elementarily all is used for connecting the 1553B bus, the secondary 1553B data communication end of connecting field programmable gate array respectively through bus transceiver of first total line transformer and the total line transformer of second, field programmable gate array's serial ports data communication end is connected to the first communication end of communication interface module, the second communication end of communication interface module is used for connecting the serial communication bus, field programmable gate array's clock signal input is connected to the clock signal output of clock module. The utility model discloses effectively compensate the current defect of scheme in the aspect of volume, price and adaptability etc.
Description
Technical field
This utility model relates to communication bus technologies field, in particular to a kind of 1553B bus communication system.
Background technology
It is that the one that U.S. Department of Defense formulates has confirmability and transmits reliable data/address bus that MIL-STD-1553 bus (is called for short 1553B bus), belong to the time multiplex bus of Double redundancy backup, be widely used in the fields such as aircraft, vehicle, naval vessel, space flight.Mainly being made up of bus control unit (BC), remote terminal (RT), bus monitor (BM), bonder and cable etc. in physical layer 1553B bus, wherein BC, RT, BM are communication terminal.Current communication terminal adopts special third party's 1553B protocol chip in conjunction with the design of a CPU mostly.
The volume of present communications terminal design is bigger than normal.Special third party's 1553B protocol chip volume is bigger, add as its supporting power supply, CPU, transformator etc., the board area of whole communication terminal has reached 100mm × 80mm, and often there is strict requirement in the fields such as the aircraft of its application, space flight for volume and weight, add the difficulty of communication terminal overall plan design.
The high expensive of present communications terminal design.Third party's 1553B protocol chip special in the market is expensive, and monolithic price is all not less than 10000 yuan so that communication terminal cost is substantially increased, and namely reduces economic benefit and also reduces the competitiveness of communication terminal.
The waste of present communications terminal design is higher.It is integrated with complete 1553B agreement, tri-kinds of mode of operations of completely compatible BC, RT, BM in special third party's 1553B protocol chip, software design patterns can be passed through.In practical application, the communication terminal in 1553B bus is often operated in single-mode, and the resource consumed for other patterns compatible is the formation of waste.
The motility of present communications terminal design is not enough.Communication terminal in 1553B bus, usually used as the translation interface of communication protocol, converts other equipment being connected in bus or other communication protocols of internal system use to, such as CAN or RS422 by 1553B bus communication.Current communication terminal is by the restriction of selected CPU hardware resource, it is impossible to realize the flexible expansion of internal communications interface.
Utility model content
The purpose of this utility model seeks to provide a kind of 1553B bus communication system, and this system effectively makes up existing scheme defect in volume, price and adaptability etc..
For realizing this purpose, 1553B bus communication system designed by this utility model, it is characterized in that: it includes field programmable gate array, first total line transformer, second total line transformer, bus transceiver, communication interface modules and clock module, wherein, the primary of described first total line transformer and second total line transformer is all used for connecting 1553B bus, the secondary of first total line transformer and second total line transformer connects the 1553B data communication end of field programmable gate array respectively through bus transceiver, first communication ends of communication interface modules connects the serial data communication end of field programmable gate array, the second communication end of communication interface modules is used for connecting serial communication bus, the clock signal output terminal of described clock module connects the clock signal input terminal of field programmable gate array.
This utility model utilizes a field programmable gate array (FPGA, Field-ProgrammableGateArray) chip substitutes special third party's 1553B protocol chip of current main-stream 1553B communication terminal employing and the design of a CPU, greatly reduces circuit volume and cost.Meanwhile, evade the external pin connected mode that special third party's 1553B protocol chip and CPU adopt, eliminated two chip chambers owing to being subject to external disturbance and interactive probability, improve communication terminal and process ability and the job stability of mass data.
This utility model is programmable gate array internal module design aspect at the scene, only remain the part related in 1553B bus protocol, evade configuration process when current main-stream 1553B communication terminal designs, special third party's 1553B protocol chip is complicated, reduce the design difficulty of communication terminal.Simultaneously as adopt hardware program language to carry out the cutting-pattern design of 1553B bus protocol, reduce the probability not mating the communication abnormality caused due to agreement, improve the reliability of communication terminal.
The type of communication interface circuit of the present utility model and quantity can flexible expansion according to actual needs, improve the adaptability of communication terminal.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model；
Wherein, 1 field programmable gate array, 1.1 Clock management modules, 1.2 first decoders, 1.3 first encoders, 1.4 protocol processors, 1.5 random access memory read-write controllers, 1.6 universal asynchronous receiving-transmitting transmission control unit (TCU)s, 1.7 random access memorys, 1.8 second decoders, 1.9 second encoders, 2 first total line transformers, 3 second total line transformers, 4 bus transceivers, 5 communication interface modules, 6 clock modules.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail:
1553B bus communication system as shown in Figure 1, it includes field programmable gate array 1, first total line transformer 2, second total line transformer 3, bus transceiver 4, communication interface modules 5 and clock module 6, wherein, the primary of described first total line transformer 2 and second total line transformer 3 is all used for connecting 1553B bus, the secondary of first total line transformer 2 and second total line transformer 3 connects the 1553B data communication end of field programmable gate array 1 respectively through bus transceiver 4, first communication ends of communication interface modules 5 connects the serial data communication end of field programmable gate array 1, the second communication end of communication interface modules 5 is used for connecting serial communication bus, the clock signal output terminal of described clock module 6 connects the clock signal input terminal of field programmable gate array 1.Communication interface modules 5 is responsible for realizing the conversion of 1553B communication protocols serial communication protocol, flexibly customized protocol type.
Above-mentioned first total line transformer 2 and second total line transformer 3 all adopt the 1553B isolating transformer of standard.
Above-mentioned bus transceiver 4 is responsible for realizing transmission and the switching received and transformator 9V end differential signal and the conversion of FPGA end 3.3V level signal, and the 1553B transceiver of employing standard, voltage specification is 3.3V, with FPGA level match.
Above-mentioned clock module 6 adopts crystal oscillator, has high accuracy and good temperature characterisitic, and clock frequency is chosen as 64MHz, and the real-time of precision and encoding and decoding to ensure output waveform pulsewidth meets protocol requirement.
nullIn technique scheme，Described field programmable gate array 1 includes Clock management module 1.1、First decoder 1.2、First encoder 1.3、Second decoder 1.8、Second encoder 1.9、Protocol processor 1.4、Random access memory (RAM) read-write controller 1.5、Universal asynchronous receiving-transmitting transmission (UniversalAsynchronousReceiver/Transmitter，UART) controller 1.6 and random access memory 1.7 (randomaccessmemory，RAM)，The input of described Clock management module 1.1 connects the clock signal output terminal of clock module 6，The clock interface of the first outfan connection protocol processor 1.4 of Clock management module 1.1，The clock interface of the second outfan connection universal asynchronous receiving-transmitting transmission control unit (TCU) 1.6 of Clock management module 1.1，First communication interface of bus transceiver 4 connects the secondary of first total line transformer 2，The second communication interface of bus transceiver 4 connects the secondary of second total line transformer 3，The input channel of the first decoder 1.2 connects the third communication interface of bus transceiver 4，The output channel of the first encoder 1.3 connects the fourth communication interface of bus transceiver 4，The input channel of the second decoder 1.8 connects the fifth communication interface of bus transceiver 4，The output channel of the second encoder 1.9 connects the 6th communication interface of bus transceiver 4，The decoding data input pin of the signal output part connection protocol processor 1.4 of described first decoder 1.2 and the second decoder 1.8，The encoding data communication end of the encoding data communication end connection protocol processor 1.4 of the first encoder 1.3 and the second encoder 1.9；
The control bus communication end of described protocol processor 1.4, data bus communication end and address bus communication ends are respectively through controlling bus, data/address bus and the control bus communication end of address bus connection universal asynchronous receiving-transmitting transmission control unit (TCU) 1.6, data bus communication end and address bus communication ends；The serial data communication end that serial data communication end is field programmable gate array 1 of universal asynchronous receiving-transmitting transmission control unit (TCU) 1.6；
Three data communication channels of described random access memory read-write controller 1.5 connect described control bus, data/address bus and address bus respectively, three data communication channels of described random access memory 1.7 connect described control bus, data/address bus and address bus respectively, and the read-write control signal outfan of described random access memory read-write controller 1.5 connects the Read-write Catrol end of random access memory 1.7.
In technique scheme, described first total line transformer 2 is identical with the transformation ratio of second total line transformer 3.The transformation ratio of described first total line transformer 2 and second total line transformer 3 is 2:1.The primary of described first total line transformer 2 and second total line transformer 3 is 18V differential signal, and the secondary of first total line transformer 2 and second total line transformer 3 is 9V differential signal.
In technique scheme, decoder is decoded converting for the unipolarity Manchester code exported by bus transceiver 4, obtain the 20 bit instruction words or the data word that need, and verify, word type, data and check results are exported to protocol processor 1.4.
Data to be sent are carried out parallel-serial conversion for the control signal according to protocol processor 1.4 by encoder, generate the synchronous head of corresponding word type, increase check bit, then according to Manchester code rule is encoded, finally changes into differential signal and send to bus transceiver 4.
Protocol processor 1.4 realizes required all communication functions and data interaction according to application layer protocol, mainly includes instruction and data reception, feedback states word, feedback data word, communication Protocol Conversion etc..
Random access memory 1.7 is used for all instructions and the data that store in communication process, it is simple to inquiry at any time and reading.The FPGA block random access memory carried can be adopted during programming to realize, so can save off-chip random access memory, reduced in size and cost.
Random access memory read-write controller 1.5 is for being written and read operating to random access memory 1.7 according to control bus, address bus and data/address bus content.
Universal asynchronous receiving-transmitting transmission control unit (TCU) 1.6 is for being responsible for realizing the communication between FPGA and serial communication bus RS422, and the data of reception are sent to random access memory read-write controller 1.5.
Clock management module 1.1, for outside high-frequency clock is carried out shaping with phase-locked, is realized by the global clock interconnection resource of FPGA, it is possible to reduce the clock jitter between depositor and time delay.
In the present embodiment, field programmable gate array 1 selects FPGAXC3S250E-4VQ (G) 100I of XILINX, this FPGA is encapsulated as VQ (G) 100, in homologous series, size is minimum, its resource is then very abundant, have 250,000 system door resources, abundant I/O interface, make terminal size reach while meeting scheme needs minimum；Communication interface modules 5 can be customized as required, in order to improve versatility, adopts 4 road RS422 interfaces in the present invention；The PM-DB2725EX of bus Transformer Selection HOLT, transformation ratio is 2:1；Bus transceiver 4 selects the HI-1573PSI of HOLT, supports the standard 1335B bus of 1Mbps speed.The all electronic devices and components used in the present embodiment are Surface Mount Component except total line transformer, and circuit board size is 60mm × 50mm.
This utility model can realize the conversion communication between 1553B data and serial data by a field programmable gate array 1, greatly reduces circuit volume and cost.
The content that this specification is not described in detail belongs to the known prior art of professional and technical personnel in the field.
Claims (6)
- null1. a 1553B bus communication system，It is characterized in that: it includes field programmable gate array (1)、First total line transformer (2)、Second total line transformer (3)、Bus transceiver (4)、Communication interface modules (5) and clock module (6)，Wherein，The primary of described first total line transformer (2) and second total line transformer (3) is all used for connecting 1553B bus，The secondary of first total line transformer (2) and second total line transformer (3) connects the 1553B data communication end of field programmable gate array (1) respectively through bus transceiver (4)，First communication ends of communication interface modules (5) connects the serial data communication end of field programmable gate array (1)，The second communication end of communication interface modules (5) is used for connecting serial communication bus，The clock signal output terminal of described clock module (6) connects the clock signal input terminal of field programmable gate array (1).
- null2. 1553B bus communication system according to claim 1，It is characterized in that: described field programmable gate array (1) includes Clock management module (1.1)、First decoder (1.2)、First encoder (1.3)、Second decoder (1.8)、Second encoder (1.9)、Protocol processor (1.4)、Random access memory read-write controller (1.5)、Universal asynchronous receiving-transmitting transmission control unit (TCU) (1.6) and random access memory (1.7)，The input of described Clock management module (1.1) connects the clock signal output terminal of clock module (6)，The clock interface of the first outfan connection protocol processor (1.4) of Clock management module (1.1)，The clock interface of the second outfan connection universal asynchronous receiving-transmitting transmission control unit (TCU) (1.6) of Clock management module (1.1)，First communication interface of bus transceiver (4) connects the secondary of first total line transformer (2)，The second communication interface of bus transceiver (4) connects the secondary of second total line transformer (3)，The input channel of the first decoder (1.2) connects the third communication interface of bus transceiver (4)，The output channel of the first encoder (1.3) connects the fourth communication interface of bus transceiver (4)，The input channel of the second decoder (1.8) connects the fifth communication interface of bus transceiver (4)，The output channel of the second encoder (1.9) connects the 6th communication interface of bus transceiver (4)，The decoding data input pin of signal output part connection protocol processor (1.4) of described first decoder (1.2) and the second decoder (1.8)，The encoding data communication end of encoding data communication end connection protocol processor (1.4) of the first encoder (1.3) and the second encoder (1.9)；The control bus communication end of described protocol processor (1.4), data bus communication end and address bus communication ends are respectively through controlling bus, data/address bus and the control bus communication end of address bus connection universal asynchronous receiving-transmitting transmission control unit (TCU) (1.6), data bus communication end and address bus communication ends；The serial data communication end of universal asynchronous receiving-transmitting transmission control unit (TCU) (1.6) is the serial data communication end of field programmable gate array (1)；Three data communication channels of described random access memory read-write controller (1.5) connect described control bus, data/address bus and address bus respectively, three data communication channels of described random access memory (1.7) connect described control bus, data/address bus and address bus respectively, and the read-write control signal outfan of described random access memory read-write controller (1.5) connects the Read-write Catrol end of random access memory (1.7).
- 3. 1553B bus communication system according to claim 1, it is characterised in that: described first total line transformer (2) is identical with the transformation ratio of second total line transformer (3).
- 4. 1553B bus communication system according to claim 3, it is characterised in that: the transformation ratio of described first total line transformer (2) and second total line transformer (3) is 2:1.
- 5. 1553B bus communication system according to claim 3, it is characterized in that: the primary of described first total line transformer (2) and second total line transformer (3) is 18V differential signal, the secondary of first total line transformer (2) and second total line transformer (3) is 9V differential signal.
- 6. 1553B bus communication system according to claim 1, it is characterised in that: above-mentioned clock module 6 is crystal oscillator, and the clock frequency of this crystal oscillator is 64MHz.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620088346.6U CN205377911U (en) | 2016-01-28 | 2016-01-28 | 1553B bus communication system |
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| CN201620088346.6U CN205377911U (en) | 2016-01-28 | 2016-01-28 | 1553B bus communication system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109245977A (en) * | 2018-08-13 | 2019-01-18 | 北方电子研究院安徽有限公司 | 1553B bus communication module, communication system and its communication means |
| CN110556124A (en) * | 2019-09-06 | 2019-12-10 | 上海航天测控通信研究所 | Aerospace digital sound mixing device based on 1553B bus |
| CN110955620A (en) * | 2019-12-13 | 2020-04-03 | 中国兵器装备集团自动化研究所 | 1553B bus protocol system based on PCIE |
| CN111130966A (en) * | 2019-12-24 | 2020-05-08 | 中国航空工业集团公司西安飞机设计研究所 | 1553B bus real-time filtering device and filtering transmission method |
-
2016
- 2016-01-28 CN CN201620088346.6U patent/CN205377911U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109245977A (en) * | 2018-08-13 | 2019-01-18 | 北方电子研究院安徽有限公司 | 1553B bus communication module, communication system and its communication means |
| CN110556124A (en) * | 2019-09-06 | 2019-12-10 | 上海航天测控通信研究所 | Aerospace digital sound mixing device based on 1553B bus |
| CN110955620A (en) * | 2019-12-13 | 2020-04-03 | 中国兵器装备集团自动化研究所 | 1553B bus protocol system based on PCIE |
| CN110955620B (en) * | 2019-12-13 | 2023-06-13 | 中国兵器装备集团自动化研究所 | 1553B bus protocol system based on PCIE |
| CN111130966A (en) * | 2019-12-24 | 2020-05-08 | 中国航空工业集团公司西安飞机设计研究所 | 1553B bus real-time filtering device and filtering transmission method |
| CN111130966B (en) * | 2019-12-24 | 2021-10-15 | 中国航空工业集团公司西安飞机设计研究所 | 1553B bus real-time filtering device and filtering transmission method |
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