CN210431483U - Message processing device based on FPGA - Google Patents

Abstract

The utility model provides a message processing apparatus based on FPGA, include: the data acquisition device acquires initial message data; each first register in the plurality of first registers is in communication connection with the data acquisition device, and stores each field content of the initial message data; each second register in the plurality of second registers stores each processing action of the processing action group, the number of the first registers is the same as that of the second registers, and each second register is in one-to-one communication connection with each first register; and the data processing device is in communication connection with the second registers, calls each processing action in the second registers to process each field content in the first registers, and generates processed message data.

Description

Message processing device based on FPGA

Technical Field

The present disclosure belongs to the technical field of information processing, and particularly relates to a message processing apparatus based on an FPGA.

Background

A message (message) is a data unit exchanged and transmitted in the network, i.e. a data block to be sent by a station at one time. The message contains complete data information to be sent, and the length of the message can be inconsistent, and is unlimited and variable.

At present, rail transit signal manufacturers are numerous, and the types of signal data provided by the rail transit signal manufacturers are different. With the increase of the scale of the rail transit, the signal message data with various types generates great difficulty for the unified management of the rail transit (such as subway).

In the prior art, the technical schemes of Automatic Train Supervision (ATS) message collection and forwarding are mostly divided into two types: one scheme is based on a software algorithm, a message is collected through a TCP port, and a computer CPU executes a preset software algorithm and performs the work of identifying, matching, translating and forwarding the message; the other scheme is based on an ASIC special customized chip, and the special chip executes corresponding matching forwarding work on the collected messages.

However, in the scheme of configuring and forwarding the ATS message based on the software algorithm, the scheduling software algorithm in the CPU of the computer uses a serial processing mode, the processing efficiency of the message is low, the stability of the software is also reduced when the data volume of the message is large, and the requirement of a large bandwidth cannot be met. In the processing scheme based on the ASIC dedicated chip, the dedicated chip has limited modification and forwarding of each layer of message content, and the diversity and flexibility of the support function are poor, so that the expansion of new functions is difficult to meet.

Therefore, in the prior art, a message collection and forwarding scheme which can support high bandwidth and also meet flexibility is lacking in the process of processing the ATS message data.

SUMMERY OF THE UTILITY MODEL

In order to solve at least one of the above technical problems, the message processing apparatus based on the FPGA of the present disclosure is implemented by the following technical solutions.

A message processing device based on FPGA comprises: the data acquisition device acquires initial message data; each first register in the plurality of first registers is in communication connection with the data acquisition device, and stores each field content of the initial message data; each second register in the plurality of second registers stores each processing action of the processing action group, the number of the first registers is the same as that of the second registers, and each second register is in one-to-one communication connection with each first register; and the data processing device is in communication connection with the second registers, calls each processing action in the second registers to process each field content in the first registers, and generates processed message data.

The message processing device according to at least one embodiment of the present disclosure further includes a verification circuit, and the verification circuit verifies integrity of the processed message data.

The message processing device according to at least one embodiment of the present disclosure further includes a data forwarding device, the data forwarding device is in communication connection with the data processing device, and the data forwarding device forwards the processed message data.

The message processing device according to at least one embodiment of the present disclosure further includes a data forwarding device, the data forwarding device is in communication connection with the verification circuit, and the data forwarding device forwards the processed message data that passes the integrity verification.

According to the message processing apparatus according to at least one embodiment of the present disclosure, the data acquisition apparatus sends each field content of the initial message data to each first register, respectively.

According to the message processing device of at least one embodiment of the present disclosure, the check circuit includes signal detection circuits and status signal generation circuits, the number of the signal detection circuits is the same as the number of the first registers and the number of the second registers, and each signal detection circuit is electrically connected to the status signal generation circuit; each signal detection circuit detects whether each field content of the processed message data is missing, and the state signal generation circuit generates an integrity check passing signal based on the detection result of each signal detection circuit.

According to the message processing apparatus of at least one embodiment of the present disclosure, the verification circuit further includes a trigger circuit, the trigger circuit is electrically connected to the status signal generation circuit, and the trigger circuit generates a trigger signal based on the integrity verification pass signal.

According to the message processing device of at least one embodiment of the present disclosure, the check circuit includes a signal detection circuit and a status signal generation circuit, the number of the signal detection circuits is the same as the number of the first registers and the number of the second registers, each signal detection circuit is electrically connected to the status signal generation circuit, each signal detection circuit detects whether each field content of the processed message data is missing, the status signal generation circuit generates an integrity check passing signal based on a detection result of each signal detection circuit, and the data forwarding device forwards the processed message data that passes the integrity check based on the integrity check passing signal.

According to the message processing device of at least one embodiment of the present disclosure, the check circuit further includes a trigger circuit, the trigger circuit is electrically connected to the status signal generation circuit, the trigger circuit generates a trigger signal based on the integrity check pass signal, and the data forwarding device forwards the processed message data based on the trigger signal.

The message processing device according to at least one embodiment of the present disclosure further includes a memory, the memory stores a plurality of processing action groups, and the data processing device selects a corresponding processing action group from the plurality of processing action groups in the memory based on a feature value in a bitmap of the initial message data, and stores each processing action of the processing action group in each second register.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 is a block diagram schematically illustrating a structure of an FPGA-based message processing apparatus according to an embodiment of the present disclosure.

Fig. 2 is a block diagram schematically illustrating the structure of an FPGA-based message processing apparatus according to still another embodiment of the present disclosure.

Fig. 3 is a block diagram schematically illustrating the structure of an FPGA-based message processing apparatus according to still another embodiment of the present disclosure.

Fig. 4 is a block diagram schematic structure of an FPGA-based message processing apparatus according to still another embodiment of the present disclosure.

Fig. 5 is a block diagram schematic structure of a check circuit of the FPGA-based message processing apparatus according to an embodiment of the present disclosure.

Fig. 6 is a block diagram schematic structure of a check circuit of an FPGA-based message processing apparatus according to still another embodiment of the present disclosure.

Fig. 7 is a block diagram schematic structure of an FPGA-based message processing apparatus according to still another embodiment of the present disclosure.

Description of reference numerals:

100 message processing device based on FPGA

101 data acquisition device

102 first register

103 second register

104 data processing device

105 verification circuit

1051 signal detection circuit

1052 state signal generating circuit

1053 trigger circuit

106 data forwarding apparatus

107 memory.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., "in the sidewall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

Fig. 1 is a block diagram schematically illustrating a structure of an FPGA-based message processing apparatus 100 according to an embodiment of the present disclosure.

The message processing apparatus 100 based on the FPGA includes: the data acquisition device 101 is used for acquiring initial message data by the data acquisition device 101; each first register 102 in the plurality of first registers 102 is in communication connection with the data acquisition device 101, and each first register 102 in the plurality of first registers 102 stores each field content of the initial message data; a plurality of second registers 103, wherein each second register 103 in the plurality of second registers 103 stores each processing action of the processing action group, the number of the first registers 102 is the same as that of the second registers 103, and each second register 103 is in one-to-one communication connection with each first register 102; and the data processing device 104, the data processing device 104 is connected with each second register 103 in a communication way, and the data processing device 104 calls each processing action in each second register 103 to process each field content in each first register 102 and generate processed message data.

The data acquisition device 101 in the present embodiment may be a data acquisition device in the related art, and the specific circuit configuration thereof is not particularly limited in the present embodiment. The data acquisition device 101 can acquire initial message data of different signal manufacturers through an external ATS interface, the initial message data has a plurality of field contents, and a plurality of first registers 102 with preset quantity can be configured according to the field contents of the initial message data of different manufacturers.

Fig. 1 exemplarily shows 3 first registers 102, and those skilled in the art can adapt the number of the first registers 102, where each first register 102 stores each field content of the initial message data, and preferably, each first register 102 stores each field content of the initial message data according to a preset sequence.

The number of the second registers 103 is the same as the number of the first registers 102, and fig. 1 also exemplarily shows 3 second registers 103, each second register 103 in the plurality of second registers 103 stores each processing action of the processing action group, and preferably, each second register 103 stores each processing action of the processing action group in a preset order, so that each processing action stored in each second register 103 can process each field content stored in each first register 102.

For example, some initial message data includes the following field contents: SystemID, Total Length, Multi-flag, Package Data, and other remaining contents, at least five first registers are required to store the contents of these fields, respectively. Illustratively, at least five second registers are needed to store five processing actions of the processing action group, and the data processing device 104 invokes each processing action in each second register 103 to process each field content in each first register 102, so as to generate processed message data.

Preferably, the data acquisition device 101 sends each field content of the initial message data to each first register 102. More preferably, the data acquisition device 101 sends each field content of the initial message data to each first register 102 according to a predetermined sequence.

Fig. 2 is a schematic block diagram of a structure of an FPGA-based message processing apparatus 100 according to still another embodiment of the present disclosure.

The FPGA-based message processing apparatus 100 includes: the data acquisition device 101 is used for acquiring initial message data by the data acquisition device 101; each first register 102 in the plurality of first registers 102 is in communication connection with the data acquisition device 101, and each first register 102 in the plurality of first registers 102 stores each field content of the initial message data; a plurality of second registers 103, wherein each second register 103 in the plurality of second registers 103 stores each processing action of the processing action group, the number of the first registers 102 is the same as that of the second registers 103, and each second register 103 is in one-to-one communication connection with each first register 102; the data processing device 104 is in communication connection with each second register 103, and the data processing device 104 invokes each processing action in each second register 103 to process each field content in each first register 102 and generate processed message data; and a check circuit 105, wherein the check circuit 105 checks the integrity of the processed message data.

Fig. 3 is a schematic block diagram of a structure of an FPGA-based message processing apparatus 100 according to still another embodiment of the present disclosure.

The FPGA-based message processing apparatus 100 includes: the data acquisition device 101 is used for acquiring initial message data by the data acquisition device 101; each first register 102 in the plurality of first registers 102 is in communication connection with the data acquisition device 101, and each first register 102 in the plurality of first registers 102 stores each field content of the initial message data; a plurality of second registers 103, wherein each second register 103 in the plurality of second registers 103 stores each processing action of the processing action group, the number of the first registers 102 is the same as that of the second registers 103, and each second register 103 is in one-to-one communication connection with each first register 102; the data processing device 104 is in communication connection with each second register 103, and the data processing device 104 invokes each processing action in each second register 103 to process each field content in each first register 102 and generate processed message data; and a data forwarding device 106, wherein the data forwarding device 106 is in communication connection with the data processing device 104, and the data forwarding device 106 forwards the processed message data.

Preferably, the data forwarding device 106 may forward the processed message data to a device or apparatus outside the message processing device 100 for processing.

Fig. 4 is a block diagram schematically illustrating the structure of an FPGA-based message processing apparatus 100 according to still another embodiment of the present disclosure.

The FPGA-based message processing apparatus 100 includes: the data acquisition device 101 is used for acquiring initial message data by the data acquisition device 101; each first register 102 in the plurality of first registers 102 is in communication connection with the data acquisition device 101, and each first register 102 in the plurality of first registers 102 stores each field content of the initial message data; a plurality of second registers 103, wherein each second register 103 in the plurality of second registers 103 stores each processing action of the processing action group, the number of the first registers 102 is the same as that of the second registers 103, and each second register 103 is in one-to-one communication connection with each first register 102; the data processing device 104 is in communication connection with each second register 103, and the data processing device 104 invokes each processing action in each second register 103 to process each field content in each first register 102 and generate processed message data; the checking circuit 105, the checking circuit 105 checks the integrity of the processed message data; and a data forwarding device 106, wherein the data forwarding device 106 is in communication connection with the verification circuit 105, and the data forwarding device 106 forwards the processed message data passing the integrity verification.

The verification circuit in the above embodiment will be described in detail below, and those skilled in the art can select the verification circuit from the prior art, and preferably, select the verification circuit of the present disclosure described below.

Fig. 5 is a block diagram schematic structure of the check circuit 105 of the FPGA-based message processing apparatus according to an embodiment of the present disclosure.

The verification circuit 105 includes signal detection circuits 1051 and status signal generation circuits 1052, the number of the signal detection circuits 1051 is the same as the number of the first registers 102 and the number of the second registers 103, and each signal detection circuit 1051 is electrically connected to the status signal generation circuits 1052; each signal detection circuit 1051 detects whether each field content of the processed message data is missing, and the state signal generation circuit 1052 generates an integrity check pass signal based on the detection result of each signal detection circuit 1051.

Illustratively, if each signal detection circuit 1051 detects that each field content of the processed message data is not missing, the state signal generation circuit 1052 generates an integrity check pass signal. If each signal detection circuit 1051 detects that one or some of the contents of each field of the processed message data is missing, the state signal generation circuit 1052 does not generate an integrity check pass signal.

Illustratively, if each signal detection circuit 1051 detects that each field content of the processed message data is not missing, the status signal generation circuit 1052 generates an integrity check passing signal, and accordingly, the data forwarding device 106 forwards the processed message data that passes the integrity check based on the integrity check passing signal. If each signal detection circuit 1051 detects that one or more of the field contents of the processed message data are missing, the status signal generation circuit 1052 does not generate an integrity check pass signal, and accordingly, the data forwarding device 106 does not forward the processed message data.

Fig. 6 is a block diagram schematic structure of the check circuit 105 of the FPGA-based message processing apparatus according to still another embodiment of the present disclosure.

The verification circuit 105 includes signal detection circuits 1051, status signal generation circuits 1052 and trigger circuits 1053, the number of the signal detection circuits 1051 is the same as the number of the first registers 102 and the number of the second registers 103, and each signal detection circuit 1051 is electrically connected to the status signal generation circuits 1052; each signal detection circuit 1051 detects whether each field content of the processed message data is missing, and the state signal generation circuit 1052 generates an integrity check passing signal based on the detection result of each signal detection circuit 1051; the trigger circuit 1053 is electrically connected to the status signal generating circuit 1052, and the trigger circuit 1053 generates a trigger signal based on the integrity check pass signal.

Illustratively, if each signal detection circuit 1051 detects that each field content of the processed message data is not missing, the state signal generation circuit 1052 generates an integrity check passing signal, and the trigger circuit 1053 generates a trigger signal based on the integrity check passing signal. If each signal detection circuit 1051 detects that one or more of the contents of each field of the processed message data is missing, the state signal generation circuit 1052 does not generate an integrity check pass signal, and the trigger circuit 1053 does not generate a trigger signal.

Illustratively, if each signal detection circuit 1051 detects that each field content of the processed message data is not missing, the state signal generation circuit 1052 generates an integrity check passing signal, the trigger circuit 1053 generates a trigger signal based on the integrity check passing signal, and the data forwarding device 106 forwards the processed message data that passes the integrity check based on the trigger signal. If each signal detection circuit 1051 detects that one or more of the field contents of the processed message data are missing, the state signal generation circuit 1052 does not generate an integrity check pass signal, the trigger circuit 1053 does not generate a trigger signal, and the data forwarding device 106 does not forward the processed message data.

Fig. 7 is a block diagram schematic structure of an FPGA-based message processing apparatus according to still another embodiment of the present disclosure.

The message processing apparatus 100 based on the FPGA includes: the data acquisition device 101 is used for acquiring initial message data by the data acquisition device 101; each first register 102 in the plurality of first registers 102 is in communication connection with the data acquisition device 101, and each first register 102 in the plurality of first registers 102 stores each field content of the initial message data; a memory 107, the memory 107 storing a plurality of processing action groups; a plurality of second registers 103, wherein each second register 103 is in one-to-one communication connection with each first register 102; and the data processing device 104, the data processing device 104 is communicatively connected to each second register 103, the data processing device 104 is further communicatively connected to the memory 107, the data processing device 104 selects a corresponding processing action group from the plurality of processing action groups in the memory 107 based on a feature value in a Bitmap (Bitmap) of the initial packet data, and stores each processing action of the processing action group in each second register 103, and the data processing device 104 invokes each processing action in each second register 103 to process each field content in each first register 102, thereby generating processed packet data.

For example, a plurality of processing action groups, which are different and can process different message data (e.g., message data provided by different vendors), may be stored in the memory 107 in advance. In practical applications, an action table entry is stored in a memory of the FPGA-based Message processing apparatus, where the action table entry records which processing action groups the Message data with different characteristics need to be processed through, so as to forward the processed Message through a forwarding port corresponding to the processing action group, where the characteristics include Multi-flag, Version, Message _ Id, Content, and the like of the Message. It will be understood by those skilled in the art that the above features are not exactly the same depending on the type of message and will not be discussed here too much. In particular practice, the set of preset processing actions may be stored in the FPGA (e.g., in memory 107) in advance.

Preferably, each processing action group includes a BITMAP for indicating a plurality of processing actions included in the processing action group and positions of the plurality of processing actions in the processing action group. The data processing device 104 may determine a corresponding processing action group from among the plurality of processing action groups in the memory 107 based on a feature value in a Bitmap (Bitmap) of the initial packet data, read the Bitmap in the processing action group, and store the plurality of processing actions in the processing action group in the corresponding second register 103 according to the Bitmap of the processing action group and the mapping table of the processing actions.

Preferably, the FPGA-based message processing apparatus of the present disclosure further includes a plurality of forwarding ports, and each forwarding port of the plurality of forwarding ports forwards the message data processed by each processing action group.

The memory 107 in this embodiment may be provided in the embodiment corresponding to fig. 1 to 6.

The message processing device based on the FPGA can unify the output formats of ATS message data of all lines in a subway network, and facilitates the unified scheduling management of each line by a network level. The unified signal data of each circuit reduces the workload of the upper layer application of the cable network level on the screening and processing of the signal data. Meanwhile, the ATS message data of each line is processed based on the FPGA, the message is processed in a circuit module for processing the FPGA message, and the processed message is forwarded through a forwarding port corresponding to a processing action group, so that the combination of flexibly supporting various message content modification and forwarding is realized through the FPGA, and the flexibility is met while the relatively high bandwidth is supported.

Because the circuit characteristics of the FPGA, namely the FPGA is designed into a circuit, the FPGA can be designed into a pipeline (Pipe-line), so that the message revision forwarding process realized by the FPGA is also the pipeline setting, and when the FPGA processes the message in the circuit module for processing the FPGA message, the message data processed by the FPGA can be synchronously forwarded through the corresponding forwarding port, so that the processing speed of the data message is further improved.

In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example" or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims (10)

1. A message processing device based on FPGA is characterized by comprising:

the data acquisition device acquires initial message data;

each first register in the plurality of first registers is in communication connection with the data acquisition device, and stores each field content of the initial message data;

each second register in the plurality of second registers stores each processing action of the processing action group, the number of the first registers is the same as that of the second registers, and each second register is in one-to-one communication connection with each first register; and

and the data processing device is in communication connection with each second register, calls each processing action in each second register to process each field content in each first register and generates processed message data.

2. The message processing apparatus according to claim 1, further comprising a verification circuit that verifies integrity of the processed message data.

3. The message processing device according to claim 1, further comprising a data forwarding device, wherein the data forwarding device is communicatively connected to the data processing device, and the data forwarding device forwards the processed message data.

4. The message processing device according to claim 2, further comprising a data forwarding device, the data forwarding device being communicatively connected to the verification circuit, the data forwarding device forwarding the processed message data that passes the integrity verification.

5. The message processing device according to any of claims 1 to 4, wherein the data collection device sends the contents of each field of the initial message data to each first register.

6. The message processing apparatus according to claim 2, wherein the check circuit includes signal detection circuits and status signal generation circuits, the number of the signal detection circuits is the same as the number of the first registers and the number of the second registers, and each signal detection circuit is electrically connected to the status signal generation circuit; the signal detection circuits detect whether the content of each field of the processed message data is missing, and the state signal generation circuit generates an integrity check passing signal based on the detection result of each signal detection circuit.

7. The message processing device of claim 6, wherein the verification circuit further comprises a trigger circuit electrically connected to the status signal generating circuit, the trigger circuit generating a trigger signal based on the integrity check pass signal.

8. The message processing apparatus according to claim 4, wherein the check circuit includes signal detection circuits and status signal generation circuits, the number of the signal detection circuits is the same as the number of the first registers and the number of the second registers, each signal detection circuit is electrically connected to the status signal generation circuit, each signal detection circuit detects whether content of each field of the processed message data is missing, the status signal generation circuit generates an integrity check passing signal based on a detection result of each signal detection circuit, and the data forwarding apparatus forwards the processed message data that passes the integrity check based on the integrity check passing signal.

9. The message processing apparatus according to claim 8, wherein the check circuit further includes a trigger circuit, the trigger circuit is electrically connected to the status signal generating circuit, the trigger circuit generates a trigger signal based on the integrity check pass signal, and the data forwarding apparatus forwards the processed message data based on the trigger signal.

10. The message processing apparatus according to any of claims 1 to 4, further comprising a memory, wherein the memory stores a plurality of processing action groups, and the data processing apparatus selects a corresponding processing action group from the plurality of processing action groups in the memory based on the feature value in the bitmap of the initial message data, and stores the respective processing actions of the processing action group in the respective second registers.

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