CN210431446U - Bit synchronization device for quantum communication - Google Patents
Bit synchronization device for quantum communication Download PDFInfo
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- CN210431446U CN210431446U CN201921284885.7U CN201921284885U CN210431446U CN 210431446 U CN210431446 U CN 210431446U CN 201921284885 U CN201921284885 U CN 201921284885U CN 210431446 U CN210431446 U CN 210431446U
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Abstract
The application discloses a bit synchronization device for quantum communication, the device includes: at least two detectors, a bit synchronization processor and a delay controller; the output end of the detector is connected with the bit synchronization processor, and the detection end of the detector is used for receiving the quantum signal; the output end of the bit synchronization processor is connected with the first input end of the delay controller; the number of the output ends of the delay controller is the same as that of the detectors, and the output ends of the delay control units are correspondingly connected with the detectors; a second input of the delay controller is for receiving a local clock signal. The device provided by the application controls the detector by the same delay controller and bit synchronization processor. Even if the detector is influenced by the environment, because only one integrated delay controller and one bit synchronization processor are arranged, the influence of the environmental factors on each detector is the same, so that the accuracy of the detector on quantum signal detection is improved, and accurate bit synchronization is realized.
Description
The present application claims priority from a chinese patent application entitled "a high speed bit synchronizer for quantum key generation system" filed by the chinese patent office on 28/12/2018 with application number 201822240618.1, the entire contents of which are incorporated herein by reference.
Technical Field
The utility model relates to an optical communication technical field, in particular to a bit synchronizer for quantum communication.
Background
Since the twenty-first century, with the overall popularization of the internet, the global informatization level is continuously improved, the attention of governments, national defense, enterprises and individuals to information security is increasingly enhanced, and the demand for information security is increasing day by day. In recent years, quantum key distribution technology has attracted much attention because its unconditional security is guaranteed by the fundamental principles of quantum mechanics. Many international research institutes have conducted intensive research on theory and application, and some companies have also successively introduced commercial quantum key distribution products.
In a quantum key distribution system, a transmitting end encodes a quantum signal (photon) and then transmits the encoded quantum signal to a receiving end, and the receiving end needs to confirm the arrival time of the photon so as to detect the photon at the optimal time by using a detector, which is a bit synchronization process. Only after the bit synchronization process is completed, the quantum key distribution system can perform the subsequent negotiation process to generate the security key, so that the bit synchronization technology has an important role in the quantum key distribution system.
The bit synchronization device of the quantum key distribution system in the related art is shown in fig. 1, and each detector is followed by a delay unit, and each delay unit is followed by a bit synchronization processing unit. The delay units work independently of each other, and the bit synchronization units work independently of each other. Because the delay units and the bit synchronization processing units corresponding to the detectors are separately deployed, the integration level of the bit synchronization device is low, and the bit synchronization device is affected by the environment, for example, the heat generated by components is affected, and the environmental influence degrees of different detectors, the corresponding delay units and the bit synchronization processing units are different, so that the accuracy of the detectors for detecting the quantum signals is reduced.
SUMMERY OF THE UTILITY MODEL
The application provides a bit synchronizer for quantum communication to when solving the bit synchronizer in the correlation technique and receiving the environmental impact, different detectors and corresponding delay unit, bit synchronization processing unit all environmental impact degree are different, thereby reduce the problem of the degree of accuracy that the detector surveyed quantum signal.
The present application provides a bit synchronization apparatus for quantum communication, the apparatus comprising: at least two detectors, a bit synchronization processor and a delay controller;
the output end of the detector is connected with the bit synchronization processor, and the detection end of the detector is used for receiving quantum signals;
the output end of the bit synchronization processor is connected with the first input end of the delay controller;
the number of the output ends of the delay controller is the same as that of the detectors, and the output ends of the delay controller are correspondingly connected with the detectors;
the second input terminal of the delay controller is used for receiving a local clock signal.
Optionally, the delay controller includes at least two stages of delay units, and the number of stages of the delay units is the same as the number of detectors;
the input end of the first-stage delay unit in the delay units is the second input end of the delay controller and is used for receiving the local clock signal;
the output end of each stage of delay unit is correspondingly connected with each detector, and the output end of each stage of delay unit is connected with the input end of the next stage of delay unit.
Optionally, the delay controller includes at least two stages of delay units, and a difference between the number of stages of the delay units and the number of detectors is one;
the input end of the first-stage delay unit in the delay units is positioned at the second input end of the delay controller and is used for receiving the local clock signal, and the input end of the first-stage delay unit is connected with a corresponding detector;
the output end of each stage of delay unit is connected with the input end of the next stage of delay unit, and the output end of each stage of delay unit is correspondingly connected with each detector.
Optionally, the pitch of adjacent delay units in the delay controller ranges from 5 mm to 50 mm.
Optionally, the apparatus comprises 4 of said detectors.
Optionally, the detector is a photodiode or an avalanche diode.
In the present application, each detector in the bit synchronization device corresponds to the same delay controller and the same bit synchronization processor, and the detectors are controlled by the same delay controller and the same bit synchronization processor. Even if the detector is influenced by the environment, because only one integrated delay controller and one bit synchronization processor are arranged, the influence of the environmental factors on each detector is the same, so that the accuracy of the detector on quantum signal detection is improved, and accurate bit synchronization is realized.
Drawings
In order to more clearly explain the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art bit synchronizer;
FIG. 2 is a schematic diagram of a bit synchronization apparatus for quantum communication in accordance with an illustrative embodiment;
FIG. 3A is a schematic diagram of a delay controller shown in an exemplary embodiment;
FIG. 3B is a schematic diagram of a delay controller shown in another exemplary embodiment;
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
Fig. 2 is a block diagram illustrating a bit synchronization apparatus for quantum communication according to an exemplary embodiment, as shown in fig. 2, the bit synchronization apparatus including: at least two detectors 210, a bit synchronization processor 220 and a delay controller 230.
The output terminal of each detector 210 is connected to the bit synchronization processor 220, and the detection terminal of each detector 210 is used for receiving the quantum signal to be detected. In practical applications, the quantum signal is embodied as a pulse signal. The detector 210 receives the detection quantum signal through the detection end, and sends the detection result, i.e., the detection pulse, to the bit synchronization processing unit through the output end. The detector 210 may be a PIN photodiode or an Avalanche Photodiode (APD). The clock signal of the detector 210 at the time of detection is output by the delay controller 230, so that the detector 210 is connected to the corresponding output terminal of the delay controller 230.
The bit synchronization processor 220 is a processor, such as a Central Processing Unit (CPU), for Processing the detection sampling result of the detector 210, and outputs a delay control signal to the delay controller 230 according to the detection sampling result, so that the delay controller 230 outputs different clock signals to different detectors 210. Thus, the output of the bit synchronization processor 220 is coupled to a first input of a delay controller 230 for transmitting the delay control signal. A bit synchronization processor 230 is connected to the output of the detector 210. The bit synchronization processor 230 has a plurality of input ports connected to the outputs of the plurality of detectors, respectively.
The delay controller 230 is a highly integrated delay control module, such as a highly integrated delay control chip. A first input of the delay controller 230 is connected to an output of the bit synchronization processor 220 to receive the delay control signal output by the bit synchronization processor 220. A second input of the delay controller 230 is for receiving a local clock signal. The delay controller 230 delays the local clock signal received by the second input terminal according to the delay control signal of the bit synchronization processor 220, and outputs the delayed clock signal, i.e., the reference clock signal, to the detector 210, so that the detector 210 performs detection sampling according to the reference clock signal. The delay controller 230 has a plurality of outputs, each of which is individually connected to a corresponding one of the detectors 210.
The delay controller 230 outputs a reference clock to the detector 210 according to the received local clock and the delay control signal from the bit synchronization processor 220. The detector 210 outputs a detection pulse to the bit synchronization processor 220 according to the reference clock output from the delay controller 230 and the pulse signal received by itself. The bit synchronization processor 220 outputs a delay control signal to the delay controller 230 according to the received detection pulse output from the detector 210. And the above steps are circulated to complete the bit synchronization process.
Alternatively, the number of the detectors 210 is 4.
In one possible real-time approach, as shown in FIG. 3A, a portion of the delay unit integrated in delay controller 230 is shown. The delay controller 230 includes at least two stages of delay units, and the number of stages of delay units is the same as the number of detectors 210. Each delay unit delays the clock signal input thereto and outputs a reference clock signal. In the integrated delay unit, the input terminal of the first stage delay unit 231 is the second input terminal of the delay controller 230, and receives the clock signal without delay. The output end of each stage of delay unit in the delay controller 230 is correspondingly connected to each detector 210. The output end of each stage of delay unit corresponds to each detector 210 one by one, and the output end of each stage of delay unit is connected with the input end of the next stage of delay unit, i.e. the clock signal output by each stage of delay unit is the input signal of the next stage of delay unit.
In another possible embodiment, as shown in FIG. 3B, a portion of the delay unit integrated in the delay controller 230 is shown. The delay controller 230 includes at least two stages of delay units, and the difference between the number of stages of delay units and the number of detectors 210 is one. Each delay unit delays the clock signal input thereto and outputs a reference clock signal. In the example shown in fig. 3B, the clock signal input to the first stage delay unit 231 is directly output to the first detector, and the clock signal input to the first stage delay unit 231 is the local clock signal received by the second input terminal of the delay controller 230. The output end of each stage of delay unit is connected with the input end of the next stage of delay unit, and the output end of each stage of delay unit is correspondingly connected with each detector.
In the two possible embodiments, the delay units are connected with each other, so that different influences caused by environmental factors can be effectively avoided.
Alternatively, in the above two possible embodiments, the distance between adjacent delay units in the delay controller 230 is in the range of 5 mm to 50 mm.
In the embodiment of the application, each detector in the bit synchronization device corresponds to the same delay controller and the same bit synchronization processor, and the detectors are controlled by the same delay controller and the same bit synchronization processor. Even if the detector is influenced by the environment, because only one integrated delay controller and one bit synchronization processor are arranged, the influence of the environmental factors on each detector is the same, so that the accuracy of the detector on quantum signal detection is improved, and accurate bit synchronization is realized.
The application provides a bit synchronization device for quantum communication to improve the accuracy of a detector for detecting a quantum signal. In addition, the present application also introduces a bit synchronization process of the bit synchronization apparatus to more clearly and more fully introduce the bit synchronization apparatus. It should be noted that, depending on the actual application scenario and the communication bar, the process of implementing bit synchronization by the bit synchronization apparatus may vary. Therefore, the description of the bit synchronization process of the bit synchronization apparatus does not limit the bit synchronization apparatus. The bit synchronization process is as follows:
the transmitting end of the quantum key distribution system sets the intensity of transmitted light according to the channel attenuation value of the quantum channel; a receiving end of the quantum key distribution system sets appropriate detector configuration parameters according to the characteristics of the detector; the transmitting end of the quantum key distribution system generates bit synchronization calibration light and transmits the bit synchronization calibration light to the receiving end of the quantum key distribution system through a quantum channel; the receiving end of the quantum key distribution system finishes the time-interval scanning process, and the bit synchronization processing unit obtains the optimal delay value of each detector according to the scanning result; and the bit synchronization processing unit sends the optimal delay value obtained in the fourth step to the delay controller, and the delay controller adjusts the delay setting of each detector according to the optimal delay value to realize high-speed bit synchronization.
The detectors cooperate to complete scanning in a combined delay search range, and the combined delay search range is determined according to the delay efficiency relation of the detectors and the period size of pulse signal light sent by a quantum channel by a quantum key distribution system transmitting end: two points are taken at two sides of the peak value of the detector delay efficiency curve, the difference value of the delay values corresponding to the two points is equal to the period of pulse signal light sent by a quantum key distribution system transmitting end through a quantum channel, and the delay range between the two delay values is a combined delay search range.
The so-called time-share scanning means that the detectors cooperate to complete scanning of the joint delay search range, and each detector completes scanning in the partial delay search range. The specific time-interval scanning modes are various: scanning coarse grain in different time periods, scanning fine grain in different time periods, direct scanning fine grain in different time periods, algorithm scanning in different time periods, etc.
The present application has been described in detail with reference to specific embodiments and illustrative examples, but the description is not intended to limit the application. Those skilled in the art will appreciate that various equivalent substitutions, modifications or improvements may be made to the presently disclosed embodiments and implementations thereof without departing from the spirit and scope of the present disclosure, and these fall within the scope of the present disclosure. The protection scope of this application is subject to the appended claims.
Claims (6)
1. A bit synchronization apparatus for quantum communication, the apparatus comprising: at least two detectors, a bit synchronization processor and a delay controller;
the output end of the detector is connected with the bit synchronization processor, and the detection end of the detector is used for receiving quantum signals;
the output end of the bit synchronization processor is connected with the first input end of the delay controller;
the number of the output ends of the delay controller is the same as that of the detectors, and the output ends of the delay controller are correspondingly connected with the detectors;
the second input terminal of the delay controller is used for receiving a local clock signal.
2. The apparatus of claim 1, wherein the delay controller comprises at least two stages of delay units, the number of stages of the delay units is the same as the number of the detectors;
the input end of the first-stage delay unit in the delay units is the second input end of the delay controller and is used for receiving the local clock signal;
the output end of each stage of delay unit is correspondingly connected with each detector, and the output end of each stage of delay unit is connected with the input end of the next stage of delay unit.
3. The apparatus of claim 1, wherein the delay controller comprises at least two stages of delay units, and the difference between the number of stages of the delay units and the number of detectors is one;
the input end of the first-stage delay unit in the delay units is positioned at the second input end of the delay controller and is used for receiving the local clock signal, and the input end of the first-stage delay unit is connected with a corresponding detector;
the output end of each stage of delay unit is connected with the input end of the next stage of delay unit, and the output end of each stage of delay unit is correspondingly connected with each detector.
4. The apparatus of claim 2 or 3, wherein the pitch of adjacent delay cells in the delay controller is in the range of 5 mm to 50 mm.
5. An apparatus according to any one of claims 1 to 3, wherein the apparatus comprises 4 said detectors.
6. The apparatus of any one of claims 1 to 3, wherein the detector is a photodiode or an avalanche diode.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2018222406181 | 2018-12-28 | ||
| CN201822240618 | 2018-12-28 |
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| Publication Number | Publication Date |
|---|---|
| CN210431446U true CN210431446U (en) | 2020-04-28 |
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| CN201921284885.7U Active CN210431446U (en) | 2018-12-28 | 2019-08-08 | Bit synchronization device for quantum communication |
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