CN210429887U - Display substrate and display device thereof - Google Patents

Abstract

The disclosure provides a display substrate and a display device thereof. The display substrate includes: a substrate including a display region and a peripheral region; a plurality of sub-pixels located in the display area, the sub-pixels including: a light-emitting element including a first electrode, a light-emitting layer, and a second electrode; a plurality of first power lines located in the display region; the first power bus is positioned in the peripheral zone and electrically connected with the plurality of first power lines; and the second power line is positioned in the peripheral area and is electrically connected with the second electrode, the second power line comprises a first part and a second part, the first part surrounds the second boundary, the third boundary and the fourth boundary of the display area, and the second part is positioned on one side of the first power bus line, which is far away from the display area. A gap exists between the first power bus and the second portion of the second power line. The orthographic projection of the gap on the substrate base plate is at least partially overlapped with the orthographic projection of the second electrode on the substrate base plate. The present disclosure can reduce interference between different signal lines.

Description

Display substrate and display device thereof

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate and a display device thereof.

Background

With the rapid development of AMOLED (Active Matrix Organic Light Emitting Diode), the development of smart terminals such as mobile phones has entered the era of full-screen and narrow-frame. In order to bring a better use experience to users, the characteristics of a full-screen, a narrow frame, high resolution, curling, wearing and/or folding and the like must become an important development direction of future AMOLEDs.

In the related art, in order to make the display panel lighter and thinner to accommodate the later folding and rolling products, a touch technology has been developed. For example, the touch technology may be fmloc (flexible Multi Layer On cell) technology.

SUMMERY OF THE UTILITY MODEL

The inventors of the present disclosure found that, in the related art, signal interference may occur between the touch electrode line and the data line or the GOA signal line, resulting in poor display.

In view of this, embodiments of the present disclosure provide a display substrate to reduce signal interference.

According to an aspect of an embodiment of the present disclosure, there is provided a display substrate including: the display device comprises a substrate and a display unit, wherein the substrate comprises a display area and a peripheral area surrounding the display area, and the display area comprises a first boundary, a second boundary, a third boundary and a fourth boundary; a plurality of sub-pixels in the display area, at least one of the plurality of sub-pixels including: a light emitting element including a first electrode on the substrate base, a light emitting layer on a side of the first electrode away from the substrate base, and a second electrode on a side of the light emitting layer away from the substrate base; a plurality of first power lines located in the display region and electrically connected to the first electrodes of the plurality of sub-pixels; the first power bus is positioned in the peripheral area on one side, far away from the display area, of the first boundary and is electrically connected with the first power lines; and a second power line located in the peripheral region and electrically connected to the second electrode, the second power line including a first portion and a second portion, the first portion surrounding the second, third, and fourth boundaries of the display region, the second portion being located on a side of the first power bus line away from the display region; wherein a gap exists between the first power bus line and the second portion of the second power line, an orthographic projection of the gap on the substrate base at least partially overlaps with an orthographic projection of the second electrode on the substrate base.

In some embodiments, the second portion includes a first sub-portion and a second sub-portion, the first sub-portion and the second sub-portion being spaced apart and disposed opposite one another; a first gap exists between the first sub-portion and the first power bus bar, a second gap exists between the second sub-portion and the first power bus bar, and an orthographic projection of at least one of the first gap and the second gap on the substrate at least partially overlaps with an orthographic projection of the second electrode on the substrate.

In some embodiments, the first sub-portion is proximate to the second boundary and the second sub-portion is proximate to the fourth boundary.

In some embodiments, an orthographic projection of the first gap and the second gap on the substrate base plate is located inside an orthographic projection of the second electrode on the substrate base plate.

In some embodiments, the display substrate further comprises: the touch control electrode lines are positioned in the peripheral area, and orthographic projections of the touch control electrode lines on the substrate base plate are at least partially overlapped with orthographic projections of the gaps on the substrate base plate.

In some embodiments, the plurality of touch electrode lines include a plurality of first touch electrode lines and a plurality of second touch electrode lines, the first touch electrode lines surrounding a portion of the first boundary, the second boundary, and the third boundary of the display area; the second touch electrode line surrounds the other part of the first boundary and the fourth boundary of the display area.

In some embodiments, the first touch electrode line is a signal transmission line, and the second touch electrode line is a signal reception line.

In some embodiments, the display substrate further comprises: a flexible circuit board electrically connected to the plurality of touch electrode lines, the first power bus, and the second power line, the flexible circuit board configured to provide electrical signals to the plurality of touch electrode lines, the first power bus, and the second power line.

In some embodiments, the first power bus is to receive a first voltage signal; the second power line is used for receiving a second voltage signal; wherein the first voltage signal is higher than the second voltage signal.

In some embodiments, at least one of the plurality of sub-pixels further includes a thin film transistor and a connection electrode; the thin film transistor includes: the active layer is positioned on the substrate base plate, the grid electrode is positioned on one side of the active layer, which is far away from the substrate base plate, and the source electrode and the drain electrode are positioned on one side of the grid electrode, which is far away from the substrate base plate; the connecting electrode is positioned on one side of the thin film transistor, which is far away from the substrate base plate; wherein the source electrode or the drain electrode is electrically connected to the connection electrode, and the connection electrode is electrically connected to the first electrode.

In some embodiments, the first power bus comprises a first sub-electrode and a second sub-electrode, the first sub-electrode at least partially overlapping with an orthographic projection of the second sub-electrode on the substrate base plate; the first sub-electrode and the source electrode or the drain electrode are positioned on the same layer; the second sub-electrode and the connecting electrode are located on the same layer.

In some embodiments, the first portion comprises a first conductive portion, a second conductive portion, and a third conductive portion; the second conductive part is positioned on one side of the first conductive part far away from the substrate base plate, the third conductive part is positioned on one side of the second conductive part far away from the substrate base plate, and the first conductive part, the second conductive part and the third conductive part are electrically connected; the first conductive part is located in the same layer as the source electrode or the drain electrode. The second conductive part and the connection electrode are positioned on the same layer; the third conductive portion is located at the same layer as the first electrode.

In some embodiments, the second portion comprises a fourth conductive portion in the same layer as the source or drain and in an integrally formed structural layer as the first conductive portion.

In some embodiments, the display substrate further comprises: an inorganic protective layer covering the second power supply line, wherein at least a portion of the inorganic protective layer is between the second power supply line and the second electrode.

According to another aspect of the embodiments of the present disclosure, there is provided a display device including: a display substrate as hereinbefore described.

In the display substrate, the substrate includes a display area and a peripheral area surrounding the display area. A plurality of sub-pixels are located in the display area. At least one of the plurality of sub-pixels includes a light emitting element. The light-emitting element includes a first electrode on a base substrate, a light-emitting layer on a side of the first electrode away from the base substrate, and a second electrode on a side of the light-emitting layer away from the base substrate. The plurality of first power lines are positioned in the display area and are electrically connected with the first electrodes of the plurality of sub-pixels. The first power bus is located in the peripheral area on one side of the first boundary far away from the display area. The first power bus is electrically connected to the plurality of first power lines. The second power line is located in the peripheral area and electrically connected with the second electrode. The second power line includes a first portion and a second portion. The first portion surrounds a second boundary, a third boundary, and a fourth boundary of the display area. The second portion is located on a side of the first power bus away from the display area. A gap exists between the first power bus and the second portion of the second power line. An orthographic projection of the gap on the substrate base at least partially overlaps an orthographic projection of the second electrode of the light emitting element on the substrate base. That is, the second electrode of the light emitting element covers over the gap. The second electrode of the light-emitting element can play a role in signal shielding, so that signal interference between the signal line above the gap and the signal line below the gap can be reduced, and the display effect of the display substrate can be improved.

Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

fig. 1 is a top view illustrating a display substrate according to one embodiment of the present disclosure;

fig. 2 is an enlarged schematic view showing a partial structure within the first dashed box 141 in fig. 1;

fig. 3 is an enlarged schematic view showing a partial structure within the second dashed-line box 142 in fig. 1;

fig. 4 is a plan view illustrating the structure of fig. 3 with the touch electrode line 410 and the second electrode 222 omitted;

FIG. 5 is a top view showing the structure of FIG. 4 with the addition of a second electrode 222;

FIG. 6 is a schematic cross-sectional view showing a structure taken along line C-C' in FIG. 3;

FIG. 7 is a schematic cross-sectional view showing a structure taken along line B-B' in FIG. 2;

fig. 8 is a schematic sectional view showing a structure taken along line a-a' in fig. 1.

It should be understood that the dimensions of the various parts shown in the figures are not drawn to scale. Further, the same or similar reference numerals denote the same or similar components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments are to be construed as merely illustrative, and not as limitative, unless specifically stated otherwise.

The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In the present disclosure, when a specific device is described as being located between a first device and a second device, there may or may not be intervening devices between the specific device and the first device or the second device. When a particular device is described as being coupled to other devices, that particular device may be directly coupled to the other devices without intervening devices or may be directly coupled to the other devices with intervening devices.

All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

Fmloc (flexible Multi Layer On cell) technology is a touch technology. In the FMLOC technology, touch electrodes are fabricated on an encapsulation layer. In the FMLOC technology, in order to prevent the touch electrode line from signal crosstalk with other traces of the backplane, the touch electrode line may be shielded from signals by a common ground line. However, the inventors of the present disclosure found that, in the related art, a gap exists between the power supply voltage line and the common ground line at the corner region of the display substrate. A portion of the touch electrode line is located above the gap, and other signal lines (e.g., data lines and/or Gate Driver on Array (GOA) circuits) are also located below the gap. Because the signals in the touch electrode line, the data line and the GOA signal line can all be alternating current signals. Parasitic capacitance exists between the touch electrode line and the data line or the GOA signal line. Signal variations in one of these signal lines affect the signal in the other signal line. Therefore, signal interference may occur between the Touch electrode lines and the data lines or the GOA signal lines, resulting in poor display or poor Touch (Touch).

In view of this, embodiments of the present disclosure provide a display substrate to reduce signal interference. The structure of a display substrate according to one embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

Fig. 1 is a top view illustrating a display substrate according to one embodiment of the present disclosure. Fig. 2 is an enlarged schematic view showing a partial structure within the first dashed box 141 in fig. 1. Fig. 7 is a schematic sectional view showing a structure taken along a line B-B' in fig. 2. The display substrate is described in detail below with reference to fig. 1, 2, and 7.

As shown in fig. 1, 2 and 7, the display substrate includes a substrate 100, a plurality of sub-pixels 200, a plurality of first power lines 311, a first power bus 310 and a second power line 320.

The substrate 100 may include a display region 110 and a peripheral region 120 surrounding the display region 110. The display area 110 includes a first boundary 111, a second boundary 112, a third boundary 113, and a fourth boundary 114. Here, the first boundary 111 is opposite to the third boundary 113, and the second boundary 112 is opposite to the fourth boundary 114.

The plurality of sub-pixels 200 are located in the display area 110. At least one of the plurality of sub-pixels 200 includes a light emitting element 220, as shown in fig. 7. The light emitting element 220 may include a first electrode 221 on the substrate 100, a light emitting layer 223 on a side of the first electrode 221 away from the substrate 100, and a second electrode 222 on a side of the light emitting layer 223 away from the substrate 100. For example, the first electrode 221 is an anode, and the second electrode 222 is a cathode. For example, the second electrode 222 may receive a common ground voltage signal Vss.

It should be noted that, in the embodiments of the present disclosure, when a structure is described as being on another structure, the structure may or may not be in direct contact with the another structure. For example, when describing the first electrode 221 as being located on the substrate base 100, the first electrode 221 may be above the substrate base 100 without being in direct contact therewith.

As shown in fig. 1, the plurality of first power lines 311 are located in the display region 110. The plurality of first power lines 311 are electrically connected to the first electrodes 221 of the plurality of sub-pixels. It should be noted that when it is described that a particular device is electrically connected to other devices, the particular device may be directly electrically connected to the other devices without intervening devices, or may be directly electrically connected to the other devices with intervening devices. For example, the first power line 311 may be electrically connected to the first electrode 221 of the sub-pixel through several thin film transistors.

As shown in fig. 1, the first power bus 310 is located in the peripheral region 120 at a side of the first boundary 111 away from the display region 110. The first power bus 310 is closer to the first border 111 than the borders of the other display areas. The first power bus 310 is electrically connected to the plurality of first power lines 311.

The second power line 320 is located in the peripheral region 120 and electrically connected to the second electrode 222. The second power line 320 may include a first portion 321 and a second portion 322. The first portion 321 surrounds the second boundary 112, the third boundary 113, and the fourth boundary 114 of the display area 110. The second portion 322 is located on a side of the first power bus 310 away from the display area 110.

In some embodiments, the first power bus 310 is configured to receive a first voltage signal and the second power line 320 is configured to receive a second voltage signal. The first voltage signal is higher than the second voltage signal. For example, the first power bus is configured to receive a power supply voltage signal Vdd, and the second power line is configured to receive a common ground voltage signal Vss.

A gap 331 or 332 exists between the first power bus 310 and the second portion 322 of the second power line 320. The orthographic projection of the gap 331 or 332 on the substrate base plate 100 at least partially overlaps the orthographic projection of the second electrode 222 on the substrate base plate 100.

Thus, a display substrate according to some embodiments of the present disclosure is provided. In the display substrate, the substrate includes a display area and a peripheral area surrounding the display area. A plurality of sub-pixels are located in the display area. At least one of the plurality of sub-pixels includes a light emitting element. The light-emitting element includes a first electrode on a base substrate, a light-emitting layer on a side of the first electrode away from the base substrate, and a second electrode on a side of the light-emitting layer away from the base substrate. The first power lines are positioned in the display area and are electrically connected with the first electrodes of the sub-pixels. The first power bus is located in the peripheral area on one side of the first boundary far away from the display area. The first power bus is electrically connected to the plurality of first power lines. The second power line is located in the peripheral area and electrically connected with the second electrode. The second power line includes a first portion and a second portion. The first portion surrounds a second boundary, a third boundary, and a fourth boundary of the display area. The second portion is located on a side of the first power bus away from the display area. A gap exists between the first power bus and the second portion of the second power line. An orthographic projection of the gap on the substrate base at least partially overlaps an orthographic projection of the second electrode of the light emitting element on the substrate base. That is, the second electrode of the light emitting element covers over the gap. The second electrode of the light-emitting element can play a role in signal shielding, so that signal interference between the signal line above the gap and the signal line below the gap can be reduced, and the display effect of the display substrate can be improved.

In some embodiments, as shown in fig. 1, the second portion 322 of the second power line 320 may include a first sub-portion 3221 and a second sub-portion 3222. The first sub-portion 3221 and the second sub-portion 3222 are spaced apart and disposed opposite to each other. For example, the first sub-portion 3221 is adjacent to the second boundary 112, and the second sub-portion 3222 is adjacent to the fourth boundary 114. A first gap 331 exists between the first sub-section 3221 and the first power bus 310. A second gap 332 exists between the second sub-section 3222 and the first power bus 310. An orthogonal projection of at least one of the first gap 331 and the second gap 332 on the substrate base 100 at least partially overlaps an orthogonal projection of the second electrode 222 on the substrate base 100.

In some embodiments, the orthographic projections of the first and second gaps 331 and 332 on the substrate base plate 100 are located inside the orthographic projection of the second electrode 222 on the substrate base plate 100. Therefore, the second electrode can completely cover the two gaps, so that the signal interference between different signal lines is further reduced, and the display effect of the display substrate is improved.

In some embodiments, as shown in fig. 1, the display substrate may further include a plurality of touch electrode lines 410 located in the peripheral region 120. The orthographic projection of the touch electrode lines 410 on the substrate base plate 100 at least partially overlaps the orthographic projection of the gaps 331 or 332 on the substrate base plate 100. Therefore, in the case that the second electrode 222 of the light emitting element does not cover the gap 331 or 332, the touch electrode line 410 may interfere with other signal lines. It can be seen that the second electrode can serve as a good signal shield.

In some embodiments, as shown in fig. 1, the plurality of touch electrode lines 410 may include a plurality of first touch electrode lines 411 and a plurality of second touch electrode lines 412. The first touch electrode line 411 surrounds a portion of the first boundary 111, the second boundary 112, and the third boundary 113 of the display area 110. The second touch electrode line 412 surrounds the fourth boundary 114 and another portion of the first boundary 111 of the display region 110. For example, the first touch electrode line 411 may be a signal transmission line, and the second touch electrode line 412 may be a signal reception line; or the first touch electrode line 411 may be a receiving signal line, and the second touch electrode line 412 may be a transmitting signal line.

In some embodiments, as shown in fig. 1, the display substrate may further include a flexible circuit board 421 electrically connected to the plurality of touch electrode lines 410, the first power bus 310, and the second power line 320. The flexible circuit board 421 is configured to provide electrical signals to the plurality of touch electrode lines 410, the first power bus 310, and the second power line 320.

In some embodiments, as shown in fig. 1, the display substrate may further include a signal connection region 422 and an integrated circuit region 423. The integrated circuit region 423 is electrically connected to the display region 110 through the signal connection region 422. A plurality of data line leads are located at the signal connection region 422.

In some embodiments, as shown in fig. 1 and 2, the display substrate may further include a first touch electrode 341 and a second touch electrode 342 located in the display area. The first touch electrode 341 is electrically connected to the first touch electrode line 411, and the second touch electrode 342 is electrically connected to the second touch electrode line 412. As shown in fig. 2, the touch signals between the first touch electrode 341 and the second touch electrode 342 are different. In addition, the opening 211 of the sub-pixel is also shown in fig. 2.

Fig. 3 is an enlarged schematic view showing a partial structure within the second dashed-line box 142 in fig. 1. Fig. 4 is a plan view illustrating the structure of fig. 3 with the touch electrode line 410 and the second electrode 222 omitted. The touch electrode line 410 and the second electrode 222 are omitted from the structure of fig. 4 in order to more clearly show the gap 331 (as indicated by the dashed box in fig. 4). Fig. 5 is a top view illustrating the structure of fig. 4 with the addition of a second electrode 222.

As shown in fig. 3, 4, and 5, a gap (e.g., a first gap) 331 exists between the first power bus 310 and the second portion 322 of the second power line 320. An orthogonal projection of the first gap 331 on the substrate 100 at least partially overlaps an orthogonal projection of the second electrode 222 on the substrate 100. This may reduce signal interference between the touch electrode line 410 and other signal lines (not shown in fig. 3 to 5).

In some embodiments, the second electrode can be guaranteed to be located above the gap under consideration of the alignment accuracy and the shadow effect of the second electrode. For example, the dimensional range considering the alignment accuracy and the shadow structure may be: -80 μm to-60 μm, or 60 μm to 80 μm, so that the second electrode can be made to exceed the gap by 60 μm to 80 μm even after covering the gap. Of course, it should be understood by those skilled in the art that the range of design dimensions for the second electrode is merely exemplary and the scope of the embodiments of the present disclosure is not limited thereto.

In some embodiments, the second electrode may be a monolithic structure. In other embodiments, the second electrode may be a layer structure disposed in blocks. For example, the blocks of the second electrode may be supplied with cathode signals, respectively.

Fig. 6 is a schematic sectional view showing a structure taken along a line C-C' in fig. 3. A partial structure of the display substrate is described herein from the perspective of a cross-sectional view.

As shown in fig. 6, the display substrate may include a base substrate 100, a buffer layer 151 on the base substrate 100, and a first insulating layer 231 on a side of the buffer layer 151 away from the base substrate 100. For example, the material of the first insulating layer 231 may include silicon dioxide, silicon nitride, or the like.

As shown in fig. 6, the display substrate may further include a plurality of first signal lines 501 and a plurality of second signal lines 502 on a side of the first insulating layer 231 remote from the substrate 100. For example, the first signal line 501 and the second signal line 502 may be data signal lines. The orthographic projections of the plurality of first signal lines 501 on the substrate 100 and the orthographic projections of the plurality of second signal lines 502 on the substrate 100 are alternately arranged, and the plurality of first signal lines 501 and the plurality of second signal lines 502 are disposed at different layers. By thus arranging the signal lines 501 and 502, space can be saved.

Since the orthographic projections of a portion of the first signal lines 501 and a portion of the second signal lines 502 on the substrate at least partially overlap with the orthographic projections of the gaps 331 or 332 on the substrate, the second electrode 222 can reduce signal interference between the signal lines 501 or 502 and the touch electrode lines 410.

As shown in fig. 6, the display substrate may further include a second insulating layer 242 between the plurality of first signal lines 501 and the plurality of second signal lines 502. For example, the material of the second insulating layer 242 may include silicon dioxide, silicon nitride, or the like.

As shown in fig. 6, the display substrate may further include an interlayer dielectric layer 243 covering the plurality of second signal lines 502. The first power bus line 310 and the second power supply line 320 are located on a side of the interlayer dielectric layer 243 away from the base substrate 100.

In some embodiments, as shown in fig. 6, the first power bus 310 may include a first sub-electrode 3101 and a second sub-electrode 3102. The first sub-electrode 3101 and the second sub-electrode 3102 at least partially overlap in an orthogonal projection on the substrate 100. For example, the first sub-electrode 3101 is positioned at the same layer as a source or drain electrode (to be described later) of a thin film transistor of the sub-pixel, and the second sub-electrode 3102 is positioned at the same layer as a connection electrode (to be described later).

The term "same layer" refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film formation process and then patterning the film layer by one patterning process using the same mask. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

In some embodiments, as shown in fig. 6, the second portion 322 of the second power line 320 includes a fourth conductive portion. The fourth conductive part is positioned at the same layer with the source electrode or the drain electrode of the thin film transistor. This fourth conductive portion is an integrally formed structural layer with a first conductive portion (to be described later) of the first portion. That is, the second portion 322 of the second power line 320 shown in fig. 6 may serve as a fourth conductive portion at the same layer as the source or drain of the thin film transistor. As shown in fig. 6, there is a gap 331 (or a gap 332) between the second power line 320 and the first power bus 310.

In some embodiments, as shown in fig. 6, the display substrate may further include an inorganic protective layer 511 covering the second power line 320. At least a portion of the inorganic protective layer 511 is between the second power line 320 and the second electrode 222. For example, the material of the inorganic protective layer 511 may include an insulating material (e.g., silicon nitride, etc.).

By providing the inorganic protective layer between the second power supply line 320 and the second electrode 222, the second power supply line 320 may not be in direct contact with the second electrode 222 at the position of the peripheral region. Since the hydrophilicity of the inorganic protective layer is less than that of the second power supply line, it is possible to prevent water vapor from intruding into the second power supply line due to the fragmentation of the shadow structure of the second electrode (e.g., cathode) (here, the shadow structure of the second electrode may occur in the edge region blocked by the mask during evaporation), and thus it is possible to prevent water vapor from intruding into the display region through the water-oxygen channel formed at the side of the second power supply line. Therefore, the organic material failure of the display area caused by water vapor can be prevented, and the problem of display failure of the display substrate is further prevented.

In some embodiments, as shown in fig. 6, the display substrate may further include a first planarization layer 521 covering the inorganic protective layer 511; and a second planarizing layer 522 overlying the first power bus 310 and the first planarizing layer 521. For example, the materials of the first and second planarization layers 521 and 522 may include insulating materials (e.g., organic insulating materials such as polyimide, etc.), respectively. The display substrate may further include a pixel defining layer 523 on a side of the second planarization layer 522 remote from the substrate 100. As shown in fig. 6, the second electrode 222 covers the pixel defining layer 523, the second planarizing layer 522, the first planarizing layer 521, and the inorganic protective layer 511.

In some embodiments, as shown in fig. 6, the display substrate may further include an encapsulation layer 530 on a side of the second electrode 222 away from the substrate 100. For example, the encapsulation layer 530 may include: a first inorganic encapsulation layer 531 on a side of the second electrode 222 away from the substrate base plate 100; an organic encapsulation layer 532 on a side of the first inorganic encapsulation layer 531 remote from the substrate base plate 100; and a second inorganic encapsulation layer 533 on a side of the organic encapsulation layer 532 remote from the substrate 100. For example, the material of the first inorganic encapsulation layer 531 may include silicon nitride, etc., the material of the organic encapsulation layer 532 may include PMMA (poly (methyl methacrylate)), polymethyl methacrylate (also called acrylic), etc., and the material of the second inorganic encapsulation layer 533 may include silicon nitride, etc.

For example, the first inorganic encapsulation layer 531 may be formed on the second electrode 222 through a CVD (Chemical Vapor Deposition) process, and then the organic encapsulation layer 532 is formed on the first inorganic encapsulation layer 531 through an inkjet printing process, and then the second inorganic encapsulation layer 533 is formed on the organic encapsulation layer 532 through a CVD process.

In some embodiments, as shown in fig. 6, the display substrate may further include a barrier layer 535 on a side of the encapsulation layer 530 remote from the substrate 100. For example, the material of the barrier layer 535 may include an inorganic insulating material.

As shown in fig. 6, the plurality of touch electrode lines 410 are on a side of the blocking layer 535 away from the substrate base plate 100. In some embodiments, as shown in fig. 6, each touch electrode line 410 may include a first conductive line 541 on the blocking layer 535 and a second conductive line 542 on a side of the first conductive line 541 far from the blocking layer 535. For example, the first wire 541 may include a Ti/Al/Ti (titanium/aluminum/titanium) triple structure, and the second wire 542 may include a Ti/Al/Ti (titanium/aluminum/titanium) triple structure.

As shown in fig. 6, the display substrate may further include: a third insulating layer 536 between the first and second conductive lines 541 and 542. For example, the material of the third insulating layer 536 may include silicon nitride, silicon oxide, silicon oxynitride, or the like. In each touch electrode line 410, the first conductive line 541 may be electrically connected to the second conductive line 542 through a first conductive via (not shown in fig. 6, which may be seen in fig. 8), which may reduce the resistance of the plurality of touch electrode lines 410.

In some embodiments, as shown in fig. 6, the display substrate may further include a covering layer 550 covering the plurality of touch electrode lines 410. For example, the material of the capping layer 550 may include an organic insulating material or an inorganic insulating material.

Fig. 7 is a schematic sectional view showing a structure taken along a line B-B' in fig. 2.

As shown in fig. 7, at least one of the plurality of sub-pixels 200 may further include a thin film transistor 230 and a connection electrode 260 in addition to the light emitting element 220.

The thin film transistor 230 may include an active layer 232 on the substrate base plate 100, a gate electrode 233 on a side of the active layer 232 away from the substrate base plate 100, and a source electrode 234 and a drain electrode 235 on a side of the gate electrode 233 away from the substrate base plate 100. For example, the active layer 232 may be positioned on the buffer layer 151. The first insulating layer 231 is located between the active layer 232 and the gate electrode 233. A second insulating layer 242 and an interlayer dielectric layer 243 are positioned between the gate and the source and drain electrodes 234 and 235. The source electrode 234 is electrically connected to the active layer 232 through a second conductive via. The second conductive via passes through the interlayer dielectric layer 243, the second insulating layer 242, and the first insulating layer 231. The drain electrode 235 is electrically connected to the active layer 232 through a third conductive via. The third conductive via passes through the interlayer dielectric layer 243, the second insulating layer 242, and the first insulating layer 231.

As shown in fig. 7, the connection electrode 260 is located on the side of the thin film transistor 230 remote from the substrate 100. The source electrode 234 or the drain electrode 235 is electrically connected to the connection electrode 260. The connection electrode 260 is electrically connected to the first electrode 221. For example, the connection electrode is electrically connected to the drain electrode 235 through a fourth conductive via. The fourth conductive via passes through the first planarization layer 521 and the inorganic protective layer 511. The first electrode 221 is electrically connected to the connection electrode 260 through a fifth conductive via. The fifth conductive via passes through the second planarization layer 522.

In some embodiments, as shown in fig. 7, the display substrate may further include a capacitor between the interlayer dielectric layer 243 and the base substrate 100. The capacitor includes a first capacitive electrode 611 on a side of the first insulating layer 231 remote from the base substrate 100 and a second capacitive electrode 612 on a side of the second insulating layer 242 remote from the first capacitive electrode 611. The first capacitor electrode 611 may be at the same layer as the gate 233 and isolated from the gate 233. The second capacitor electrode 612 may be in the same layer as the second signal line 502 and may be formed through the same patterning process as the second signal line. The second insulating layer 242 covers the first capacitor electrode 611, and the interlayer dielectric layer 243 covers the second capacitor electrode 612.

Here, the same patterning process means that a film layer for forming a specific pattern is formed using the same film forming process, and then a layer structure is formed through one patterning process using the same mask plate. It should be noted that, depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses.

In some embodiments, as shown in fig. 7, the display substrate may further include a spacer layer 630 on a side of the pixel defining layer 523 away from the substrate 100. The second electrode 222 covers the spacer layer 630. For example, the material of the spacer layer 630 may include an inorganic insulating material, an organic insulating material, or the like.

In some embodiments, as shown in fig. 7, the first touch electrode 341 and the second touch electrode 342 are located on a side of the third insulating layer 536 away from the substrate base plate 100. The covering layer 550 covers the first touch electrode 341 and the second touch electrode 342.

Fig. 8 is a schematic sectional view showing a structure taken along line a-a' in fig. 1.

In some embodiments, as shown in fig. 8, the first portion 321 of the second power line 320 includes a first conductive portion 711, a second conductive portion 712, and a third conductive portion 713. The second conductive portion 712 is located on a side of the first conductive portion 711 remote from the substrate base plate 100. The third conductive portion 713 is located on a side of the second conductive portion 712 remote from the substrate base plate 100. The first conductive portion 711, the second conductive portion 712, and the third conductive portion 713 are electrically connected. The first conductive portion 711 is located at the same layer as the source electrode 234 or the drain electrode 235. The second conductive part 712 is located at the same layer as the connection electrode 260. The third conductive portion 713 is located at the same layer as the first electrode 221. The first conductive portion 711 of the first portion 321 and the fourth conductive portion of the second portion 322 of the second power supply line 320 are integrally formed structural layers. The first conductive portion 711 is the same material as the source electrode 234 or the drain electrode 235, and is formed through the same patterning process as the source electrode and the drain electrode. The second conductive part 712 is formed of the same material as the connection electrode 260 and is formed through the same patterning process as the connection electrode. The third conductive portion 713 is made of the same material as the first electrode 221 and is formed through the same patterning process as the first electrode 221. As shown in fig. 8, the third conductive portion 713 may be electrically connected to the second electrode 222.

In some embodiments, as shown in fig. 8, the display substrate may further include a first dam (dam) 810. The first bank 810 may include a portion 811 at the same layer as the second planarization layer 522 and a portion 812 at the same layer as the pixel defining layer 523. The display substrate may further include a second bank 820. The second bank 820 may include a portion 821 in the same layer as the second planarization layer 522, a portion 822 in the same layer as the pixel defining layer 523, and a portion 823 in the same layer as the spacer layer 630.

In addition, as shown in fig. 8, the first conductive line 541 may be electrically connected to the second conductive line 542 through a first conductive via.

Thus far, a display substrate according to some embodiments of the present disclosure is described in detail.

In some embodiments of the present disclosure, a display device is also provided. The display device may comprise a display substrate as described previously (e.g. the display substrate shown in fig. 1). For example, the display device may be: any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (15)

1. A display substrate, comprising:

the display device comprises a substrate and a display unit, wherein the substrate comprises a display area and a peripheral area surrounding the display area, and the display area comprises a first boundary, a second boundary, a third boundary and a fourth boundary;

a plurality of sub-pixels in the display area, at least one of the plurality of sub-pixels including: a light emitting element including a first electrode on the substrate base, a light emitting layer on a side of the first electrode away from the substrate base, and a second electrode on a side of the light emitting layer away from the substrate base;

a plurality of first power lines located in the display region and electrically connected to the first electrodes of the plurality of sub-pixels;

the first power bus is positioned in the peripheral area on one side, far away from the display area, of the first boundary and is electrically connected with the first power lines; and

a second power line located in the peripheral region and electrically connected to the second electrode, the second power line including a first portion and a second portion, the first portion surrounding the second, third, and fourth boundaries of the display region, the second portion being located on a side of the first power bus line away from the display region;

wherein a gap exists between the first power bus line and the second portion of the second power line, an orthographic projection of the gap on the substrate base at least partially overlaps with an orthographic projection of the second electrode on the substrate base.

2. The display substrate of claim 1, wherein the second portion comprises a first sub-portion and a second sub-portion, the first sub-portion and the second sub-portion being spaced apart and disposed opposite each other;

a first gap exists between the first sub-portion and the first power bus bar, a second gap exists between the second sub-portion and the first power bus bar, and an orthographic projection of at least one of the first gap and the second gap on the substrate at least partially overlaps with an orthographic projection of the second electrode on the substrate.

3. The display substrate of claim 2, wherein the first sub-portion is proximate to the second boundary and the second sub-portion is proximate to the fourth boundary.

4. The display substrate according to claim 2, wherein an orthographic projection of the first gap and the second gap on the substrate base is located inside an orthographic projection of the second electrode on the substrate base.

5. The display substrate of claim 1, further comprising:

the touch control electrode lines are positioned in the peripheral area, and orthographic projections of the touch control electrode lines on the substrate base plate are at least partially overlapped with orthographic projections of the gaps on the substrate base plate.

6. The display substrate of claim 5,

the plurality of touch electrode lines include a plurality of first touch electrode lines and a plurality of second touch electrode lines, the first touch electrode lines surrounding a portion of the first boundary, the second boundary, and the third boundary of the display area;

the second touch electrode line surrounds the other part of the first boundary and the fourth boundary of the display area.

7. The display substrate of claim 6,

the first touch electrode line is a signal sending line, and the second touch electrode line is a signal receiving line.

8. The display substrate of claim 5, further comprising:

a flexible circuit board electrically connected to the plurality of touch electrode lines, the first power bus, and the second power line, the flexible circuit board configured to provide electrical signals to the plurality of touch electrode lines, the first power bus, and the second power line.

9. The display substrate according to any one of claims 1 to 8,

the first power bus is used for receiving a first voltage signal;

the second power line is used for receiving a second voltage signal;

wherein the first voltage signal is higher than the second voltage signal.

10. The display substrate of claim 9, wherein at least one of the plurality of sub-pixels further comprises a thin film transistor and a connection electrode;

the thin film transistor includes: the active layer is positioned on the substrate base plate, the grid electrode is positioned on one side of the active layer, which is far away from the substrate base plate, and the source electrode and the drain electrode are positioned on one side of the grid electrode, which is far away from the substrate base plate;

the connecting electrode is positioned on one side of the thin film transistor, which is far away from the substrate base plate;

wherein the source electrode or the drain electrode is electrically connected to the connection electrode, and the connection electrode is electrically connected to the first electrode.

11. The display substrate of claim 10, wherein the first power bus comprises a first sub-electrode and a second sub-electrode, and an orthographic projection of the first sub-electrode and the second sub-electrode on the substrate at least partially overlaps;

the first sub-electrode and the source electrode or the drain electrode are positioned on the same layer;

the second sub-electrode and the connecting electrode are located on the same layer.

12. The display substrate according to claim 10, wherein the first portion comprises a first conductive portion, a second conductive portion, and a third conductive portion;

the second conductive part is positioned on one side of the first conductive part far away from the substrate base plate, the third conductive part is positioned on one side of the second conductive part far away from the substrate base plate, and the first conductive part, the second conductive part and the third conductive part are electrically connected;

the first conductive part and the source electrode or the drain electrode are positioned on the same layer;

the second conductive part and the connection electrode are positioned on the same layer;

the third conductive portion is located at the same layer as the first electrode.

13. The display substrate according to claim 12, wherein the second portion comprises a fourth conductive portion in the same layer as the source electrode or the drain electrode and integrally formed with the first conductive portion.

14. The display substrate of claim 1, further comprising:

an inorganic protective layer covering the second power supply line,

wherein at least a portion of the inorganic protective layer is between the second power supply line and the second electrode.

15. A display device, comprising: a display substrate according to any one of claims 1 to 14.

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