CN210405820U

CN210405820U - Circuit board

Info

Publication number: CN210405820U
Application number: CN201822190507.4U
Authority: CN
Inventors: 黄立湘; 缪桦
Original assignee: Shennan Circuit Co Ltd
Current assignee: Shennan Circuit Co Ltd
Priority date: 2018-12-21
Filing date: 2018-12-21
Publication date: 2020-04-24
Anticipated expiration: 2028-12-21

Abstract

The application provides a circuit board. The circuit board includes: a substrate; a boss disposed on the substrate; the first bare chip comprises a first top surface and a first bottom surface which are oppositely arranged, a first connecting terminal is arranged on the first top surface, and the first bottom surface is arranged on the boss; the insulating layer is arranged on the first top surface of the first bare chip, and a first conductive hole is arranged at a position corresponding to the first connecting terminal; the first leading-out terminal is arranged in the first conductive hole and electrically connected with the first connecting terminal so as to fan out the first connecting terminal. Therefore, the conductive hole can be formed in a laser punching mode more accurate than mechanical punching, so that the connection terminal of the bare core can be accurately fanned out, and the accuracy of chip packaging in the circuit board is improved.

Description

Circuit board

Technical Field

The application relates to the technical field of circuit boards, in particular to a circuit board.

Background

With the development of high-frequency and high-speed requirements of electronic products, chip packaging of a traditional circuit board generally adopts wire bonding packaging and flip packaging modes in manufacturing, and the traditional packaging modes are difficult to meet the requirements of high-frequency and high-speed signal transmission, so that more and more chip packaging of the circuit board adopts a substrate embedded or wafer level fan-out process to realize bare chip packaging, and the packaging interconnection size is reduced to realize the requirements of high-frequency and high-speed transmission of chips on signal integrity.

However, in the manufacturing process of the circuit board in the prior art, the board body of the package is too thick, so that the connection terminal of the chip can only be fanned out in a mechanical rotary hole mode. The accuracy of fan-out of the connecting terminal is influenced due to the reasons of large vibration and the like during mechanical hole rotation, so that the accuracy of chip packaging is influenced.

Disclosure of Invention

The technical problem that this application mainly solved provides a circuit board, can improve the accuracy of chip package in the circuit board.

In order to solve the technical problem, the application adopts a technical scheme that: provided is a circuit board including: a substrate; a boss disposed on the substrate; the first bare chip comprises a first top surface and a first bottom surface which are oppositely arranged, a first connecting terminal is arranged on the first top surface, and the first bottom surface is arranged on the boss; the insulating layer is arranged on the first top surface of the first bare chip, and a first conductive hole is arranged at a position corresponding to the first connecting terminal; and the first leading-out terminal is arranged in the first conductive hole and is electrically connected with the first connecting terminal so as to fan out the first connecting terminal.

This application sets up the boss on the basement, sets up the bare core on this boss to can raise the position of bare core, when seting up the electrically conductive hole on the insulating layer of its top surface, the degree of depth of electrically conductive hole can reduce. Therefore, the conductive hole can be formed in a laser punching mode more accurate than mechanical punching, so that the connection terminal of the bare core can be accurately fanned out, and the accuracy of chip packaging in the circuit board is improved.

Drawings

Fig. 1 is a schematic flow chart of a method for manufacturing a circuit board according to an embodiment of the present disclosure;

fig. 2 is a schematic flow chart of another circuit board manufacturing method according to an embodiment of the present disclosure;

FIGS. 3-9 are schematic process flow diagrams of methods of manufacturing circuit boards corresponding to those of FIG. 2;

fig. 10 is a schematic flow chart of another circuit board manufacturing method according to an embodiment of the present disclosure;

fig. 11-15 are schematic process flow diagrams of methods of manufacturing circuit boards corresponding to fig. 10.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the embodiments described below are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In order to make the technical solutions provided by the embodiments of the present application clearer, the following embodiments describe the technical solutions of the present application in detail with reference to the accompanying drawings.

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for manufacturing a circuit board according to an embodiment of the present disclosure. As shown in fig. 1, the manufacturing method of the present embodiment includes the steps of:

step S10: a substrate is provided.

Step S11: at least one boss is disposed on the substrate.

Step S12: providing a first bare chip, wherein the first bare chip comprises a first top surface and a first bottom surface which are oppositely arranged, a first connecting terminal is arranged on the first top surface, and the first bottom surface is arranged on the boss.

Step S13: an insulating layer is arranged on the first top surface of the first bare chip, and a first conductive hole is arranged at a position corresponding to the first connecting terminal.

Step S14: and a first leading-out terminal is arranged in the first conductive hole and is electrically connected with the first connecting terminal so as to fan out the first connecting terminal.

Therefore, according to the invention, the boss is arranged on the substrate, the first bare chip is arranged on the boss, so that the position of the first bare chip can be raised, and when the first conductive hole is formed in the insulating layer of the first top surface, the depth of the first conductive hole can be reduced. Therefore, the first conductive hole can be formed in a laser punching mode more accurate than mechanical punching, so that the fan-out of the first connecting terminal of the first bare chip can be accurate, and the accuracy of chip packaging in the circuit board is improved.

Referring to fig. 2, fig. 2 is a schematic flow chart of another circuit board manufacturing method according to an embodiment of the present disclosure, and fig. 3 to 9 are schematic process flow diagrams corresponding to the manufacturing method shown in fig. 2. The manufacturing method of the present embodiment includes the steps of:

step S20: as shown in fig. 3, a substrate 100 is provided.

The substrate 100 may be made of an insulating material.

Step S21: at least one boss 200 is provided on the substrate 100.

As shown in fig. 4, the bump 200 may be plated on the substrate 100. The boss 200 may be made of conductive material, such as copper, silver, iron, etc.

The number of the bosses 200 is equal to and corresponds to the number of the connection terminals on the bottom surface of the die. As shown in fig. 4, the two bumps 200 are two

bumps

201 and 202, which correspond to the connection terminals on the bottom surface of the die, as described below.

The bumps 200 serve to raise the height of the die so that the top surface of the die is closer to the outer surface of the insulating layer, thereby facilitating the placement of the conductive vias on the top surface of the die. Based on this, the height of the mesa 200 is determined according to the thickness of the die placed thereon.

Step S22: a bare chip 300 is provided, the bare chip 300 includes a top surface 301 and a bottom surface 302 oppositely arranged, the top surface 301 is provided with

first connection terminals

303 and 304, the bottom surface 302 is provided with

second connection terminals

305 and 306, the bottom surface 302 is arranged on the boss 200, and the

second connection terminals

305 and 306 are electrically connected with the boss 200.

As shown in fig. 5, the bottom surface 302 of the bare chip 300 is provided with two

second connection terminals

305 and 306, which correspond to one of the bumps 200, respectively. Specifically, the second connection terminal 305 corresponds to the boss 201, and the second connection terminal 306 corresponds to the boss 202.

The electrical connection of the

second connection terminals

305 and 306 to the

lands

201 and 202, respectively, is particularly achieved by conductive layers provided therebetween. Specifically,

conductive layers

203 and 204 are provided on the

lands

201 and 202, respectively, and when the die 300 is placed on the land 200, the second connection terminal 305 is in contact with the conductive layer 203, fixed and electrically connected by the conductive layer 203 and the land 201; the second connection terminal 306 is in contact with the conductive layer 204, and is fixed and electrically connected through the conductive layer 204 and the land 202.

The

conductive layers

203 and 204 may be metal paste with which the

second connection terminals

305 and 306 are in contact when they are liquid, and may fix the

second connection terminals

305 and 306 to the corresponding lands 200 when they are changed from a liquid state to a solid state.

It should be understood that the number of the conductive layers and the number of the second connection terminals are also the same and correspond one to one.

Step S23: an insulating layer 600 is disposed on the top surface 301 of the die 300, and first conductive vias 601 are disposed at positions corresponding to the

first connection terminals

303 and 304.

As shown in fig. 6, the process of disposing the insulating layer 600 is specifically as follows:

first, a frame 400 is disposed on the substrate 100, and a through-slot 401 is formed on the frame 400. The through-slots 401 leak the substrate 100 out at a position corresponding to the position where the bare die 300 is disposed.

The width of the through-slots 401 may be greater than or equal to the width of the die 300. The present embodiment will be described in detail by taking an example in which the width of the through-groove 401 is greater than the width of the bare chip 300 placed therein.

Then, a dielectric layer 500 is disposed on the surface of the frame 400, and the dielectric layer 500 is pressed so as to cover the surface of the frame 400 and fill the gap between the die 300 and the through-groove 401.

The dielectric layer 500 may be a sheet material composed of a semi-cured resin material, such as epoxy resin or bismaleimide-triazine resin, and an inorganic filler, and the thickness of the material may be selected to be 20 micrometers to 100um as required. The dielectric layer 500 may also be a photosensitive sheet material that is cured by heating. Of course, the dielectric layer 500 may also be a sheet material of a non-photosensitive type.

Further, the dielectric layer 500 is cured. Specifically, the dielectric layer 500 is pressed onto the surface of the frame 400 at high temperature and high pressure and completely cured, thereby covering the surface of the frame 400 and the top surface 301 of the bare chip 300. The dielectric layer 500 may also liquefy and flow between the die 300 and the through-vias 401 at high temperature and high pressure.

In this embodiment, the material of the dielectric layer 500 may be the same as that of the frame 300, so that the cured dielectric layer 500 and the frame 300 form the insulating layer 600 of an integrated structure.

The above is a process of providing the insulating layer 600 on the top surface 301 of the die 300. After the insulating layer 600 is provided, first conductive holes 601 may be further provided at positions corresponding to the

first connection terminals

303 and 304, respectively.

Since the die 300 is raised by the mesa 200. The top surface 301 is thus at a smaller distance from the outer surface of the insulating layer 600. The first conductive hole 601 can be arranged in a laser hole-turning mode with high precision, so that the accuracy of the first conductive hole 601 is improved. The aperture size may be set according to the size of the first connection terminal 303, and may be set to about 30 to 100 micrometers, for example.

Step S24: the substrate 100 is provided with second conductive holes 101 at positions corresponding to the lands 200.

As shown in fig. 7, the number of the second conductive holes 101 is the same as the number of the lands 200. The second conductive via 101 may be formed in the same manner as the first conductive via 601, and is not described herein again.

Step S25: the first lead-out terminal 602 is disposed in the first conductive hole 601 and electrically connected to the

first connection terminals

303 and 304 to fan out the

first connection terminals

303 and 304.

As shown in fig. 8, the number of first lead-out terminals 602 is the same as the number of first connection terminals and corresponds to one. The first lead out terminal 602 extends further out of the insulating layer 600, having fanned out the

first connection terminals

303 and 304 as pads (pins) of the die 300.

Step S26: the second lead-out terminal 102 is disposed in the second conductive hole 101 and electrically connected to the boss 200 such that the

second connection terminals

305 and 306 fan out through the boss 200 and the second lead-out terminal 102.

As shown in fig. 9, the number of the second lead-out terminals 102 is the same as the number of the bosses 200 and corresponds one to one. The second outgoing terminal 102 extends further out of the substrate 100, having fanned out the

second connection terminals

305 and 306 as pads (pins) of the die 300.

Therefore, in the present embodiment, the bumps 200 are disposed on the substrate 100, and the bare chip 300 is disposed on the bumps 200, so that the position of the bare chip 300 can be raised, and when the first conductive holes 601 are formed in the insulating layer 600 on the top surface 301, the depth of the first conductive holes 601 can be reduced. Therefore, the first conductive hole 601 can be opened by a laser drilling method more precisely than a mechanical drilling method, so that the

first connection terminals

303 and 304 of the bare chip 300 can be fanned out accurately, and the accuracy of chip packaging in a circuit board is improved.

Further, a second lead-out terminal may also be provided on the substrate 100 such that the

second connection terminals

305 and 306 fan out through the boss 200 and the second lead-out terminal 102.

In other embodiments, the above steps S21 and S26 may be adjusted according to actual conditions. The setting step of the frame 400 in step S23 is performed before step S21, for example. After the insulating layer is formed in step S23, step S24 may be performed, and step S23 of forming the first conductive via may be performed, and step S25 and step S26 may be performed simultaneously. Similarly, the above process sequence can be adjusted according to the actual situation.

The above-mentioned bump in the disclosed circuit board is for facilitating fan-out of the connection terminal of the die, and in other embodiments, the bump may also facilitate simultaneous manufacturing of a plurality of dies with different thicknesses, wherein the die with smaller thickness may be the die 300 described above. In particular, in the following embodiments, if the same features as those of the previous embodiments are provided, the same reference numerals are given to the same features as those of the previous embodiments. Please refer to fig. 10.

Fig. 10 is a schematic flowchart of a manufacturing method of a circuit board according to an embodiment of the present application. The manufacturing method of the present embodiment includes the steps of:

step S30: a substrate 100 is provided. In particular, the substrate 100 shown in fig. 3.

Step S31: at least one boss 200 is provided on the substrate 100.

The arrangement of the boss 200 can be as described above and shown in fig. 4 and will not be described herein.

Step S32: a first die 300 and a second die 700 are provided. The first die 300 includes a first top surface 301 and a first bottom surface 302 arranged oppositely, the first top surface 301 is provided with

first connection terminals

303 and 304, and the first bottom surface 302 is provided with

second connection terminals

305 and 306. The second die 700 includes a second top surface 701 and a second bottom surface 702 which are oppositely arranged, the second top surface 701 is provided with

third connection terminals

703 and 704, and the second bottom surface 702 is provided with

fourth connection terminals

705 and 706. The first die 300 is disposed on the boss 200, the second die 700 is disposed on the substrate 100, and the first top surface 301 of the first die 300 and the second top surface 701 of the second die 700 are flush.

The number of the

first connection terminals

303 and 304 of the first die 300 is two, the number of the

second connection terminals

305 and 306 is also two, and the number of the bumps 200 is the same as that of the second connection terminals, and the bumps and the second connection terminals are in one-to-one correspondence. As shown in fig. 11, the bump 200 includes two, respectively, bumps 201 and 202, which correspond to the

second connection terminals

305 and 306, respectively.

Further, the

second connection terminals

305 and 306 are electrically connected to the corresponding

lands

201 and 202 through the

conductive layers

203 and 204, respectively.

Conductive layers

203 and 204 are as described above and will not be described in detail herein.

The second die 700 is disposed on the substrate 100, and the

fourth connection terminals

705 and 706 on the second bottom surface 702 thereof are in contact with and fixed relative to the substrate 100.

The height of the second die 700 is greater than the height of the first die 300. Further, the height of the second die 700 is equal to the sum of the height of the first die 300 and the height of the land 200. Thus, in a configuration in which the first die 300 is disposed on the boss 200 and the second die 700 is disposed on the substrate 100, the first top surface 301 of the first die 300 and the second top surface 701 of the second die 700 are flush.

Step S33: an insulating layer 600 is disposed on the first top surface 301 of the first die 300 and the second top surface 701 of the second die 700, and first conductive holes 601 are disposed at positions corresponding to the

first connection terminals

303 and 304, and third conductive holes 603 are disposed at positions corresponding to the

third connection terminals

703 and 704.

As shown in fig. 12, the process of disposing the insulating layer 600 is specifically as follows:

first, a frame 400 is disposed on the substrate 100, and through

slots

401 and 402 are formed in the frame 400. The through

slots

401 and 402 leak the substrate 100. The positions of the through grooves 401 correspond to the positions of the first die 300, and the positions of the through grooves 402 correspond to the positions of the second die 700.

The width of the through-slot 401 may be greater than or equal to the width of the first die 300. Likewise, the width of the through-slots 402 can be greater than or equal to the width of the second die 700. The present embodiment is described in detail by taking an example in which the width of the through-groove 401 is greater than the width of the first die 300 placed therein, and the width of the through-groove 402 is greater than the width of the second die 700.

A dielectric layer 500 is then disposed on the surface of the frame 400, and the dielectric layer 500 is pressed so that it covers the surface of the frame 400 and fills the gap between the first die 300 and the through-slot 401 and the gap between the second die 700 and the through-slot 402.

Further, the dielectric layer 500 is cured. Specifically, the dielectric layer 500 is pressed onto the surface of the frame 400 at high temperature and high pressure and completely cured, thereby covering the surface of the frame 400, the top surface 301 of the first die 300, and the top surface 701 of the second die 700. The dielectric layer 500 can also liquefy and flow at high temperature and high pressure into between the first die 300 and the through-trench 401 and between the second die 700 and the through-trench 402.

The above is a process of providing the insulating layer 600 on the first top surface 301 of the first die 300 and the second top surface 701 of the second die 700. After the insulating layer 600 is provided, first conductive holes 601 may be further provided at positions corresponding to the

first connection terminals

303 and 304, respectively, and third conductive holes 603 may be further provided at positions corresponding to the

third connection terminals

703 and 704, respectively.

Since the first die 300 is lifted by the stage 200. The first top surface 301 is located a small distance from the outer surface of the insulating layer 600. The first conductive hole 601 can be arranged in a laser hole-turning mode with high precision, so that the accuracy of the first conductive hole 601 is improved. The aperture size may be set according to the size of the first connection terminal 303, and may be set to about 30 to 100 micrometers, for example

In addition, since the first top surface 301 of the first die 300 and the second top surface 701 of the second die 700 are flush with each other, when the insulating layer 600 is pressed, the first die 300 and the second die 700 are stressed to the same degree, which is beneficial to pressing the insulating layer 600. Therefore, the packaging of the bare cores with different thicknesses can be carried out at one time, and the packaging efficiency is improved.

Step S34: the substrate 100 is provided with the second conductive holes 101 at positions corresponding to the lands 200, and the fourth conductive holes 103 at positions corresponding to the

fourth connection terminals

705 and 705.

As shown in fig. 13, the number of the second conductive holes 101 is the same as the number of the bosses 200 and corresponds to one. The second conductive hole 101 exposes the boss 200.

The number of the fourth conductive holes 103 is the same as and corresponds to the number of the

fourth connection terminals

705 and 705. The fourth conductive via 103 exposes the

fourth connection terminals

705 and 705.

Step S35: as shown in fig. 14, a first lead-out terminal 602 is provided in the first conductive hole 601 and electrically connected to the

first connection terminals

303 and 304 to fan out the

first connection terminals

303 and 304, and a third lead-out terminal 604 is provided in the third conductive hole 603 and electrically connected to the

third connection terminals

703 and 704 to fan out the

third connection terminals

703 and 704.

Step S36: as shown in fig. 15, the second lead-out terminal 102 is disposed in the second conductive hole 101 and electrically connected to the boss 200 such that the

second connection terminals

305 and 306 fan out through the boss 200 and the second lead-out terminal 102, and the fourth lead-out terminal 104 is disposed in the fourth conductive hole 103 and connected to the

fourth connection terminals

705 and 706 to fan out the

fourth connection terminals

705 and 706.

Therefore, in the present embodiment, the first die 300 with a smaller height is lifted by the bump 200, which not only facilitates the packaging of the first die 300, but also facilitates the packaging of the first die 300 with the second die 700 with a larger height.

In other embodiments, more dies of different thicknesses may be placed on the same substrate 100, as long as their top surfaces are kept flush by the lands 200.

In other embodiments, the second die 700 may also have the

third connection terminals

703 and 704 only on the second top surface 701. It is only necessary to fan out the

third connection terminals

703 and 704 of the second top surface 701.

The application also provides a corresponding circuit board for the manufacturing method.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a circuit board according to an embodiment of the present disclosure. It is noted that the circuit board of the present embodiment can be formed by the manufacturing method shown in fig. 2. As shown in fig. 9, the circuit board of the present embodiment includes a substrate 100, a bump 200, a die 300, an insulating layer 600, a first lead-out terminal 602, and a second lead-out terminal 102.

Wherein the boss 200 is disposed on the substrate 100. The boss 200 has conductivity.

Die 300 includes oppositely disposed top and

bottom surfaces

301 and 302. The top surface 301 is provided with

first connection terminals

303 and 304, and the bottom surface 302 is provided on the boss 200. Further, the

second connection terminals

305 and 306 on the bottom surface 302 are electrically connected to the boss 200.

Specifically, the number of the bosses 200 is the same as the number of the

second connection terminals

305 and 306, and corresponds to one. As shown in fig. 9, the number of the bosses is two, that is, a boss 201 and a boss 202. The second connection terminal 305 is electrically connected to the boss 201, and the second connection terminal 306 is electrically connected to the boss 202.

The electrical connection of the

second connection terminals

305 and 306 to the

lands

conductive layers

203 and 204 are provided on the

lands

It should be understood that the number of the conductive layers and the number of the second connection terminals are also the same and correspond one to one. The material of the conductive layer can be as described above, and is not described herein again.

The insulating layer 600 is disposed on the top surface 301 of the die 300, and is provided with first conductive vias 602 at positions corresponding to the

first connection terminals

303 and 304. It is understood that the number of the first conductive holes 602 and the number of the first connection terminals are equal and correspond one to one.

Since the die 300 is disposed on the bump 200, i.e., the bump 200 lifts the die 300, the distance between the top surface 301 of the die 300 and the outer surface of the insulating layer 600 is reduced, thereby facilitating the formation of the first conductive via 602. For example, the first conductive hole 601 may be formed by laser drilling with high precision.

The first lead-out terminal 602 is disposed in the first conductive hole 601 and electrically connected to the

first connection terminals

303 and 304 to fan out the

first connection terminals

303 and 304. It is to be understood that the number of the first lead-out terminals 602 is the same as and corresponds one to the number of the

first connection terminals

303 and 304.

The substrate 100 is provided with second conductive holes 101 at positions corresponding to the lands 200. The second conductive hole 101 exposes the boss 200. The second lead-out terminal 102 is disposed in the second conductive hole 101 and electrically connected to the

second connection terminals

305 and 306 to fan out the

second connection terminals

305 and 306.

It is to be understood that the number of the second conductive holes 101 and the second lead-out terminals 102 is the same as and corresponds to the number of the

second connection terminals

305 and 306.

The above-mentioned bump 200 in the disclosed circuit board is for facilitating fan-out of the connection terminal of the die, and in other embodiments, the bump 200 may also facilitate simultaneous manufacturing of a plurality of dies with different thicknesses, wherein the die with smaller thickness may be the die 300 described above. In particular, in the following embodiments, if the same features as those of the previous embodiments are provided, the same reference numerals are given to the same features as those of the previous embodiments. Please refer to fig. 15.

Fig. 15 is a schematic structural diagram of another circuit board provided in the embodiment of the present application. It is noted that the circuit board of the present embodiment can be formed by the manufacturing method shown in fig. 10.

As shown in fig. 15, the circuit board of the present embodiment includes a substrate 100, a stage 200, a first die 300, a second die 700, an insulating layer 600, first

outgoing terminals

602 and 604, and second

outgoing terminals

102 and 104.

The first die 300 includes a first top surface 301 and a first bottom surface 302 disposed opposite one another. The first top surface 301 is provided with

first connection terminals

303 and 304, and the first bottom surface 302 is provided on the boss 200. Further, the

second connection terminals

305 and 306 on the first bottom surface 302 are electrically connected to the stage 200.

Specifically, the number of the bosses 200 is the same as the number of the

second connection terminals

305 and 306, and corresponds to one. As shown in fig. 15, the number of bosses is two, that is, a boss 201 and a boss 202. The second connection terminal 305 is electrically connected to the boss 201, and the second connection terminal 306 is electrically connected to the boss 202.

The electrical connection of the

second connection terminals

305 and 306 to the

lands

201 and 202, respectively, is particularly achieved by conductive layers provided therebetween. The details can be as described above, and are not described herein.

The second die 700 includes a second top surface 701 and a second bottom surface 702 that are oppositely disposed.

Third connection terminals

703 and 704 are provided on the second top surface 701, and

connection terminals

705 and 706 are provided on the second bottom surface 702.

The second die 700 is disposed on the substrate 100, and the

fourth connection terminals

705 and 706 of the second bottom surface 702 are in contact with and fixed to the substrate 100.

The height of the second die 700 is greater than the height of the first die 300. Further, the height of the second die 700 is equal to the sum of the height of the first die 300 and the height of the boss 200, such that the first top surface of the first die 300 and the second top surface 701 of the second die 700 are flush.

An insulating layer 600 is disposed on the top surface 301 of the first die 300 and the second top surface 701 of the second die 700. Further, the insulating layer 600 is provided with first conductive holes 602 at positions corresponding to the

first connection terminals

303 and 304. The insulating layer 600 is provided with third conductive holes 603 at positions corresponding to the

third connection terminals

703 and 704. It is understood that the number of the first conductive holes 602 and the number of the first connection terminals are equal and correspond one to one. The number of the third conductive holes 603 is equal to the number of the third connection terminals and corresponds to one another.

Further, the first top surface of the first die 300 and the second top surface 701 of the second die 700 are flush. Therefore, when the insulating layer 600 is laminated, the first die 300 and the second die 700 are stressed to the same degree, which is beneficial to laminating the insulating layer 600. Therefore, the packaging of the bare cores with different thicknesses can be carried out at one time, and the packaging efficiency is improved.

first connection terminals

303 and 304 to fan out the

first connection terminals

303 and 304.

The third lead-out terminal 604 is disposed in the third conductive hole 603, and is electrically connected to the

third connection terminals

703 and 704 to fan out the

third connection terminals

703 and 704. It is to be understood that the number of the third lead-out terminals 604 is the same as and corresponds to one with the number of the

third connection terminals

703 and 704.

The substrate 100 is provided with second conductive holes 101 at positions corresponding to the lands 200. The second conductive hole 101 exposes the boss 200. The second lead-out terminal 102 is disposed in the second conductive hole 101 and electrically connected to the boss 200 such that the

second connection terminals

305 and 306 fan out through the boss 200 and the second lead-out terminal 102.

second connection terminals

305 and 306.

Further, the substrate is provided with fourth conductive holes 103 at positions corresponding to the

fourth connection terminals

705 and 706.

The fourth conductive via 103 exposes the

fourth connection terminals

705 and 706. The fourth lead-out terminal 104 is disposed in the fourth conductive hole 103 and electrically connected to the

fourth connection terminals

705 and 706 to fan out the

fourth connection terminals

705 and 706.

It is to be understood that the number of the fourth conductive holes 103 and the fourth lead-out terminals 104 is the same as and corresponds to the number of the

fourth connection terminals

705 and 706.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A circuit board, comprising:

a substrate;

a boss disposed on the substrate;

the first bare chip comprises a first top surface and a first bottom surface which are oppositely arranged, a first connecting terminal is arranged on the first top surface, and the first bottom surface is arranged on the boss;

the insulating layer is arranged on the first top surface of the first bare chip, and a first conductive hole is arranged at a position corresponding to the first connecting terminal;

and the first leading-out terminal is arranged in the first conductive hole and is electrically connected with the first connecting terminal so as to fan out the first connecting terminal.

2. The circuit board according to claim 1, wherein a second connection terminal is provided on the first bottom surface, and the land has conductivity;

the first bottom surface is arranged on the boss, and the second connection terminal is electrically connected with the boss;

the substrate is provided with a second conductive hole at a position corresponding to the boss;

the circuit board further includes:

and the second leading-out terminal is arranged in the second conductive hole and is electrically connected with the boss, so that the second connecting terminal can fan out through the boss and the second leading-out terminal.

3. The circuit board according to claim 2, wherein the number of the second connection terminals is the same as the number of the bosses, and corresponds to one another.

4. The circuit board according to claim 2, wherein a conductive layer is provided between the second connection terminal and the boss to relatively fix the second connection terminal and the boss.

5. The circuit board of claim 1, further comprising:

a second die disposed on the substrate, the second die having a height greater than a height of the first die.

6. The circuit board of claim 5, wherein a height of the second die is equal to a sum of a height of the first die and a height of the mesa.

7. The circuit board of claim 5, wherein the second die comprises a second bottom surface and a second top surface, the second top surface having a third connection terminal disposed thereon;

the insulating layer further covers the second top surface, and a third conductive hole is arranged at a position corresponding to the third connecting terminal;

the circuit board further includes:

and the third leading-out terminal is arranged in the third conductive hole and is electrically connected with the third connecting terminal so as to fan out the third connecting terminal.

8. The circuit board according to claim 7, wherein a fourth connection terminal is provided on the second bottom surface;

the fourth connecting terminal is arranged on a substrate, and a fourth conductive hole is formed in the position, corresponding to the fourth connecting terminal, of the substrate;

the circuit board further includes:

and the fourth leading-out terminal is arranged in the fourth conductive hole and electrically connected with the fourth connecting terminal so as to fan out the fourth connecting terminal.