CN210405267U

CN210405267U - Level conversion system

Info

Publication number: CN210405267U
Application number: CN201920469537.0U
Authority: CN
Inventors: 黄兴浩
Original assignee: Guangzhou Gaoke Communications Technology Co ltd
Current assignee: Guangzhou Gaoke Communications Technology Co ltd
Priority date: 2019-04-09
Filing date: 2019-04-09
Publication date: 2020-04-24
Anticipated expiration: 2029-04-09

Abstract

The utility model discloses a level conversion system, including 1.8V signal module and 3.3V signal module, still include level conversion circuit, level conversion circuit includes voltage stabilizing circuit and area lock control converting circuit, voltage stabilizing circuit's input and the 3.3V voltage end electric connection of area lock control converting circuit, voltage stabilizing circuit's output and the 1.8V voltage end electric connection of area lock control converting circuit, 1.8V signal module is through area lock control converting circuit and 3.3V signal module electric connection. The level conversion system carries out level conversion through the level conversion circuit, can use normal power supply voltage, can ensure the service life of the chip, has high-resistance output, and can be used in a normal cascade mode when in parallel connection; the frequency of the device is as high as 100M, and most high-speed use scenes can be met.

Description

Level conversion system

Technical Field

The utility model relates to an electronic circuit technical field especially relates to a level shift system.

Background

The current level conversion circuit has three implementation modes: the first method adopts a wide-range input chip and performs conversion by means of the bearing capacity of the chip, and the design life of the method is limited; the second is to use a driving chip, such as 16245, for conversion, which has the defects that high-resistance output cannot be realized, and the method cannot be used in a parallel use scene; and thirdly, level conversion is realized by using an up-down pull resistor, and the method is limited in use in a high-speed signal scene, so that poor signal quality is caused.

SUMMERY OF THE UTILITY MODEL

In order to overcome the defects of the prior art, the utility model aims to provide a level conversion system which can meet the use scenes of most high-speed communication.

The purpose of the utility model is realized by adopting the following technical scheme:

the level conversion system comprises a 1.8V signal module, a 3.3V signal module and a level conversion circuit, wherein the level conversion circuit comprises a voltage stabilizing circuit and a lock control conversion circuit, the input end of the voltage stabilizing circuit is electrically connected with the 3.3V voltage end of the lock control conversion circuit, the output end of the voltage stabilizing circuit is electrically connected with the 1.8V voltage end of the lock control conversion circuit, and the 1.8V signal module is electrically connected with the 3.3V signal module through the lock control conversion circuit.

Further, the voltage stabilizing circuit comprises a voltage stabilizing chip, a first filtering module, a second filtering module and a voltage dividing module; the voltage division module comprises a resistor R1 and a resistor R2, and the voltage stabilizing chip comprises an input end, an output end and a feedback end; the 3.3V voltage end of the band lock control conversion circuit is connected with one end of the first filtering module and the input end of the voltage stabilizing chip, the other end of the first filtering module is grounded, the 1.8V voltage end of the band lock control conversion circuit is connected with the output end of the voltage stabilizing chip and one end of the second filtering module, the other end of the second filtering module is grounded, the feedback end of the voltage stabilizing chip is grounded through a resistor R1, and the feedback end of the voltage stabilizing chip is connected with the output end of the voltage stabilizing chip through a resistor R2.

Further, the first filtering module comprises a capacitor C1 and a capacitor C2, and the capacitor C1 is connected with the capacitor C2 in parallel; the second filtering module comprises a capacitor C3 and a capacitor C4, and the capacitor C3 is connected with the capacitor C4 in parallel.

Further, the capacitance value of the capacitor C1 is 0.1 μ F, the capacitance value of the capacitor C2 is 0.4 μ F, the resistance value of the resistor R1 is 97.6 Ω, and the resistance value of the resistor R2 is 43 Ω.

Further, the model of the voltage stabilizing chip is ZTP1117 SA.

Further, the conversion circuit with lock control is a conversion control chip, and the conversion control chip includes end positions electrically connected to the 1.8V signal module, end positions electrically connected to the 3.3V signal module, a 1.8V voltage terminal, a 3.3V voltage terminal, and a ground terminal.

Further, the 1.8V signal system is connected to a 1.8V voltage end of the conversion control chip through a pull-up resistor, and a resistance value of the pull-up resistor is 472 Ω.

Further, the conversion control chip is in a 74HC125AD model.

Further, the 1.8V signal module is an LTE module, and the model of the LTE module is EC 25.

Furthermore, the 3.3V signal system comprises an ARM processor and an SLIC module, and the conversion control chip is respectively connected with corresponding end bits of the ARM processor and the SLIC module; the model of the ARM processor is MT7620A, and the model of a chip in the SLIC module is SI 3217X.

Compared with the prior art, the beneficial effects of the utility model reside in that:

the level conversion system carries out level conversion through the level conversion circuit, can use normal power supply voltage, can ensure the service life of the chip, has high-resistance output, and can be used in a normal cascade mode when in parallel connection; the frequency of the device is as high as 100M, and most high-speed use scenes can be met.

Drawings

Fig. 1 is a circuit schematic diagram of the switching circuit with lock control of the present invention;

fig. 2 is a schematic connection diagram of the matching circuit of the present invention;

FIG. 3 is a schematic circuit diagram of a voltage regulator circuit according to the present invention;

fig. 4 is a chip pin diagram of the LTE module of the present invention;

fig. 5 is a schematic connection diagram of the pull-up resistor of the present invention;

fig. 6 is a schematic circuit diagram corresponding to the SLIC module of the present invention;

FIG. 7 is a diagram of the chip pins of the ARM processor of the present invention;

FIG. 8 is a pin diagram of a chip with a latch control switching circuit.

Detailed Description

The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that the embodiments or technical features described below can be arbitrarily combined to form a new embodiment without conflict.

The scheme of the embodiment comprises three parts, namely a 3.3V signal system part, a level conversion system part and a 1.8V signal system part; the connection relationship of each part is that a 3.3V signal system is connected to a level conversion system part, and a 1.8V signal system is connected to the level conversion system part; the level shift system serves as a bridge to connect the two systems.

The embodiment provides a level conversion system, including 1.8V signal module, 3.3V signal module and level conversion circuit, level conversion circuit includes voltage stabilizing circuit and area lock control converting circuit, voltage stabilizing circuit's input and area lock control converting circuit's 3.3V voltage end electric connection, voltage stabilizing circuit's output and area lock control converting circuit's 1.8V voltage end electric connection, 1.8V signal module is through area lock control converting circuit and 3.3V signal module electric connection.

As shown in fig. 4, fig. 6, and fig. 7, in this embodiment, the 1.8V signal module is an LTE module, the 3.3V signal system includes an ARM processor and an SLIC module, and the conversion control chip is respectively connected to corresponding terminals of the ARM processor and the SLIC module; the model of the ARM processor is MT7620A, and the model of a chip in the SLIC module is SI 3217X; the LTE module is EC 25. The GPIO level in the LTE system is 1.8V LVCOMS level, the GPIO level in the ARM system is 3.3V LVCOMS level, and the level is converted into a two-way recognizable signal through a level conversion circuit, so that the two systems can carry out normal communication. The 1.8V voltage terminal is 1.8V _ LTE in fig. 1, and the 3.3V voltage terminal is 3.3VD in fig. 1.

As shown in fig. 1, fig. 2, fig. 4, and fig. 5, which are schematic diagrams illustrating a connection between a lock control conversion circuit and a 1.8V signal system, specifically, the lock control conversion circuit is a conversion control chip, and the conversion control chip includes end bits electrically connected to the 1.8V signal system, end bits electrically connected to the 3.3V signal system, a 1.8V voltage terminal, a 3.3V voltage terminal, and a ground terminal. The 1.8V signal system is connected with a 1.8V voltage end of the conversion control chip through a pull-up resistor, and the resistance value of the pull-up resistor is 472 omega; the pull-up resistors are a resistor R319 and a resistor R320 in FIG. 5; the conversion control chip is in a model of 74HC125 AD. As shown in fig. 8, which is a specific pin diagram of the conversion control chip, in the description of the present embodiment, the specific pin diagram is expressed by disassembling the conversion control chip into different circuit structure modules, and the specific disassembly structure is shown in fig. 1, and those skilled in the art can know how to perform pin connection and why to perform level conversion by using the chip through the illustration of fig. 1 and 8.

As shown in fig. 3, the voltage stabilizing circuit includes a voltage stabilizing chip, a first filtering module, a second filtering module and a voltage dividing module; the voltage division module comprises a resistor R1 and a resistor R2, and the voltage stabilizing chip comprises an input end, an output end and a feedback end; the 3.3V voltage end of the band lock control conversion circuit is connected with one end of the first filtering module and the input end of the voltage stabilizing chip, the other end of the first filtering module is grounded, the 1.8V voltage end of the band lock control conversion circuit is connected with the output end of the voltage stabilizing chip and one end of the second filtering module, the other end of the second filtering module is grounded, the feedback end of the voltage stabilizing chip is grounded through a resistor R1, and the feedback end of the voltage stabilizing chip is connected with the output end of the voltage stabilizing chip through a resistor R2. The first filtering module comprises a capacitor C1 and a capacitor C2, and a capacitor C1 is connected with a capacitor C2 in parallel; the second filtering module comprises a capacitor C3 and a capacitor C4, and the capacitor C3 is connected with the capacitor C4 in parallel. The capacitance value of the capacitor C1 is 0.1 muF, the capacitance value of the capacitor C2 is 0.4 muF, the resistance value of the resistor R1 is 97.6 omega, and the resistance value of the resistor R2 is 43 omega. The model of the voltage stabilizing chip is ZTP1117 SA. The voltage stabilizing circuit is used for keeping the voltage at two output ends of the voltage stabilizing circuit stable.

The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention cannot be limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are all within the protection scope of the present invention.

Claims

1. The level conversion system comprises a 1.8V signal module and a 3.3V signal module, and is characterized by further comprising a level conversion circuit, wherein the level conversion circuit comprises a voltage stabilizing circuit and a lock control conversion circuit, the input end of the voltage stabilizing circuit is electrically connected with the 3.3V voltage end of the lock control conversion circuit, the output end of the voltage stabilizing circuit is electrically connected with the 1.8V voltage end of the lock control conversion circuit, and the 1.8V signal module is electrically connected with the 3.3V signal module through the lock control conversion circuit.

2. The system of claim 1, wherein the voltage regulator circuit comprises a voltage regulator chip, a first filter module, a second filter module, and a voltage divider module; the voltage division module comprises a resistor R1 and a resistor R2, and the voltage stabilizing chip comprises an input end, an output end and a feedback end; the 3.3V voltage end of the band lock control conversion circuit is connected with one end of the first filtering module and the input end of the voltage stabilizing chip, the other end of the first filtering module is grounded, the 1.8V voltage end of the band lock control conversion circuit is connected with the output end of the voltage stabilizing chip and one end of the second filtering module, the other end of the second filtering module is grounded, the feedback end of the voltage stabilizing chip is grounded through a resistor R1, and the feedback end of the voltage stabilizing chip is connected with the output end of the voltage stabilizing chip through a resistor R2.

3. The level shift system of claim 2, wherein the first filtering module comprises a capacitor C1 and a capacitor C2, wherein the capacitor C1 is connected in parallel with the capacitor C2; the second filtering module comprises a capacitor C3 and a capacitor C4, and the capacitor C3 is connected with the capacitor C4 in parallel.

4. The system of claim 3, wherein the capacitor C1 has a capacitance of 0.1 μ F, the capacitor C2 has a capacitance of 0.4 μ F, the resistor R1 has a resistance of 97.6 Ω, and the resistor R2 has a resistance of 43 Ω.

5. The system of claim 4, wherein the voltage regulation chip is model ZTP1117 SA.

6. The system of claim 1, wherein the latch controlled switching circuit is a switching control chip, and the switching control chip comprises terminals electrically connected to the 1.8V signal module, terminals electrically connected to the 3.3V signal module, a 1.8V voltage terminal, a 3.3V voltage terminal, and a ground terminal.

7. The level shift system as claimed in claim 6, wherein the 1.8V signal system is connected to the 1.8V voltage terminal of the shift control chip through a pull-up resistor, and the pull-up resistor has a resistance of 472 Ω.

8. The system of claim 6, wherein the conversion control chip is of a type 74HC125 AD.

9. The system of claim 6, wherein the 3.3V signal system comprises an ARM processor and a SLIC module, and the conversion control chip is respectively connected to corresponding terminals of the ARM processor and the SLIC module; the model of the ARM processor is MT7620A, and the model of a chip in the SLIC module is SI 3217X.

10. The system of any of claims 1-9, wherein the 1.8V signal module is an LTE module having a model number of EC 25.