CN210405254U - Frequency converter control circuit - Google Patents
Frequency converter control circuit Download PDFInfo
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- CN210405254U CN210405254U CN201921594374.5U CN201921594374U CN210405254U CN 210405254 U CN210405254 U CN 210405254U CN 201921594374 U CN201921594374 U CN 201921594374U CN 210405254 U CN210405254 U CN 210405254U
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Abstract
The utility model relates to the technical field of frequency converters, and discloses a frequency converter control circuit with stable driving signal and higher safety performance of an IGBT, which comprises a sampling circuit, a control circuit and a control circuit, wherein the sampling circuit is configured on a collector electrode of the IGBT and is used for acquiring a current signal flowing through the IGBT; the control end of the logic circuit is coupled to the grid of the IGBT; the input end of the amplifying circuit is connected with the output end of the logic circuit; the inverting input end of the adder circuit is coupled to the output end of the amplifying circuit; the non-inverting input end of the threshold comparison circuit is connected with the output end of the adder circuit, and the current signal output by the adder circuit is compared with the reference signal of the threshold comparison circuit; the first input end of the holding circuit is coupled with the output end of the threshold comparison circuit; the input end of the controller is coupled with the output end of the holding circuit; if the current signal is larger than the reference signal, the holding circuit outputs a high level, and the high level is used for triggering the controller to close the driving signal of the IGBT.
Description
Technical Field
The utility model relates to a converter technical field, more specifically say, relate to a converter control circuit.
Background
The frequency converter is a power control device which applies a frequency conversion technology and a microelectronic technology and controls an alternating current motor by changing the frequency of a working power supply. In the past, a solid-state power supply directly provides required electric energy for a load, when the load is started, the impact on a power grid is large, the voltage of the power grid is pulled down instantly, and the reliability of the output voltage of the solid-state power supply is low.
Therefore, in the prior art, a frequency converter control circuit with adjustable output voltage/frequency ratio and high reliability is provided, so that the problem of large impact on a power grid when a load is started is effectively solved. However, when a conventional inverter outputs a variable voltage to a load, a PWM (pulse width modulation) pulse signal is unstable when an IGBT (Insulated Gate Bipolar Transistor) operates, so that the temperature of the IGBT increases and the performance decreases, and the IGBT is broken by a peak current when the IGBT is used for a long time.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in, to the unstable defect of the above-mentioned pulse signal of prior art, provide a stable and higher converter control circuit of security performance of IGBT's drive signal.
The utility model provides a technical scheme that its technical problem adopted is: a frequency converter control circuit is constructed, which comprises a sampling circuit, a logic circuit, an amplifying circuit, an adder circuit, a threshold comparison circuit, a holding circuit and a controller,
the sampling circuit is configured at a collector of the IGBT and used for acquiring a current signal flowing through the IGBT;
the input end of the logic circuit is connected with the output end of the sampling circuit and is used for receiving the current signal output by the sampling circuit;
the control end of the logic circuit is coupled to the grid electrode of the IGBT;
the input end of the amplifying circuit is connected with the output end of the logic circuit;
the inverting input end of the adder circuit is coupled to the output end of the amplifying circuit and is used for operating the current signal input by the amplifying circuit;
the non-inverting input end of the threshold comparison circuit is connected with the output end of the adder circuit, and the current signal output by the adder circuit is compared with the reference signal of the threshold comparison circuit;
a first input terminal of the holding circuit is coupled to an output terminal of the threshold comparison circuit;
the input end of the controller is coupled with the output end of the holding circuit;
and if the current signal is greater than the reference signal, the holding circuit outputs a high level, and the high level is used for triggering the controller to close the driving signal of the IGBT.
In some embodiments, the threshold comparison circuit is provided with a first threshold comparison circuit and a second threshold comparison circuit, and the adder circuit comprises an adder;
the inverting input end of the first threshold comparison circuit is connected with a high level, the non-inverting input end of the first threshold comparison circuit is connected with the output end of the adder, and the inverting input end of the adder is connected with the output end of the amplifying circuit;
the output end of the first threshold comparison circuit is coupled to the first input end of the holding circuit;
the non-inverting input end of the second threshold comparison circuit is connected with the high level, and the inverting input end of the second threshold comparison circuit is connected with one end of the sampling circuit and the control end of the logic circuit;
the output end of the second threshold comparison circuit is coupled to the first input end of the holding circuit.
In some embodiments, the amplification circuit comprises a first amplifier and a second amplifier,
inverting input ends of the first amplifier and the second amplifier are connected with an output end of the logic circuit;
and the output ends of the first amplifier and the second amplifier are connected with the inverting input end of the adder.
In some embodiments, the first threshold comparison circuit comprises a first comparator, the second threshold comparison circuit comprises a second comparator and a third comparator;
the circuit sampling device is provided with a first resistor and a second resistor, and the logic circuit is provided with a first four-way analog switch and a second four-way analog switch;
the inverting input end of the first comparator is connected with the high level, the non-inverting input end of the first comparator is connected with the output end of the adder, and the output end of the first comparator is coupled with the first input end of the holding circuit;
the inverting input end of the second comparator is connected with one end of the first resistor and the control end of the first four-way bidirectional analog switch,
the non-inverting input end of the second comparator is connected with the high level, and the output end of the second comparator is connected with the first input end of the holding circuit;
the inverting input end of the third comparator is connected with one end of the second resistor and the control end of the second four-way bidirectional analog switch,
the non-inverting input end of the third comparator is connected with the high level, and the output end of the third comparator is connected with the first input end of the holding circuit;
the other ends of the first resistor and the second resistor are commonly connected with a collector of the IGBT.
In some embodiments, the holding circuit comprises an R-S flip-flop having a first input commonly connected with outputs of the first comparator, the second comparator and the third comparator.
In some embodiments, the device further comprises a first diode, a second diode and a third diode,
anodes of the first diode, the second diode and the third diode are respectively connected with a first input end of the R-S trigger;
the cathode of the first diode is connected with the output end of the first comparator;
the cathode of the second diode is connected with the output end of the second comparator;
and the cathode of the third diode is connected with the output end of the third comparator.
In some embodiments, further comprises a fourth diode, a fifth diode, an eighth diode and a ninth diode,
anodes of the fourth diode and the eighth diode are connected with an inverting input end of the second comparator;
the cathode of the fourth diode is connected with the control end of the first four-way bidirectional analog switch, and the cathode of the eighth diode is connected with one end of the first resistor;
anodes of the fifth diode and the ninth diode are connected with an inverting input end of the third comparator;
the cathode of the fifth diode is connected with the control end of the second four-way analog switch, and the cathode of the ninth diode is connected with one end of the second resistor.
The frequency converter control circuit of the utility model comprises a sampling circuit, a logic circuit, an amplifying circuit, an adder circuit, a threshold comparison circuit, a holding circuit and a controller, wherein the sampling circuit is used for acquiring a current signal flowing through an IGBT; the current signal output by the adder circuit is compared with the reference signal of the threshold comparison circuit; the first input end of the holding circuit is coupled with the output end of the threshold comparison circuit; the input end of the controller is coupled with the output end of the holding circuit; if the current signal is larger than the reference signal, the holding circuit outputs a high level, and the high level is used for triggering the controller to close the driving signal of the IGBT. Compared with the prior art, the sampling circuit acquires the current signal flowing through the IGBT, the signal is processed and compared through the adder circuit and the threshold comparison circuit, the comparison result is output to the controller, when the IGBT is abnormal, the controller can timely block the driving signal of the IGBT, the IGBT is guaranteed to operate in a safer voltage range, and the overall stability of the frequency converter is improved.
Drawings
The invention will be further explained with reference to the drawings and examples, wherein:
fig. 1a is a partial circuit diagram of an inverter circuit according to an embodiment of the present invention;
fig. 1b is a driving waveform diagram of an IGBT bridge arm provided by the present invention;
fig. 2 is a partial circuit diagram of an embodiment of a control circuit of a frequency converter provided by the present invention.
Detailed Description
In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1a is a partial circuit diagram of an inverter circuit according to an embodiment of the present invention, and fig. 1b is a driving waveform diagram of an IGBT bridge arm according to the present invention.
As shown in fig. 1a and 1b, in the first embodiment of the inverter circuit of the present invention, the inverter circuit is mainly formed by connecting at least two IGBTs, wherein the IGBTs form an upper bridge arm circuit and a lower bridge arm circuit of the inverter circuit, and in this embodiment, the lower bridge arm circuit is taken as an example.
Specifically, fig. 1a shows an H-bridge PWM converting circuit operating in a PWM rectification state (this figure is an equivalent circuit under the input of a sine wave positive half-wave, two IGBTs of the upper half-bridge are not shown), and fig. 1b shows driving signals of the IGBTs of the lower bridge arm circuit and related device waveforms. Now, the positive half-wave working process is taken as an example for analysis (for a three-phase PWM circuit, the analysis process and conclusion of the PWM circuit are performed in a rectification and inversion working state or a single-phase DC and DC working state).
In the circuit shown in fig. 1a, in the positive half cycle of the mains supply, a high frequency drive signal shown by Ug (T2, T4) is applied to the gates of the two IGBTs of the lower half bridge, resulting in a tube drop waveform Ut.
The working principle is as follows: at time T1-T2, under the action of the PWM driving signal, T2 and T4 are turned on, the current passing through the inductor Ls is increased under the action of the alternating current, and an exponentially rising pipe voltage drop waveform as shown by Ut in fig. 1b is formed on the T2 pipe, and the pipe voltage drop is the voltage drop generated by the body resistance when the IGBT is turned on by the on-state current.
At times t2-t 3: t2 and T4 are turned off, and because there is stored energy in the inductor Ls, the diodes installed at both ends of the collector and emitter of the IGBT T2 and IGBT T4 freewheel under the action of the inductor Ls, forming a tube drop waveform shown by the shaded portion of Ut in fig. 1b, and so on.
Analysis shows that in order to be able to detect the value of the pipe drop when the IGBT is turned on, the pipe drop when the IGBT is turned on at the time t1-t2 should be retained, and the current value of the pipe drop of the IGBT detected at the time t2-t3 should be removed, i.e., the pipe drop waveform shown by the shaded portion in Ut in fig. 1 b. Since the switching frequency of IGBTs is relatively high and there is a large switching noise, sufficient consideration should be given to designing the sampling circuits (10a, 10 b).
From the above analysis, under normal conditions, the value of the tube voltage drop Uce when the IGBT is turned on is relatively low, and is usually smaller than the rated value of the data Uce given by the device manual. If the H-type bridge conversion circuit fails (like a 'through' phenomenon that an upper IGBT and a lower IGBT on a bridge arm on one side are conducted at the same time), a tube voltage which is much larger than a normal value is generated at two ends of a C-E pole of a lower tube IGBT. If the pipe voltage drop value during the fault can be quickly detected, the pipe voltage drop value can be used as a basis for protecting the IGBT, and therefore the IGBT is effectively protected.
Fig. 2 is a partial circuit diagram of an embodiment of a control circuit of a frequency converter provided by the present invention. As shown in fig. 2, the frequency converter control circuit mainly includes sampling circuits (10a, 10b), a logic circuit 20, an amplifying circuit 30, an adder circuit 40, threshold comparison circuits (50a, 50b), a holding circuit 60, and a controller MUC.
Specifically, the sampling circuits (10a, 10b) are disposed at the collectors of the IGBTs (T2, T4), and are configured to acquire a current signal flowing through the IGBTs and output the current signal to the logic circuit 20.
The logic circuit 20 is used for the transmission and processing of discrete signals, and is a circuit which realizes the logical operation and operation of digital signals by using the binary system as the principle. The logic circuit 20 has an input terminal (IN), an output terminal (out) and a control terminal (C).
The input end of the logic circuit 20 is connected to the output ends of the sampling circuits (10a, 10b) for receiving the current signals output by the sampling circuits (10a, 10b), and the control end of the logic circuit 20 is coupled to the gate of the IGBT.
The collector current signal and the gate current signal of the IGBT obtained by the sampling circuits (10a, 10b) are calculated by the logic circuit 20 and then output to the amplifier circuit 30.
The amplifying circuit 30 can increase the output power of the input signal. The input terminal of the amplifying circuit 30 is connected to the output terminal of the logic circuit 20, and specifically, the inverting input terminal of the amplifying circuit 30 is connected to the output terminal of the logic circuit 20. The amplifier circuit 30 amplifies the input current signal and outputs the amplified current signal to the adder circuit 40.
The inverting input terminal of the adder circuit 40 is coupled to the output terminal of the amplifying circuit 30, and operates the current signal input by the amplifying circuit 30, and then outputs the current signal to the threshold comparing circuits (50a, 50b), where the threshold comparing circuit has a first threshold comparing circuit 50a and a second threshold comparing circuit 50b, where the threshold comparing circuits (50a, 50b) have reference signals, and in this embodiment, the voltage value of the reference signal is + 12V.
In the present embodiment, the current signal output from the adder circuit 40 is input to the first threshold comparison circuit 50 a.
Specifically, the non-inverting input terminal of the first threshold comparison circuit 50a is connected to the output terminal of the adder circuit 40, and the current signal output from the adder circuit 40 is compared with the reference signal of the first threshold comparison circuit 50a, and the compared output parameter is output to the holding circuit 60 in the form of a level (i.e., high level or low level).
The holding circuit 60 has a function of holding the original state after canceling the external signal after the inversion. Specifically, a first input terminal (corresponding to the R terminal) of the holding circuit 60 is coupled to an output terminal of the first threshold comparing circuit 50a (threshold comparing circuit), and outputs a level parameter obtained by comparing the level parameter with the reference signal to the controller MUC.
The controller MUC is used as the core of the circuit and has the functions of logical operation, control, feedback and alarm output.
The input terminal of the controller MUC is coupled to the output terminal (corresponding to the Qa terminal) of the hold circuit 60.
If the current signal is greater than the reference signal, the holding circuit 60 outputs a high level, and the high level is used for triggering the controller MUC to close the drive signal of the IGBT, so that the IGBT is switched from on to off, on one hand, the IGBT is protected in time in the abnormal state of the circuit, and further, the stability and the safety of the circuit are improved; on the other hand, in the abnormal state of the circuit, the controller MUC stops outputting the PWM signal, so that the IGBT is cut off, and the load (the crusher or the motor) can be powered off in time, so that the load coil is prevented from being burnt by peak current, and the safety of the whole operation is improved.
In some embodiments, in order to improve the accuracy of the sampled signal (i.e., the current signal of the IGBT), a first amplifier a1 and a second amplifier a2 may be provided in the amplifying circuit 20. Specifically, the inverting inputs of the first amplifier a1 and the second amplifier a2 are commonly connected to the output of the logic circuit 20.
The output terminals of the first amplifier a1 and the second amplifier a2 are commonly connected to the inverting input terminal of the adder circuit 40, and the current signal input from the logic circuit 20 is amplified by the first amplifier a1 and the second amplifier a2 and then output to the adder circuit 40.
In some embodiments, in order to improve the safety of the IGBT operation, a first threshold comparison circuit 50a and a second threshold comparison circuit 50b may be provided in the circuit.
Adder A3 is provided in adder circuit 40, specifically, adder A3 is divided into a half adder and a full adder, where the addend and the addend are inputs, and the sum and the carry are outputs as half adders; if the addend, the summand, and the carry of the low order bits are inputs, and the sum and the carry are outputs, a full adder is provided.
Specifically, the inverting input terminal of the first threshold comparing circuit 50a is connected to the high level (+12V), the non-inverting input terminal of the first threshold comparing circuit 50a is connected to the output terminal of the adder A3, and the inverting input terminal of the adder A3 is connected to the output terminal of the amplifying circuit 30, specifically, the inverting input terminal of the adder A3 is connected to the output terminals of the first amplifier a1 and the second amplifier a2 in common.
The output terminal of the first threshold comparing circuit 50a is coupled to the first input terminal (corresponding to the R terminal) of the holding circuit 60, and the input current signal is compared with the reference signal of the first threshold comparing circuit 50a to obtain a level signal, which is output to the holding circuit 60, and then input to the signal input terminal of the controller MUC through the holding circuit 60.
Meanwhile, the non-inverting input terminal of the second threshold comparing circuit 50b is connected to the high level (+12V),
the inverting input terminal of the second threshold comparing circuit 50b is commonly connected to one terminal of the sampling circuits (10a, 10b) and the control terminal of the logic circuit 20. The gate drive signal of the IGBT and the collector current signal are input to the inverting input terminal of the second threshold comparison circuit 50b, and compared with the reference signal of the second threshold comparison circuit 50 b.
An output terminal of the second threshold comparing circuit 50b is coupled to a first input terminal (corresponding to terminal R) of the holding circuit 60.
Illustratively, when a driving signal is input to the gate of the IGBT T2, the tube voltage drop of the down tube IGBT T2 of the PWM conversion circuit abnormally increases (set the level value to "high"), that is, the voltage of the collector of the IGBT T2 abnormally increases, and the high level UT2-dBy applying the resistor (corresponding resistor R1) to the cathode of the diode (corresponding diode D8) and applying the high level driving signal to the IGBT T2 to the cathode of the diode (corresponding diode D4), for the second threshold comparing circuit 50b (corresponding to the second comparator a5), the inverting input terminal thereof is at a high level, and if the level value is larger than the reference signal value (+12V) of the non-inverting input terminal, the corresponding second comparator a5 (belonging to the second threshold comparing circuit 50b) outputs a low level, the low level is applied to the first input terminal (corresponding to the R terminal) of the holding circuit 60 through a diode (corresponding to the diode D2), the output level of the output terminal (corresponding to the Qa terminal) of the holding circuit 60 is inverted, a high level is output to the controller MUC, this high level may trigger the controller MUC to turn off the drive signal to the IGBT T2, causing the IGBT T2 to turn off.
In some embodiments, to improve the detection capability of the IGBT leg current signals, circuit samples (10a, 10b) may be respectively disposed on the collector electrodes of the IGBTs. Specifically, the sampling circuit (10a, 10b) includes a first resistor R1 and a second resistor R2, wherein the sampling circuit 10a is the first resistor R1, and the sampling circuit 10b is the second resistor R2.
One end of the first resistor R1 is connected to the collector (corresponding to T2-d) of the IGBT T2, and the other end of the first resistor R1 is commonly connected to the input terminal of the logic circuit 20 and the inverting input terminal of the second threshold comparison circuit 50 b.
One end of the second resistor R2 is connected to the collector (corresponding to T4-d) of the IGBT T4, and the other end of the second resistor R2 is commonly connected to the input terminal of the logic circuit 20 and the inverting input terminal of the second threshold comparison circuit 50 b.
In some embodiments, to improve the processing capability of the current signal of the IGBT, a first four-way analog switch K1 and a second four-way analog switch K2 may be provided in the logic circuit 20. The four-way analog switch is provided with an input end (IN), an output end (out) and a control end (C). Wherein the input and output are interchangeable. When the control end (C) is heightened, the switch is conducted; the switch is turned off when the control terminal (C) is applied with a low level.
Specifically, an input end (IN) of the first four-way analog switch K1 is connected to one end of a first resistor R1, a current signal of a collector of the IGBT T2 is input to the first four-way analog switch K1 through the first resistor R1, a control end (C) of the first four-way analog switch K1 is connected to a gate (corresponding to a T2-G end) of the IGBT T2, a driving signal of the gate is input to the first four-way analog switch K1, and an output end of the first four-way analog switch K1 is connected to an inverting input end of the second amplifier a 2.
The working principle is as follows; when the gate driving voltage of the IGBT T2 is at a high level, that is, the control terminal (C) is at a high level, the first four-way analog switch K1 is turned on, the collector current signal of the IGBT T2 is input to the inverting input terminal of the second amplifier a2, the input signal is amplified by the second amplifier a2, and then output to the adder A3.
When the input control terminal (C) is low, the first four-way analog switch K1 is turned off.
An input end (IN) of the second four-way analog switch K2 is connected with one end of a second resistor R2, a current signal of a collector of the IGBT T4 is input into the second four-way analog switch K2 through the second resistor R2, a control end (C) of the second four-way analog switch K2 is connected with a grid (corresponding to a T4-G end) of the IGBT T4, a driving signal of the grid is input into the second four-way analog switch K2, and an output end of the second four-way analog switch K2 is connected with an inverting input end of the first amplifier A1. The working principle is the same as that of the first four-way analog switch K1, and the description thereof is omitted here.
In some embodiments, to improve the accuracy of the current signal processing of the IGBT, a first comparator a4 may be provided at the first threshold comparison circuit 50 a.
Specifically, the inverting input terminal of the first comparator a4 is connected to the high level (+12V) through the twenty-second resistor R22 and the thirty-second resistor R32.
The non-inverting input terminal of the first comparator a4 is connected to the output terminal of the adder A3 through a twenty-first resistor R21, a twenty-sixth resistor R26, a twenty-seventh resistor R27 and a twenty-eighth resistor R28 which are connected in series. The output terminal of the first comparator a4 is connected to the first input terminal (corresponding to terminal R) of the R-S flip-flop U1 (belonging to the holding circuit 60) through a thirtieth resistor R30.
The operating principle is that the current signals of the IGBTs (T2, T4) are amplified by the first amplifier a1 and the second amplifier a2, then output to the adder A3, calculated by the adder A3, then output to the first comparator a4, compared with the reference signal (+12V) of the first comparator a4, when the input current signal is greater than the reference signal, the first comparator a4 outputs a low level, and after the low level R-S flip-flop U1 is inverted, a high level is input to the output controller MUC to turn off the driving signals of the IGBTs (T2, T4), thereby protecting the IGBTs (T2, T4) from the breakdown of the fluctuating peak current.
In some embodiments, to improve the accuracy of the current signal processing of the IGBT, a second comparator a5, a third comparator a6, a fourth diode D4, a fifth diode D5, an eighth diode D8, a ninth diode D9, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, an eighteenth resistor R18 and a twentieth resistor R20 may be disposed in the second threshold comparison circuit 50 b.
Specifically, the inverting input terminal of the second comparator a5 is commonly connected to one terminal of the first resistor R1 and the control terminal (C) of the first four-way analog switch K1.
The non-inverting input terminal of the second comparator a5 is connected to the high level (+12V), and the output terminal of the second comparator a5 is connected to the first input terminal (corresponding to the R terminal) of the R-S flip-flop U1 (belonging to the holding circuit 60).
The inverting input terminal of the third comparator a6 is commonly connected to one terminal of the second resistor R2 and the control terminal (C) of the second four-way analog switch K2.
The non-inverting input terminal of the third comparator a6 is connected to the high level (+12V), and the output terminal of the third comparator a6 is connected to the first input terminal (corresponding to the R terminal) of the R-S flip-flop U1 (belonging to the holding circuit 60).
The other end of the first resistor R1 is connected to the collector (corresponding to T2-d) of the IGBT T2, and the other end of the second resistor R2 is connected to the collector (corresponding to T4-d) of the IGBT T4.
Further, anodes of the fourth diode D4 and the eighth diode D8 are commonly connected to the inverting input terminal of the second comparator a5 and one end of the first capacitor C1, a cathode of the fourth diode D4 is connected to the control terminal (C) of the first four-way analog switch K1, and a cathode of the eighth diode D8 is connected to one end of the first resistor R1.
The other end of the first capacitor C1 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the non-inverting input terminal of the second comparator a 5.
One end of the eighteenth resistor R18 is connected to the high (+12V) terminal, and the other end of the eighteenth resistor R18 is coupled to the non-inverting input terminal of the second comparator a 5. Note that the high level (+12V) is the reference signal value of the second comparator a 5.
Anodes of the fifth diode D5 and the ninth diode D9 are commonly connected to the inverting input terminal of the third comparator a6 and one end of the third capacitor C3, a cathode of the fifth diode D5 is connected to the control terminal (C) of the second four-way analog switch K2, and a cathode of the ninth diode D9 is connected to one end of the second resistor R2.
The other end of the third capacitor C3 is connected to one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is connected to the non-inverting input terminal of the third comparator a 6.
One end of the twentieth resistor R20 is connected to the high (+12V) terminal, and the other end of the twentieth resistor R20 is coupled to the non-inverting input terminal of the third comparator a 6. Note that the high level (+12V) is the reference signal value of the third comparator a 6.
Illustratively, taking the IGBT T4 as an example, when the tube voltage drop of the lower tube IGBT T4 of the IGBT leg is abnormally increased, that is, the current signal input to the inverting input terminal of the third comparator a6 is greater than the reference signal, the third comparator a6 outputs a low level signal, which is applied to the first input terminal (corresponding to the R terminal) of the R-S flip-flop U1 (belonging to the holding circuit 60) through the third diode D3, the input low level is inverted in the R-S flip-flop U1, and the output terminal Qa of the R-S flip-flop U1 outputs a high level.
In some embodiments, to protect the R-S flip-flop U1 from transient large current breakdown, a first diode D1, a second diode D2, and a third diode D3 may be provided in the circuit.
Specifically, anodes of the first diode D1, the second diode D2, and the third diode D3 are commonly connected to a first input terminal (corresponding to the R terminal) of the R-S flip-flop U1, respectively.
The cathode of the first diode D1 is connected to the output of the first comparator a4, the cathode of the second diode D2 is connected to the output of the second comparator a5, and the cathode of the third diode D3 is connected to the output of the third comparator a 6.
While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many modifications may be made by one skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (7)
1. A frequency converter control circuit is characterized by comprising a sampling circuit, a logic circuit, an amplifying circuit, an adder circuit, a threshold comparison circuit, a holding circuit and a controller,
the sampling circuit is configured at a collector of the IGBT and used for acquiring a current signal flowing through the IGBT;
the input end of the logic circuit is connected with the output end of the sampling circuit and is used for receiving the current signal output by the sampling circuit;
the control end of the logic circuit is coupled to the grid electrode of the IGBT;
the input end of the amplifying circuit is connected with the output end of the logic circuit;
the inverting input end of the adder circuit is coupled to the output end of the amplifying circuit and is used for operating the current signal input by the amplifying circuit;
the non-inverting input end of the threshold comparison circuit is connected with the output end of the adder circuit, and the current signal output by the adder circuit is compared with the reference signal of the threshold comparison circuit;
a first input terminal of the holding circuit is coupled to an output terminal of the threshold comparison circuit;
the input end of the controller is coupled with the output end of the holding circuit;
and if the current signal is greater than the reference signal, the holding circuit outputs a high level, and the high level is used for triggering the controller to close the driving signal of the IGBT.
2. The frequency converter control circuit of claim 1, wherein the threshold comparison circuit is provided with a first threshold comparison circuit and a second threshold comparison circuit, the adder circuit comprising an adder;
the inverting input end of the first threshold comparison circuit is connected with a high level, the non-inverting input end of the first threshold comparison circuit is connected with the output end of the adder, and the inverting input end of the adder is connected with the output end of the amplifying circuit;
the output end of the first threshold comparison circuit is coupled to the first input end of the holding circuit;
the non-inverting input end of the second threshold comparison circuit is connected with the high level, and the inverting input end of the second threshold comparison circuit is connected with one end of the sampling circuit and the control end of the logic circuit;
the output end of the second threshold comparison circuit is coupled to the first input end of the holding circuit.
3. The frequency converter control circuit of claim 2, wherein the amplification circuit comprises a first amplifier and a second amplifier,
inverting input ends of the first amplifier and the second amplifier are connected with an output end of the logic circuit;
and the output ends of the first amplifier and the second amplifier are connected with the inverting input end of the adder.
4. The frequency converter control circuit of claim 2, wherein the first threshold comparison circuit comprises a first comparator, and the second threshold comparison circuit comprises a second comparator and a third comparator;
the sampling circuit is provided with a first resistor and a second resistor, and the logic circuit is provided with a first four-way analog switch and a second four-way analog switch;
the inverting input end of the first comparator is connected with the high level, the non-inverting input end of the first comparator is connected with the output end of the adder, and the output end of the first comparator is coupled with the first input end of the holding circuit;
the inverting input end of the second comparator is connected with one end of the first resistor and the control end of the first four-way bidirectional analog switch,
the non-inverting input end of the second comparator is connected with the high level, and the output end of the second comparator is connected with the first input end of the holding circuit;
the inverting input end of the third comparator is connected with one end of the second resistor and the control end of the second four-way bidirectional analog switch,
the non-inverting input end of the third comparator is connected with the high level, and the output end of the third comparator is connected with the first input end of the holding circuit;
the other ends of the first resistor and the second resistor are commonly connected with a collector of the IGBT.
5. The frequency converter control circuit of claim 4, wherein the holding circuit comprises an R-S flip-flop having a first input commonly connected to the outputs of the first, second, and third comparators.
6. The inverter control circuit of claim 5, further comprising a first diode, a second diode, and a third diode,
anodes of the first diode, the second diode and the third diode are respectively connected with a first input end of the R-S trigger;
the cathode of the first diode is connected with the output end of the first comparator;
the cathode of the second diode is connected with the output end of the second comparator;
and the cathode of the third diode is connected with the output end of the third comparator.
7. The inverter control circuit of claim 4, further comprising a fourth diode, a fifth diode, an eighth diode, and a ninth diode,
anodes of the fourth diode and the eighth diode are connected with an inverting input end of the second comparator;
the cathode of the fourth diode is connected with the control end of the first four-way bidirectional analog switch, and the cathode of the eighth diode is connected with one end of the first resistor;
anodes of the fifth diode and the ninth diode are connected with an inverting input end of the third comparator;
the cathode of the fifth diode is connected with the control end of the second four-way analog switch, and the cathode of the ninth diode is connected with one end of the second resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921594374.5U CN210405254U (en) | 2019-09-24 | 2019-09-24 | Frequency converter control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921594374.5U CN210405254U (en) | 2019-09-24 | 2019-09-24 | Frequency converter control circuit |
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| CN210405254U true CN210405254U (en) | 2020-04-24 |
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| CN201921594374.5U Active CN210405254U (en) | 2019-09-24 | 2019-09-24 | Frequency converter control circuit |
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