CN212086083U

CN212086083U - Current limiting circuit and device of inverter

Info

Publication number: CN212086083U
Application number: CN202020586934.9U
Authority: CN
Inventors: 程启建; 于玮; 李睿
Original assignee: East Group Co Ltd
Current assignee: East Group Co Ltd
Priority date: 2020-04-20
Filing date: 2020-04-20
Publication date: 2020-12-04
Anticipated expiration: 2030-04-20

Abstract

The utility model relates to a current-limiting circuit and device of dc-to-ac converter, this circuit includes: the device comprises a main control module, a wave sending module, an overcurrent detection module and a plurality of sealing and unlocking modules; the main control module is connected with the input end of the wave sending module, the wave sending module is provided with a plurality of output ends, the input end of each sealing and unlocking module is connected with one output end of the wave sending module, the output end of each sealing and unlocking module is used for being connected with one control signal input end of the three-level inverter, the input end of the over-current detection module is used for being connected with the output end of the three-level inverter, and the output end of the over-current detection module is connected with the input end of each sealing and unlocking module; through setting up a plurality of independent locking and unlocking modules to guarantee that each switch tube of three level inverter can both block the drive cycle by cycle when taking place the current-limiting, make when three level inverter appear the line-to-line short circuit, can prolong switch tubulose attitude switching time, reduce the damage to the switch tube, and reduce the loss of switch tube.

Description

Current limiting circuit and device of inverter

Technical Field

The utility model relates to the field of electronic technology, especially, relate to current limiting circuit and device of dc-to-ac converter.

Background

An inverter is a device that converts direct current into alternating current; the inverter mainly comprises an inverter bridge, control logic and a filter circuit; the multifunctional electric grinding wheel is widely applied to air conditioners, home theaters, electric grinding wheels, electric tools, sewing machines, DVDs (digital video disks), VCDs (video recorders), computers, televisions, washing machines, range hoods, refrigerators, video recorders, massagers, fans and lighting.

Referring to fig. 1, fig. 1 shows a circuit schematic diagram of a three-level inverter, which includes four switching tubes and a freewheeling diode, where the four switching tubes are switching tube T1, switching tube T2, switching tube T3 and switching tube T4, respectively, where switching tube T1 and switching tube T4 are outer tubes of a bridge arm, and switching tube T2 and switching tube T3 are inner tubes of the bridge arm.

At present, a current-limiting control system of a commonly used linear three-level inverter mainly includes a wave-sending and fault-driving protection module of a DSP (Digital Signal Processor), a CPLD (Complex Programmable Logic Device), an inverter current detection circuit and an inverter topology circuit, and its basic control strategy is: the DSP generates two driving signals, wherein the two driving signals are respectively a positive half-wave driving signal PWMA and a negative half-wave driving signal PWMB, an output voltage positive and negative half cycle selection signal PWMS and an enable signal PWMEN. When the PWMEN is at a high level, the CPLD generates four-way drive through the wave-transmitting module according to the wave-transmitting logic of the linear three-level inverter, when the PWMEN is at a high level and the PWMS is at a high level, the output voltage of the three-level inverter is in a positive half cycle, the switching tube T2 is switched on, the switching tube T4 is switched off, and the switching tubes T1 and T3 are switched on in a complementary mode and guarantee dead time; when the PWMEN is at a high level and the PWMS is at a low level, the output voltage is at a negative half cycle, the switch tube T3 is conducted, the switch tube T1 is cut off, the switch tubes T2 and T4 are conducted in a complementary mode, and the dead time is ensured, wherein the dead time is generated in the CPLD wave-generating module, and the phenomenon that the complementary tubes are conducted simultaneously due to the switching delay of the switch tubes is prevented.

However, in the current-limiting control system of the existing inverter, the outer pipe and the inner pipe are driven to be locked and unlocked according to the driving signal of the outer pipe and the hardware current-limiting detection signal, in order to prevent the pipe from being damaged due to overlarge stress, the outer pipe is firstly closed and then the inner pipe is closed to drive when the locking is driven, and the inner pipe is firstly opened and then the outer pipe is opened when the unlocking is carried out. This mode appears when hardware current-limiting signal processing has time delay and or line-to-line short circuit, leads to triggering the current-limiting when the inner tube is beaten the drive, can appear the very big phenomenon that inner tube switching frequency becomes during the unblock, even the on-off state of inner tube frequently switches, causes the damage of inner tube easily, and the switching loss of inner tube also can increase simultaneously.

SUMMERY OF THE UTILITY MODEL

Therefore, it is necessary to provide a current limiting circuit and a device for an inverter, which solve the problem that the conventional current limiting circuit for an inverter has large loss of a switching tube in the inverter.

There is provided a current limiting circuit of an inverter, the current limiting circuit of the inverter including: the device comprises a main control module, a wave sending module, an overcurrent detection module and a plurality of sealing and unlocking modules; the main control module is connected with the input end of the wave sending module, the wave sending module is provided with a plurality of output ends, the input end of each sealing and unlocking module is connected with one output end of the wave sending module, the output end of each sealing and unlocking module is used for being connected with one control signal input end of a three-level inverter, the input end of the over-current detection module is used for being connected with the output end of the three-level inverter, and the output end of the over-current detection module is connected with the input end of each sealing and unlocking module.

In one embodiment, the number of the locking and unlocking modules is equal to the number of control signal input ends in the three-level inverter.

In one embodiment, the output end of each locking and unlocking module is used for being connected with a control signal input end in a linear three-level inverter.

In one embodiment, the number of the locking and unlocking modules is four. The first sealing and unlocking module, the second sealing and unlocking module, the third sealing and unlocking module and the fourth sealing and unlocking module are respectively arranged; the wave-sending module is provided with four output ends which are respectively a first output end, a second output end, a third output end and a fourth output end, the input end of the first locking and unlocking module is connected with the first output end, the output end of the first locking and unlocking module is used for being connected with the first control signal input end of the three-level inverter, the input end of the second locking and unlocking module is connected with the second output end, the output end of the second locking and unlocking module is used for being connected with the second control signal input end of the three-level inverter, the input end of the third sealing and unlocking module is connected with the third output end, the output end of the third sealing and unlocking module is used for being connected with the third control signal input end of the three-level inverter, the input end of the fourth unlocking and sealing module is connected with the fourth output end, and the fourth output end of the fourth unlocking and sealing module is used for being connected with the fourth control signal input end of the three-level inverter.

In one embodiment, the main control module is further connected to the over-current detection module.

In one embodiment, the main control module is a digital signal processor.

In one embodiment, a current limiting device for an inverter is provided, the device comprises a three-level inverter and a current limiting circuit of the inverter in any one of the above embodiments; the output end of each sealing and unlocking module is connected with one control signal input end of the three-level inverter, and the input end of the over-current detection module is connected with the output end of the three-level inverter.

In one embodiment, the three-level inverter is a linear three-level inverter.

In one embodiment, the three-level inverter includes: a switching tube T1, a switching tube T2, a switching tube T3, a switching tube T4, a diode D5, a diode D6 and a capacitor C1; a first end of the switch tube T1 is configured to be connected to a positive half-wave power supply, a second end of the switch tube T1 and the switch tube T1 is connected to a first end of the switch tube T2, a second end of the switch tube T2 is connected to a first end of the switch tube T3, a second end of the switch tube T3 is connected to a first end of the switch tube T4, a second end of the switch tube T4 is configured to be connected to a negative half-wave power supply, a second end of the switch tube T3 is connected to an anode of the diode D6, a cathode of the diode D6 is connected to an anode of the diode D5, a cathode of the diode D5 is connected to a second end of the switch tube T1, a cathode of the diode D6 is further configured to be grounded, a second end of the switch tube D2 is connected to a first end of the capacitor C1, a second end of the capacitor C1 is configured to be grounded, and a first end of the capacitor C1 is further connected to an input end of the over-current, the control ends of the switch tube T1, the switch tube T2, the switch tube T3 and the switch tube T4 are respectively connected with the output end of the locking and unlocking module.

In one embodiment, the three-level inverter further comprises a diode D1, a diode D2, a diode D3, and a diode D4; an anode of the diode D1 is connected to the second terminal of the switch transistor T1, a cathode of the diode D1 is connected to the first terminal of the switch transistor T1, an anode of the diode D2 is connected to the second terminal of the switch transistor T2, a cathode of the diode D2 is connected to the first terminal of the switch transistor T2, an anode of the diode D3 is connected to the second terminal of the switch transistor T3, a cathode of the diode D3 is connected to the first terminal of the switch transistor T3, an anode of the diode D4 is connected to the second terminal of the switch transistor T4, and a cathode of the diode D4 is connected to the first terminal of the switch transistor T4.

The current limiting circuit of the inverter is provided with a plurality of independent sealing and unlocking modules which are respectively connected with each control signal input end in the three-level inverter so as to independently drive each switching tube of the three-level inverter and ensure that each switching tube of the three-level inverter can be blocked and driven cycle by cycle when current limiting occurs, so that the effect of wave-by-wave current limiting is better achieved, and when the three-level inverter has line-to-line short circuit, the switching time of the tubular state of a switch can be prolonged, namely the switching frequency of the switching state of the switching tube is reduced, so that the damage to the switching tube is reduced, the loss of the switching tube is reduced, and the service life of the switching tube is prolonged; furthermore, by reducing the switching frequency of the switching tube, the frequent jump of the output waveform of the inverter can be reduced, i.e. the current-limiting current waveform output by the inverter is better.

Drawings

Fig. 1 is a schematic circuit diagram of a conventional inverter;

fig. 2 is a block diagram of a current limiting control system of a conventional inverter;

fig. 3 is a block diagram of a current limiting circuit of the inverter according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating an abnormal current limit of the current limit control system of the conventional inverter shown in FIG. 2;

fig. 5 is a timing diagram illustrating an abnormal current limiting of the current limiting circuit of the inverter according to an embodiment of the present invention;

fig. 6 is a schematic circuit diagram of a current limiting circuit of the inverter according to another embodiment of the present invention;

fig. 7 is a block diagram of a current limiting device of an inverter according to an embodiment of the present invention;

fig. 8 is a schematic circuit diagram of a current limiting device of the inverter according to another embodiment of the present invention;

fig. 9 is a schematic circuit diagram of a three-level inverter in the current limiting device of the inverter according to an embodiment of the present invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, as those skilled in the art will be able to make similar modifications without departing from the spirit and scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In the present application, unless expressly stated or limited otherwise, the first feature may be directly on or directly under the second feature or indirectly via intermediate members. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.

For example, there is provided a current limiting circuit of an inverter, including: the device comprises a main control module, a wave sending module, an overcurrent detection module and a plurality of sealing and unlocking modules; the main control module is connected with the input end of the wave sending module, the wave sending module is provided with a plurality of output ends, the input end of each sealing and unlocking module is connected with one output end of the wave sending module, the output end of each sealing and unlocking module is used for being connected with one control signal input end of a three-level inverter, the input end of the over-current detection module is used for being connected with the output end of the three-level inverter, and the output end of the over-current detection module is connected with the input end of each sealing and unlocking module.

Referring to fig. 3, fig. 3 shows a block diagram of a current limiting circuit of an inverter according to an embodiment of the present invention, and an embodiment of the present invention provides a current limiting circuit 10 of an inverter, where the current limiting circuit 10 of the inverter includes: the system comprises a main control module 100, a wave sending module 200, an over-current detection module 500 and a plurality of locking and unlocking modules 400; the main control module 100 is connected to the input end of the wave generating module 200, the wave generating module 200 has a plurality of output ends, the input end of each of the locking and unlocking modules 300 is connected to one of the output ends of the wave generating module 200, the output end of each of the locking and unlocking modules 300 is used for being connected to a control signal input end of the three-level inverter 400, the input end of the over-current detection module 500 is used for being connected to the output end of the three-level inverter 400, and the output end of the over-current detection module 500 is connected to the input end of each of the locking and unlocking modules 300.

Specifically, a control signal input end of the three-level inverter is a control end of a switching tube in the three-level inverter; the sealing and unlocking module is used for sending a logic level signal to a control signal input end of the three-level inverter so as to control the conversion of the working state of the corresponding switch tube in the three-level inverter. It should be understood that the three-level inverter has a plurality of control signal input terminals, that is, the three-level inverter has a plurality of switching tubes, and each locking and unlocking module is used for being connected with one control signal input terminal in a one-to-one correspondence manner. Namely, the unlocking module is used for controlling the switching of the state of a switching tube.

Specifically, the over-current detection module is configured to detect a magnitude of an output current of the three-level inverter, and output a first control signal, that is, a current-limiting signal, when the current is detected to be greater than a preset value; and transmitting the first control signal to the sealing and unlocking module so that the sealing and unlocking driving module outputs a locking signal to enter a current limiting logic. When the current is detected to be smaller than or equal to a preset value, outputting a second control signal, and sending the second control signal to the sealing and unlocking module so as to enable the sealing and unlocking module to work normally, namely enable the sealing and unlocking module to output a normal driving pulse signal; thus, the purpose of wave-by-wave current limiting is achieved. In this embodiment, the first control signal is a low level signal, and the second control signal is a high level signal. It should be noted that the over-current detection module is the prior art, for example, the over-current detection module may be formed by combining a current detection unit and a comparator, and specific circuit schematic diagrams thereof are not listed in this embodiment.

To further illustrate the beneficial effects obtained by the current limiting circuit of the inverter described in the present application, as shown in fig. 4, it shows the timing diagram of the current limiting circuit of the conventional inverter when the line-to-line short circuit occurs in the positive half-wave signal, i.e. the current limiting circuit of the inverter in fig. 2 should be in the inverter of fig. 1, and its timing diagram when the line-to-line short circuit occurs in the positive half-wave signal, which is referred to as the abnormal current limiting timing diagram; in the normal mode, the overcurrent is generally generated when the outer tube is driven, but the overcurrent actually occurs when the outer tube is driven; the first control signal, i.e. the current limiting signal IC, is asserted when the inner tubes T2 and T4 are driven due to hardware delay, according to the existing wave-by-wave current limiting technology. As shown in fig. 4, when a current-limiting signal IC is detected at time T1, the voltage received by the unlocking/sealing module is pulled low, the current-limiting logic is entered, the outer tube is closed, that is, the switching tube T1 and the switching tube T4 are closed, at this time, the switching tube T1 and the switching tube T4 are driven to be in a closed state, and the inner tube is directly closed at time T1; namely a switch tube T2 and a switch tube T3; when the current-limiting signal is detected to be pulled low, the positive half-wave drive rising edge comes at the same time, the switch tube T2 and the switch tube T3 are turned on at the same time, the time is delayed to T4, the drive is turned on according to normal logic, the time delta T in the figure is short, the switch tube frequently jumps in a period, the phenomenon that the switching frequency of the switch tube T3 changes greatly occurs, the switch tube is damaged, and meanwhile the switching loss of the switch tube is increased.

In the current limiting circuit of the inverter in the present application, the circuit is applied to the three-level inverter circuit in fig. 1, that is, the switch tube T1, the switch tube T2, the switch tube T3 and the switch tube T4 in fig. 1 are respectively connected to the output end of a lock/unlock module. A timing diagram of the current limiting circuit of the inverter when a line-to-line short circuit occurs in a positive half-wave signal is shown in fig. 5, taking the positive half-wave as an example, for example, when an outer tube is driven, an overcurrent actually occurs, but the current limiting signal is only effective when an inner tube is driven due to hardware delay, a current limiting signal IC is detected at time T1, a receiving potential of a sealing and unlocking module is pulled low, the current limiting logic is entered, the sealing and unlocking module closes a switch tube T1 and a switch tube T4, at this time, the switch tube T1 and the switch tube T4 are driven to be in a closed state, and the switch tube T2 and the switch tube T3 are directly closed at time T1; when the current-limiting signal is detected to be pulled low, the control end of each switching tube is connected with different unlocking modules, so that the working state of each switching tube is not affected by logic signals sent by other unlocking modules, the switching tube T2 and the switching tube T3 are driven to be switched on or off according to the periodic source signals, namely the switching tube T2 and the switching tube T3 are switched on at the time T4 and then are driven according to a normal time sequence, the time delta T in fig. 5 is longer than the time delta T in fig. 4, so that the switching tube T3 keeps a switching state in a period close to one cycle, namely the switching frequency of the switching tube is reduced, the damage to the switching tube is reduced, the loss of the switching tube is reduced, and the service life of the switching tube is prolonged.

In order to reduce the production and manufacturing cost of the current limiting circuit of the inverter, in one embodiment, the number of the locking and unlocking modules is equal to the number of control signal input ends in the three-level inverter. Specifically, the output end of each sealing and unlocking module is used for being connected with a control signal input end in the three-level inverter, namely, each control signal input end in the three-level inverter is connected with one sealing and unlocking module, and the number of the sealing and unlocking modules is set to be equal to that of the control signal input ends in the three-level inverter, so that the current-limiting protection of the inverter is met, the occupation of resources of the sealing and unlocking modules is reduced, and the production and manufacturing cost is reduced.

In one embodiment, the output end of each locking and unlocking module is used for being connected with a control signal input end in a linear three-level inverter. The I-shaped three-level inverter is a 1-shaped three-level inverter, namely, the current limiting circuit of the inverter can be applied to the I-shaped inverter to carry out current limiting protection on the I-shaped three-level inverter, and can prolong the switching time of a switching tube state when the three-level inverter generates line-to-line short circuit, namely, reduce the switching frequency of the switching tube state, reduce the damage to the switching tube, reduce the loss of the switching tube and prolong the service life of the switching tube.

Referring to fig. 6, in one embodiment, the number of the locking and unlocking modules is four. Specifically, the linear three-level inverter generally comprises two outer tubes and two inner tubes, and the four sealing and unlocking modules are arranged to respectively drive the two outer tubes and the two inner tubes, so that the current-limiting protection of the linear three-level inverter is met, and the loss of a switching tube in the inverter is reduced. In detail, the four sealing and unlocking modules are respectively a first sealing and unlocking module, a second sealing and unlocking module, a third sealing and unlocking module and a fourth sealing and unlocking module; the wave-sending module is provided with four output ends which are respectively a first output end, a second output end, a third output end and a fourth output end, the input end of the first locking and unlocking module is connected with the first output end, the output end of the first locking and unlocking module is used for being connected with the first control signal input end of the three-level inverter, the input end of the second locking and unlocking module is connected with the second output end, the output end of the second locking and unlocking module is used for being connected with the second control signal input end of the three-level inverter, the input end of the third sealing and unlocking module is connected with the third output end, the output end of the third sealing and unlocking module is used for being connected with the third control signal input end of the three-level inverter, the input end of the fourth unlocking and sealing module is connected with the fourth output end, and the fourth output end of the fourth unlocking and sealing module is used for being connected with the fourth control signal input end of the three-level inverter.

Referring to fig. 3, in one embodiment, the main control module 100 is further connected to the over-current detection module 500, specifically, the main control module is connected to the over-current detection module, that is, the main control module is connected to an adjusting end of the over-current detection module, and the main control module is configured to adjust a current limiting current of the over-current detection module, that is, adjust a preset value, so as to meet requirements of different products or users.

In one embodiment, the main control module is a digital signal processor. Specifically, a digital Signal processor (dsp) is a dedicated chip for performing digital Signal processing. Through setting up digital signal processor to send wave module better and send positive half-wave drive signal and negative half-wave drive signal.

Referring to fig. 7, in one embodiment, an inverter current limiting apparatus 20 is provided, which includes a three-level inverter 400 and the inverter current limiting circuit 10 described in any of the above embodiments; the output end of each of the locking and unlocking modules 300 is connected to a control signal input end of the three-level inverter 400, and the input end of the over-current detection module 500 is connected to the output end of the three-level inverter 400. In one embodiment, the current limiting circuit 10 of the inverter includes: the system comprises a main control module 100, a wave sending module 200, an over-current detection module 500 and a plurality of locking and unlocking modules 300; the main control module 100 is connected to the input end of the wave generating module 200, the wave generating module 200 has a plurality of output ends, the input end of each of the locking and unlocking modules 300 is connected to one of the output ends of the wave generating module 200, the output end of each of the locking and unlocking modules 300 is connected to one of the control signal input ends of the three-level inverter 400, the input end of the over-current detection module 500 is connected to the output end of the three-level inverter 400, and the output end of the over-current detection module 500 is connected to the input end of each of the locking and unlocking modules 300.

The current limiting device of the inverter is provided with a plurality of independent sealing and unlocking modules which are respectively connected with each control signal input end in the three-level inverter so as to independently drive each switching tube of the three-level inverter and ensure that each switching tube of the three-level inverter can be blocked and driven cycle by cycle when current limiting occurs, so that the effect of wave-by-wave current limiting is better achieved, and when the three-level inverter has line-to-line short circuit, the switching time of the tubular state of a switch can be prolonged, namely the switching frequency of the switching state of the switching tube is reduced, so that the damage to the switching tube is reduced, the loss of the switching tube is reduced, and the service life of the switching tube is prolonged; furthermore, by reducing the switching frequency of the switching tube, the frequent jump of the output waveform of the inverter can be reduced, i.e. the current-limiting current waveform output by the inverter is better.

In one embodiment, the three-level inverter is a linear three-level inverter.

Referring to fig. 8 and 9, in one embodiment, the three-level inverter 400 includes: a switching tube T1, a switching tube T2, a switching tube T3, a switching tube T4, a diode D5, a diode D6 and a capacitor C1; a first end of the switch tube T1 is configured to be connected to the positive half-wave power supply + BUS, a second end of the switch tube T1 and the switch tube T1 are connected to a first end of the switch tube T2, a second end of the switch tube T2 and the switch tube T3 are connected, a second end of the switch tube T3 and the switch tube T4 are connected, a second end of the switch tube T4 is configured to be connected to the negative half-wave power supply-BUS, a second end of the switch tube T3 and the anode of the diode D6, a cathode of the diode D6 and the anode of the diode D5 are connected, a cathode of the diode D5 and the second end of the switch tube T1 are connected to ground, a cathode of the diode D6 and the second end of the switch tube D2 and the first end of the capacitor C1 are connected, a second end of the capacitor C1 and the second end of the capacitor C1 and the input end of the over-current detection module 500 are connected to the over-current detection module, the control ends of the switch tube T1, the switch tube T2, the switch tube T3 and the switch tube T4 are respectively connected with the output end of the locking and unlocking module. Specifically, the number of the sealing and unlocking modules is four, and the sealing and unlocking modules are respectively a first sealing and unlocking module, a second sealing and unlocking module, a third sealing and unlocking module and a fourth sealing and unlocking module; the control ends of the switch tube T1, the switch tube T2, the switch tube T3 and the switch tube T4 are respectively connected with the output end of one of the locking and unlocking modules; namely, the control end of the switch tube T1 is connected with the output end of the first unlocking module, the control end of the switch tube T2 is connected with the output end of the second unlocking module, the control end of the switch tube T3 is connected with the output end of the third unlocking module, and the control end of the switch tube T4 is connected with the output end of the fourth unlocking module. In the three-level inverter in this embodiment, the logic level signals output by the locking and unlocking module respectively control the switching states of the switching tube T1, the switching tube T2, the switching tube T3 and the switching tube T4 to change, so as to output three level signals, for example, the switching tube T1 and the switching tube T2 are controlled to be turned on, and the switching tube T3 and the switching tube T4 are controlled to be turned off, so that the first end of the capacitor C1 outputs a positive half-wave signal. For another example, the switch transistor T1 and the switch transistor T2 are controlled to be turned off, and the switch transistor T3 and the switch transistor T4 are controlled to be turned on, so that the first end of the capacitor C1 outputs a negative half-wave signal. For another example, the switching tube T1 and the switching tube T4 are controlled to be turned off, so that the first end of the capacitor C1 is grounded, and thus the inverter can output a three-level signal. In one embodiment, the switch tube is a field effect tube. In another embodiment, the switch tube is a triode.

Referring to fig. 9, in an embodiment, the three-level inverter 400 further includes an inductor L1, a first terminal of the inductor L1 is connected to a second terminal of the switching transistor D2, and a second terminal of the inductor L1 is connected to a first terminal of the capacitor C1.

Referring to fig. 9 again, in one embodiment, the three-level inverter further includes a diode D1, a diode D2, a diode D3, and a diode D4; an anode of the diode D1 is connected to the second terminal of the switch transistor T1, a cathode of the diode D1 is connected to the first terminal of the switch transistor T1, an anode of the diode D2 is connected to the second terminal of the switch transistor T2, a cathode of the diode D2 is connected to the first terminal of the switch transistor T2, an anode of the diode D3 is connected to the second terminal of the switch transistor T3, a cathode of the diode D3 is connected to the first terminal of the switch transistor T3, an anode of the diode D4 is connected to the second terminal of the switch transistor T4, and a cathode of the diode D4 is connected to the first terminal of the switch transistor T4. Specifically, the switch tube T1, the switch tube T2, the switch tube T3 and the switch tube T4 are respectively connected with a diode in parallel in an opposite direction, which is equivalent to a damping diode, to provide a loop for inductive load energy feedback, so as to prevent the switch tube from being broken down by reverse electromotive force generated by the inductive load, and to protect the switch tube.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A current limiting circuit of an inverter, the current limiting circuit of the inverter comprising: the device comprises a main control module, a wave sending module, an overcurrent detection module and a plurality of sealing and unlocking modules;

the main control module is connected with the input end of the wave sending module, the wave sending module is provided with a plurality of output ends, the input end of each sealing and unlocking module is connected with one output end of the wave sending module, the output end of each sealing and unlocking module is used for being connected with one control signal input end of a three-level inverter, the input end of the over-current detection module is used for being connected with the output end of the three-level inverter, and the output end of the over-current detection module is connected with the input end of each sealing and unlocking module.

2. The current-limiting circuit of an inverter according to claim 1, wherein the number of the locking and unlocking modules is equal to the number of control signal inputs in the three-level inverter.

3. The current-limiting circuit of claim 1, wherein the output terminal of each of the locking and unlocking modules is configured to be connected to a control signal input terminal of a linear three-level inverter.

4. The current-limiting circuit of an inverter according to claim 3, wherein the number of the locking and unlocking modules is four.

5. The current-limiting circuit of an inverter according to claim 1, wherein the main control module is further connected to the over-current detection module.

6. The current-limiting circuit of an inverter of claim 1, wherein the main control module is a digital signal processor.

7. A current limiting device of an inverter, comprising a three-level inverter and a current limiting circuit of the inverter as claimed in any one of claims 1 to 6;

the output end of each sealing and unlocking module is connected with one control signal input end of the three-level inverter, and the input end of the over-current detection module is connected with the output end of the three-level inverter.

8. The current-limiting apparatus of an inverter according to claim 7, wherein the three-level inverter is a line-type three-level inverter.

9. The current limiting device of the inverter according to claim 7, wherein the three-level inverter comprises: a switching tube T1, a switching tube T2, a switching tube T3, a switching tube T4, a diode D5, a diode D6 and a capacitor C1;

a first end of the switch tube T1 is configured to be connected to a positive half-wave power supply, a second end of the switch tube T1 and the switch tube T1 is connected to a first end of the switch tube T2, a second end of the switch tube T2 is connected to a first end of the switch tube T3, a second end of the switch tube T3 is connected to a first end of the switch tube T4, a second end of the switch tube T4 is configured to be connected to a negative half-wave power supply, a second end of the switch tube T3 is connected to an anode of the diode D6, a cathode of the diode D6 is connected to an anode of the diode D5, a cathode of the diode D5 is connected to a second end of the switch tube T1, a cathode of the diode D6 is further configured to be grounded, a second end of the switch tube D2 is connected to a first end of the capacitor C1, a second end of the capacitor C1 is configured to be grounded, and a first end of the capacitor C1 is further connected to an input end of the over-current, the control ends of the switch tube T1, the switch tube T2, the switch tube T3 and the switch tube T4 are respectively connected with the output end of the locking and unlocking module.

10. The current limiting device of the inverter according to claim 9, wherein the three-level inverter further comprises a diode D1, a diode D2, a diode D3, and a diode D4; an anode of the diode D1 is connected to the second terminal of the switch transistor T1, a cathode of the diode D1 is connected to the first terminal of the switch transistor T1, an anode of the diode D2 is connected to the second terminal of the switch transistor T2, a cathode of the diode D2 is connected to the first terminal of the switch transistor T2, an anode of the diode D3 is connected to the second terminal of the switch transistor T3, a cathode of the diode D3 is connected to the first terminal of the switch transistor T3, an anode of the diode D4 is connected to the second terminal of the switch transistor T4, and a cathode of the diode D4 is connected to the first terminal of the switch transistor T4.