CN210378420U

CN210378420U - LED display screen blanking circuit and chip

Info

Publication number: CN210378420U
Application number: CN201921974755.6U
Authority: CN
Inventors: 胡渊; 刘盛彬
Original assignee: Shenzhen Fuman Electronic Group Co ltd
Current assignee: Fuman microelectronics Group Co.,Ltd.
Priority date: 2019-11-15
Filing date: 2019-11-15
Publication date: 2020-04-21
Anticipated expiration: 2029-11-15

Abstract

The utility model provides a blanking circuit of LED display screen, including configuration register, blanking enable module, combinational logic circuit and output drive circuit module; the output end of the configuration register is connected with the first input end of the blanking enabling module, the second input end of the blanking enabling module is connected with an external display clock signal, the third input end of the blanking enabling module is connected with an external instruction signal, the output end of the blanking enabling module is connected with the first input end of the combinational logic circuit, the second input end of the combinational logic circuit is connected with the channel of the LED chip, and the output end of the combinational logic circuit is connected to the output driving circuit module. The circuit improves the display effect and meets the requirement of high image quality.

Description

LED display screen blanking circuit and chip

Technical Field

The utility model relates to an integrated circuit technical field, concretely relates to blanking circuit and chip of LED display screen.

Background

The LED scanning screen has the advantages of high gray scale, wide visual angle, low working voltage, low power consumption, long service life, individuation customized shape and the like. Therefore, the method is widely used in the fields of commercial advertisement, information distribution and the like. However, in the conventional LED display screen, there are two defects (see fig. 1, exemplified by ROW1 and ROW 2):

① when two ROWs of display panel LEDs need to be lit up in ROW1 and ROW2, the ROW voltage drops slowly after ROW1 is lit up, and when the ROW scanning signal of ROW2 comes, the dark and bright of ROW1 will appear due to the pull-down of the column signals, which causes the upper ghost.

② when ROW1 needs to be turned on and ROW2 needs to be turned off in two ROWs of upper and lower display screen LEDs, after ROW1 is turned on, ROW2 rises slowly due to column voltage, and when a ROW scanning signal of ROW1 comes, it is found that ROW2 appears dark and bright to generate a lower ghost condition.

In the mainstream LED display control system at present, the LED gray scale brightness is generally dispersed to different sub-frames, and the gray scale is expressed by using the accumulated lighting time of the LED lamp in each frame period to display an image. The accumulated effective lighting time of the LED lamp corresponds to gray scale data of the corresponding pixel throughout the frame period.

In the conventional blanking technology, when each line of display scanning is finished, fixed pulse blanking is performed on a scanning array so as to achieve the purpose of removing ghost. Referring to fig. 2, in each line scan display, however, the column scan driver chips are not fully turned on. When the column scanning driving chip is pulled up and closed, a certain time delay exists, and further certain errors exist between the LED display brightness and actual gray scale data, and the larger the parasitic of the display screen array is, the larger the errors are. With the increasing quality of LED display, the error is not negligible.

SUMMERY OF THE UTILITY MODEL

Therefore, the utility model aims at providing a circuit and chip are blanked to LED display screen, circuit structure is simple, and is with low costs.

In a first aspect, a blanking circuit of an LED display screen comprises a configuration register, a blanking enabling module, a combinational logic circuit and an output driving circuit module;

the output end of the configuration register is connected with the first input end of the blanking enabling module, the second input end of the blanking enabling module is connected with an external display clock signal, the third input end of the blanking enabling module is connected with an external instruction signal, the output end of the blanking enabling module is connected with the first input end of the combinational logic circuit, the second input end of the combinational logic circuit is connected with the channel of the LED chip, and the output end of the combinational logic circuit is connected to the output driving circuit module.

Preferably, the output driving circuit module comprises an operational amplifier OP1, an operational amplifier OP2, a field effect transistor PM1, a field effect transistor NM1 and a current source Isink;

the source electrode of the field effect transistor PM1 is connected with a high level, the grid electrode of the field effect transistor PM1 is connected with a control signal, and the drain electrode of the field effect transistor PM1 is connected to the drain electrode of the field effect transistor NM1 through a forward connection light emitting diode L1;

the forward input end of an operational amplifier OP2 is connected with a reference voltage, the enable end of the operational amplifier OP2 is connected with a channel of an LED chip, the output end of the operational amplifier OP2 is connected with the grid of a field effect tube NM1, the source of the field effect tube NM1 is connected with the reverse input end of the operational amplifier OP2, the source of the field effect tube NM1 is grounded through a series connection of a current source Isink, the node between the drain of the field effect tube NM1 and the negative electrode of a light emitting diode L1 is connected with the output end of the operational amplifier OP1, the forward input end of the operational amplifier OP1 is connected with a blanking voltage, the reverse input end of the operational amplifier OP1 is connected with the output end of the operational amplifier OP 1.

Preferably, the combinational logic circuit comprises a shift register, an instruction decoding circuit, a memory and a PWM data division processing module;

the first input end of the shift register is connected with an external control signal, the second input end of the shift register and the first input end of the instruction decoding circuit are connected with an external data clock signal, and the second input end of the instruction decoding circuit is connected with an external input signal;

the first output end of the shift register is connected to the instruction decoding circuit, the second output end of the shift register is connected to the memory, and the third output end of the shift register is used as the data output end of the circuit;

the first output end of the instruction decoding circuit is connected to the memory, and the second output end of the instruction decoding circuit is connected to the configuration register;

a plurality of output ends of the memory are respectively connected to a plurality of first input ends of the PWM data division processing module;

the first output end of the configuration register is connected to the second input end of the PWM data division processing module, the second output end of the configuration register and the output ends of the PWM data division processing module are connected to the output driving circuit module, and the third input end of the PWM data division processing module is connected to an external display clock signal.

Preferably, the memory comprises an SRAM and a buffer;

the second output end of the shift register and the first output end of the instruction decoding circuit are connected to the SRAM, the output end of the SRAM is connected to the buffer, and a plurality of output ends of the buffer are respectively connected to a plurality of first input ends of the PWM data segmentation processing module.

In a second aspect, an LED display blanking chip,

the circuit comprises a configuration register, a blanking enabling module, a combinational logic circuit and an output driving circuit module;

Preferably, the memory comprises an SRAM and a buffer;

The utility model provides a circuit and chip are blanked to LED display screen, circuit structure is simple, and is with low costs, promotes the display effect, satisfies the high image quality requirement.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below. In the drawings, elements or portions are not necessarily drawn to scale.

Fig. 1 is a schematic diagram of a principle of an LED display screen provided in the background art.

Fig. 2 is a timing diagram of a conventional blanking method provided in the background art.

Fig. 3 is a structural diagram of a blanking circuit of an LED display panel according to an embodiment of the present invention.

FIG. 4 is a timing diagram of blanking associated with LED gray scale display data according to an embodiment of the present invention.

Fig. 5 is a circuit diagram of the output driving circuit module in fig. 3.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.

A blanking circuit of an LED display screen is disclosed, referring to FIG. 3, and comprises a configuration register, a blanking enabling module, a combinational logic circuit and an output driving circuit module;

Specifically, the blanking Enable module generates a blanking Enable signal BK Enable, which can be applied to all channels in the LED chip, according to the external display clock signal GCLK and the command signal Vsync, and transmits to the combinational logic circuit. The combinational logic circuit obtains blanking pulse signals BKn of all channels in the LED chip according to output data SPWMn of the LED chip, and transmits the blanking pulse signals BKn to the output driving circuit module; and when the channel in the LED chip is closed, the output driving circuit module performs pre-charging by utilizing the parasitics between the columns and the rows in the channel of the blanking pulse signal. The circuit is shown in fig. 4 in conjunction with the LED gray scale display data blanking timing diagram.

The circuit combines the LED gray scale display data to carry out real-time blanking control on different channels of the LED chip, has simple circuit structure and low cost, improves the display effect, meets the requirement of high image quality, and solves the ghost phenomenon of the LED display screen in the prior art.

Referring to fig. 5, the output driving circuit block includes an operational amplifier OP1, an operational amplifier OP2, a field effect transistor PM1, a field effect transistor NM1, and a current source Isink;

Specifically, in fig. 5, Vsync is a command signal, and one pulse appears per frame of an image for refreshing display data. GCLK is an external display clock signal; vghost is the blanking voltage; ROW is a ROW control signal, and setting 0 to ROW indicates scanning the current ROW; SPWMn is output data of the nth channel of the LED chip; vds is a reference voltage and is used for determining the Vds voltage of the constant-current NMOS tube; isink is a channel output constant current source; BKn is blanking pulse signal of nth channel; OUTN is the output port of the nth channel.

When the channel in the LED chip is closed, the output driving circuit module utilizes the parasitics between the rows and the columns in the channel of the blanking pulse signal to carry out pre-charging, thereby eliminating the LED brightness display error and the ghost phenomenon caused by the parasitics.

Specifically, the circuit writes the register configuration information and the LED gray scale data into the shift register in a serial shifting mode through the external control signal SDI and the external data clock signal DCLK. The command decoding circuit writes the shift register data into the configuration register or the memory by using N (N is an arbitrary integer) DCLK edges included in a high level in the external input signal LA as a command, and also generates a command signal Vsync signal. And the PWM data segmentation processing module is used for scattering the LED gray scale data into different grouped subframes. The blanking enable module generates a blanking enable signal. The output driving circuit module realizes a blanking function and provides a driving current.

Preferably, the memory comprises an SRAM and a buffer;

Specifically, the capacity of the SRAM can store two frames of LED grayscale data, and the LED grayscale data written in the previous frame is displayed while the LED grayscale data is stored, thereby forming a "ping-pong" operation. The BUFFER is used for prefetching the next line of LED gray scale data from the SRAM for buffering when the line feed or line display is finished.

For a brief description, the circuit provided by the embodiment of the present invention may refer to the corresponding content in the foregoing embodiments.

Example three:

a blanking chip of an LED display screen is provided,

Preferably, the memory comprises an SRAM and a buffer;

The chip combines the LED gray scale display data to carry out real-time blanking control on different channels of the LED chip, thereby improving the display effect, meeting the requirement of high image quality and solving the ghost phenomenon of the LED display screen in the prior art.

For a brief description, the chip provided by the embodiment of the present invention may refer to the corresponding content in the foregoing embodiments.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the scope of the embodiments of the present invention, and are intended to be covered by the claims and the specification.

Claims

1. A blanking circuit of an LED display screen is characterized by comprising a configuration register, a blanking enabling module, a combinational logic circuit and an output driving circuit module;

2. The blanking circuit of LED display screen according to claim 1,

the output driving circuit module comprises an operational amplifier OP1, an operational amplifier OP2, a field effect transistor PM1, a field effect transistor NM1 and a current source Isink;

3. The blanking circuit of LED display screen according to claim 1,

the combinational logic circuit comprises a shift register, an instruction decoding circuit, a memory and a PWM data segmentation processing module;

4. The blanking circuit of LED display screen of claim 3,

the memory comprises an SRAM and a buffer;

5. A blanking chip of an LED display screen is characterized in that,

6. The blanking chip of LED display screen according to claim 5,

7. The blanking chip of LED display screen according to claim 5,

8. The blanking chip of LED display screen according to claim 7,

the memory comprises an SRAM and a buffer;