CN210351093U - V-band power amplifying circuit - Google Patents
V-band power amplifying circuit Download PDFInfo
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- CN210351093U CN210351093U CN201921880840.6U CN201921880840U CN210351093U CN 210351093 U CN210351093 U CN 210351093U CN 201921880840 U CN201921880840 U CN 201921880840U CN 210351093 U CN210351093 U CN 210351093U
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Abstract
The utility model discloses a V wave band power amplification circuit. The bias circuit comprises a voltage polarity conversion chip LTC1983ES6-3 and an operational amplifier chip AD8616, wherein the voltage polarity conversion chip LTC1983ES6-3 carries out voltage polarity conversion on power supply input +5V into-3V, and then the-3V is input into the operational amplifier chip AD8616 to be isolated and divided, so that a Vg end of the power amplification chip gAPZ0038 supplied with direct current-2V is obtained. The utility model discloses a biasing circuit provides-2V, 2.5V and three kinds of DC supply voltage of 3.3V to power amplification chip gAPZ0038 to guaranteeing to provide earlier under-2V DC voltage to chip gAPZ0038, provide 2.5V and 3.3V DC voltage to chip gAPZ0038 again, protected chip gAPZ0038 effectively.
Description
Technical Field
The utility model relates to a millimeter wave communication field especially relates to a V wave band power amplification circuit.
Background
The signal amplification processing in the V-band (50 GHz-75 GHz) needs to fully consider the signal characteristics of this band, and particularly when a power amplification chip is used to amplify the signal in this band, a corresponding power supply voltage must be provided according to the characteristics of the chip used. In addition, since the signal transmission of this frequency band is mainly performed through a waveguide, power amplification of the signal of this frequency band is based on power amplification of an electrical signal. Therefore, it is desirable to provide a V-band power amplifier circuit with signal conversion, transmission matching, low noise figure, and high gain output.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the main technical problem who solves provides a V wave band power amplification circuit, solves current V wave band signal conversion, power amplification and provides the problem of different polarity voltage power supplies for V wave band power amplification chip.
In order to solve the technical problem, the utility model discloses a technical scheme provide a V wave band power amplifier circuit, including power amplification chip gAPZ0038 to and for power amplification chip gAPZ0038 provide-2V, 2.5V and 3.3V three kinds of direct current supply voltage's bias circuit, bias circuit includes voltage polarity conversion chip LTC1983ES6-3 and operational amplifier chip AD8616, voltage polarity conversion chip LTC1983ES6-3 carries out voltage polarity conversion to-3V with power supply input +5V, then inputs this-3V to operational amplifier chip AD8616 and keeps apart the partial pressure, obtains direct current-2V and supplies with the Vg end of power amplification chip gAPZ 0038.
Preferably, the bias circuit further comprises a terminal Vd1 for converting +5V of the power supply input into 3.3V through the first voltage reduction circuit and converting into 2.5V through the second voltage reduction circuit, wherein the first voltage reduction circuit and the second voltage reduction circuit respectively comprise a chip TLV1117, the 3.3V supplies a terminal Vd2 of a power amplification chip gAPZ0038, and the 2.5V supplies a terminal Vd1 of the power amplification chip gAPZ 0038.
Preferably, the first voltage reduction circuit comprises a first voltage reduction resistor and a second voltage reduction resistor which are arranged between a voltage regulation end and a voltage output end of the first voltage reduction chip TLV1117, the voltage regulation end of the first voltage reduction chip TLV1117 is respectively connected with the first voltage reduction resistor and the second voltage reduction resistor, the other end of the first voltage reduction resistor is grounded, and the other end of the second voltage reduction resistor is connected with the voltage output end of the first voltage reduction chip TLV 1117.
Preferably, the second voltage-reducing circuit comprises a third voltage-reducing resistor and a fourth voltage-reducing resistor arranged between a voltage-regulating end and a voltage output end of the second voltage-reducing chip TLV1117, the voltage-regulating end of the second voltage-reducing chip TLV1117 is respectively connected with the third voltage-reducing resistor and the fourth voltage-reducing resistor, the other end of the third voltage-reducing resistor is grounded, and the other end of the fourth voltage-reducing resistor is connected with the voltage output end of the second voltage-reducing chip TLV 1117.
Preferably, the power supply input +5V power supply is separated by 5V through the chip IRF7416 and is respectively provided for the first voltage reduction circuit and the second voltage reduction circuit.
Preferably, the control terminal of the chip LTC1983ES6-3 is directly electrically connected with the power supply access terminal, and an interconnection capacitor is connected in series between the positive electrode capacitor terminal and the negative electrode capacitor terminal of the chip LTC1983ES 6-3.
Preferably, a voltage output end of the chip LTC1983ES6-3 is electrically connected to a negative power end of the operational amplifier chip AD8616, and is further electrically connected to a voltage dividing circuit and then connected to a positive voltage input end of the operational amplifier chip AD8616, the voltage dividing circuit includes a first voltage dividing resistor and a second voltage dividing resistor, one end of the first voltage dividing resistor is electrically connected to the voltage output end of the chip LTC1983ES6-3, the other end of the first voltage dividing resistor is electrically connected to the positive voltage input end of the operational amplifier chip AD8616, and is further electrically connected to a second voltage dividing resistor, and the other end of the second voltage dividing resistor is grounded.
Preferably, the bias circuit further comprises a control circuit, the control circuit comprises an inverter chip SN74LVC1G04 and a control triode, a voltage output end of the chip LTC1983ES6-3 is electrically connected with an input end of the inverter chip SN74LVC1G04, an output end of the inverter chip SN74LVC1G04 is electrically connected with a base of the control triode after being connected in series with a current-limiting resistor, an emitter of the control triode is electrically connected with a negative power end of the operational amplifier chip AD8616, a +5V power supply input is connected in series with an inductor and a resistor and then is connected to a G end of the chip IRF7416, and a collector of the control triode is connected in series with another resistor and then is also connected to a G end of the chip IRF 7416.
The utility model has the advantages that: the utility model discloses a V wave band power amplification circuit. The bias circuit comprises a voltage polarity conversion chip LTC1983ES6-3 and an operational amplifier chip AD8616, wherein the voltage polarity conversion chip LTC1983ES6-3 carries out voltage polarity conversion on power supply input +5V into-3V, and then the-3V is input into the operational amplifier chip AD8616 to be isolated and divided, so that a Vg end of the power amplification chip gAPZ0038 supplied with direct current-2V is obtained. The utility model discloses a biasing circuit provides-2V, 2.5V and three kinds of DC supply voltage of 3.3V to power amplification chip gAPZ0038 to guaranteeing to provide earlier under-2V DC voltage to chip gAPZ0038, providing 2.5V and 3.3V DC voltage to chip gAPZ0038, protected chip gAPZ0038 effectively.
Drawings
Fig. 1 is a circuit schematic diagram of an embodiment of a V-band power amplifier circuit according to the present invention;
fig. 2 is a diagram of a bias circuit in another embodiment of a V-band power amplifier circuit according to the present invention;
fig. 3 is a first voltage step-down circuit diagram in another embodiment of the V-band power amplifying circuit according to the present invention;
fig. 4 is a second voltage-reducing circuit diagram in another embodiment of the V-band power amplifying circuit according to the present invention.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described in more detail with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It is to be noted that, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the V-band power amplifier circuit includes a power amplifier chip gmapz 0038, and a bias circuit for providing three dc supply voltages of-2V, 2.5V, and 3.3V to the power amplifier chip gmapz 0038.
As shown in FIG. 2, the bias circuit comprises a voltage polarity conversion chip LTC1983ES6-3 and an operational amplifier chip AD8616, wherein the voltage polarity conversion chip LTC1983ES6-3 converts the +5V power supply input into a-3V voltage in a voltage polarity manner, and then the-3V voltage is input into the operational amplifier chip AD8616 to be isolated and divided, so that a Vg end of a direct current-2V power supply amplification chip gAPZ0038 is obtained.
Specifically, a regulation and control end SHDN of the chip LTC1983ES6-3 is directly and electrically connected to a power supply access end VCC, the power supply access end VCC is connected to one end of a filter inductor L3, and the other end of the filter inductor L3 is connected to a +5V power supply input. And an interconnection capacitor C14 is connected between the positive capacitor terminal C + and the negative capacitor terminal C-of the chip LTC1983ES6-3 in series.
The voltage output end VOUT of the chip LTC1983ES6-3 is electrically connected with a negative power end V of the operational amplifier chip AD8616, and is also electrically connected with a voltage division circuit and then connected to a positive voltage input end + INA of the operational amplifier chip AD8616, the voltage division circuit comprises a first voltage division resistor R5 and a second voltage division resistor R6, one end of the first voltage division resistor R5 is electrically connected with the voltage output end VOUT of the chip LTC1983ES6-3, the other end of the first voltage division resistor R5 is electrically connected with the positive voltage input end + INA of the operational amplifier chip AD8616, and is also electrically connected with the second voltage division resistor R6, and the other end of the second voltage division.
The positive power source end V + of the operational amplifier chip AD8616 is grounded, the output end OUTA of the operational amplifier chip AD8616 is electrically connected with one end of the filter inductor L4, the other end of the filter inductor L4 outputs-2V voltage, the output end OUTA of the operational amplifier chip AD8616 is also electrically connected with one end of the filter capacitor C17 and one end of the filter capacitor C18 respectively, and the other end of the filter capacitor C17 and the other end of the filter capacitor C18 are both grounded.
Furthermore, the control terminal SHDN of the chip LTC1983ES6-3 is electrically connected with the capacitor C13 and then grounded, the ground terminal GND of the chip LTC1983ES6-3 is grounded, and the voltage output terminal VOUT of the chip LTC1983ES6-3 is also electrically connected with the capacitor C15 and then grounded.
The chip LTC1983ES6-3 converts the +5V voltage of the power supply input into-3V voltage for output, the output-3V voltage is input into the negative power end V-and the positive voltage input end + INA of the operational amplifier chip AD8616, and after the isolated voltage division of the operational amplifier chip AD8616, the output end OUTA of the operational amplifier chip AD8616 outputs-2V voltage for supplying to the Vg end of the power amplification chip gAPZ 0038.
In fig. 3 and 4, the bias circuit further includes a terminal Vd1 for converting +5V voltage of the power supply input into 3.3V voltage and 2.5V voltage respectively through the first voltage-reducing circuit and the second voltage-reducing circuit, wherein the first voltage-reducing circuit and the second voltage-reducing circuit respectively include a chip TLV1117, a terminal Vd2 for supplying 3.3V to the power amplification chip gAPZ0038, and a terminal Vd1 for supplying 2.5V to the power amplification chip gAPZ 0038.
In fig. 3, the first voltage-reducing circuit includes a first voltage-reducing resistor R1 and a second voltage-reducing resistor R2 disposed between the voltage-regulating terminal ADJ of the first voltage-reducing chip TLV1117 and the voltage output terminal Vout, the voltage-regulating terminal ADJ of the first voltage-reducing chip TLV1117 is connected to the first voltage-reducing resistor R1 and the second voltage-reducing resistor R2, respectively, the other terminal of the first voltage-reducing resistor R1 is grounded, and the other terminal of the second voltage-reducing resistor R2 is connected to the voltage output terminal Vout of the first voltage-reducing chip TLV 1117.
Preferably, the voltage regulating terminal ADJ of the first buck chip TLV1117 is connected to the capacitor C4 and then grounded, and the voltage output terminal Vout of the first buck chip TLV1117 is further connected to the capacitor C5 and then grounded.
Preferably, a filter network is connected to a voltage input terminal Vin of the first voltage-reducing chip TLV1117, the filter network includes a filter inductor L1 and a filter capacitor C3, the voltage input terminal Vin of the first voltage-reducing chip TLV1117 is connected to one end of the filter inductor L1, the other end of the filter inductor L1 is connected to a +5V voltage, and the voltage input terminal Vin of the first voltage-reducing chip TLV1117 is further connected to the filter capacitor C3 and then grounded.
The first voltage-reducing chip TLV1117 filters the +5V voltage of the power supply input through the filter network, divides the voltage of the first voltage-dividing circuit, and outputs a 3.3V direct-current power supply at the voltage output end Vout of the first voltage-reducing chip TLV1117, wherein the direct-current power supply is used for supplying the Vd2 end of the power amplification chip gAPZ 0038.
In fig. 4, the second voltage-reducing circuit includes a third voltage-reducing resistor R3 and a fourth voltage-reducing resistor R4 disposed between the voltage-regulating terminal ADJ and the voltage output terminal Vout of the second voltage-reducing chip TLV1117, the voltage-regulating terminal ADJ of the second voltage-reducing chip TLV1117 is respectively connected to the third voltage-reducing resistor R3 and the fourth voltage-reducing resistor R4, the other terminal of the third voltage-reducing resistor R3 is grounded, and the other terminal of the fourth voltage-reducing resistor R4 is connected to the voltage output terminal Vout of the second voltage-reducing chip TLV 1117.
Preferably, the voltage regulating terminal ADJ of the second buck chip TLV1117 is connected to the capacitor C7 and then grounded, and the voltage output terminal Vout of the second buck chip TLV1117 is further connected to the capacitor C8 and then grounded.
Preferably, a voltage input end Vin of the second voltage-reducing chip TLV1117 is connected to a filter network, the filter network includes a filter inductor L2 and a filter capacitor C6, the voltage input end Vin of the second voltage-reducing chip TLV1117 is connected to one end of the filter inductor L2, the other end of the filter inductor L2 is connected to a +5V voltage, and the voltage input end Vin of the second voltage-reducing chip TLV1117 is connected to the filter capacitor C6 and then grounded.
The second voltage-reducing chip TLV1117 filters the +5V voltage of the power supply input through the filter network, divides the voltage of the second voltage-dividing circuit, and outputs a 2.5V direct-current power supply at the voltage output end Vout of the second voltage-reducing chip TLV1117, wherein the direct-current power supply is used for supplying the Vd1 end of the power amplification chip gAPZ 0038.
Preferably, in fig. 2, the +5V voltage of the externally-connected power input is not directly supplied to the first voltage-dropping circuit and the second voltage-dropping circuit, but is isolated by the chip IRF7416 and then outputs a 5V voltage source to be supplied to the first voltage-dropping circuit and the second voltage-dropping circuit, respectively. The +5V power supply input voltage is electrically connected with one end of an inductor L5, and the other end of the inductor L5 is connected with a resistor R9 and then connected to the G end of the chip IRF 7416. The chip IRF7416 has its S terminals connected in common and to the capacitors C19 and C20, respectively, and then to ground. The D ends of the chip IRF7416 are connected in common, and are grounded after being respectively connected with the capacitor C21 and the capacitor C22. This is the output 5V voltage source electrically connected to the filter inductor L1 in fig. 3 and the filter inductor L2 in fig. 4, respectively, thereby powering the first and second buck circuits, respectively.
The bias circuit further comprises a control circuit, the control circuit comprises an inverter chip SN74LVC1G04 and a control triode MMBT3904, a voltage output end of the chip LTC1983ES6-3 is electrically connected with an input end A of the inverter chip SN74LVC1G04, an output end Y of the inverter chip SN74LVC1G04 is electrically connected with a base electrode of the control triode MMBT3904 after being connected with a current limiting resistor R7 in series, and a power supply end Vcc of the inverter chip SN74LVC1G04 is grounded.
The emitter of the control triode MMBT3904 is electrically connected with the negative power supply end V-of the operational amplifier chip AD8616, and the collector of the control triode MMBT3904 is also connected to the G end of the chip IRF7416 after being connected in series with another resistor R8.
When the chip LTC1983ES6-3 in FIG. 2 converts the +5V voltage of the power supply input into-3V voltage for output, the-3V voltage is input into the input end A of the inverter chip SN74LVC1G04, the output voltage of the output end Y of the inverter chip SN74LVC1G04 enables the control triode MMBT3904 to be conducted, the 5V voltage output by the D end of the chip IRF7416 is respectively provided for the first voltage reduction circuit and the second voltage reduction circuit, and the +2.5V voltage and the +3.3V voltage can be generated only when the-3V voltage output is ensured.
The utility model has the advantages that: the utility model discloses a V wave band power amplification circuit. The bias circuit comprises a voltage polarity conversion chip LTC1983ES6-3 and an operational amplifier chip AD8616, wherein the voltage polarity conversion chip LTC1983ES6-3 carries out voltage polarity conversion on input +5V into-3V, then the-3V is input into the operational amplifier chip AD8616 to carry out isolation and voltage division, and the obtained direct current-2V is supplied to a Vg end of the power amplification chip gAPZ 0038. The utility model discloses a biasing circuit provides-2V, 2.5V and three kinds of DC supply voltage of 3.3V to power amplification chip gAPZ0038 to guaranteeing to provide earlier under-2V DC voltage to chip gAPZ0038, providing 2.5V and 3.3V DC voltage to chip gAPZ0038, protected chip gAPZ0038 effectively.
The above only is the embodiment of the present invention, not limiting the scope of the present invention, all the equivalent structure changes made in the specification and the attached drawings or directly or indirectly applied to other related technical fields are included in the same principle as the present invention.
Claims (8)
1. A V-band power amplifying circuit is characterized by comprising a power amplifying chip gAPZ0038 and a bias circuit which provides three direct current supply voltages of-2V, 2.5V and 3.3V for the power amplifying chip gAPZ0038, wherein the bias circuit comprises a voltage polarity conversion chip LTC1983ES6-3 and an operational amplifier chip AD8616, the voltage polarity conversion chip LTC1983ES6-3 carries out voltage polarity conversion on a power supply input of +5V to be-3V, then the-3V is input to the operational amplifier chip AD8616 to be isolated and divided, and the direct current-2V is supplied to a Vg end of the power amplifying chip gAPZ 0038.
2. The V-band power amplifier circuit according to claim 1, wherein the bias circuit further comprises a terminal Vd1 for converting +5V of the power supply input to 3.3V by the first voltage-reducing circuit and 2.5V by the second voltage-reducing circuit, respectively, the first voltage-reducing circuit and the second voltage-reducing circuit respectively comprising a chip TLV1117, the 3.3V supplying a terminal Vd2 of the power amplifying chip gAPZ0038, and the 2.5V supplying a terminal Vd1 of the power amplifying chip gAPZ 0038.
3. The V-band power amplifying circuit according to claim 2, wherein the first voltage-reducing circuit comprises a first voltage-reducing resistor and a second voltage-reducing resistor arranged between a voltage-regulating end and a voltage output end of a first voltage-reducing chip TLV1117, the voltage-regulating end of the first voltage-reducing chip TLV1117 is connected with the first voltage-reducing resistor and the second voltage-reducing resistor respectively, the other end of the first voltage-reducing resistor is grounded, and the other end of the second voltage-reducing resistor is connected with the voltage output end of the first voltage-reducing chip TLV 1117.
4. The V-band power amplifying circuit according to claim 3, wherein the second voltage-reducing circuit comprises a third voltage-reducing resistor and a fourth voltage-reducing resistor arranged between a voltage-regulating end and a voltage output end of a second voltage-reducing chip TLV1117, the voltage-regulating end of the second voltage-reducing chip TLV1117 is connected with the third voltage-reducing resistor and the fourth voltage-reducing resistor respectively, the other end of the third voltage-reducing resistor is grounded, and the other end of the fourth voltage-reducing resistor is connected with the voltage output end of the second voltage-reducing chip TLV 1117.
5. The V-band power amplifying circuit according to claim 4, wherein the +5V power supply input is isolated by the chip IRF7416 to output a 5V voltage source to the first voltage-reducing circuit and the second voltage-reducing circuit respectively.
6. The V-band power amplifier circuit as claimed in claim 5, wherein the regulation terminal of the chip LTC1983ES6-3 is directly electrically connected to +5V of the power input, and an interconnection capacitor is connected in series between the positive and negative capacitor terminals of the chip LTC1983ES 6-3.
7. The V-band power amplifier circuit according to claim 6, wherein a voltage output terminal of the chip LTC1983ES6-3 is electrically connected to a negative power terminal of the operational amplifier chip AD8616, and is further electrically connected to a voltage divider circuit and then connected to a positive voltage input terminal of the operational amplifier chip AD8616, the voltage divider circuit comprises a first voltage divider resistor and a second voltage divider resistor, one end of the first voltage divider resistor is electrically connected to the voltage output terminal of the chip LTC1983ES6-3, the other end of the first voltage divider resistor is electrically connected to the positive voltage input terminal of the operational amplifier chip AD8616, and is further electrically connected to the second voltage divider resistor, and the other end of the second voltage divider resistor is grounded.
8. The V-band power amplifier circuit according to claim 7, wherein the bias circuit further comprises a control circuit, the control circuit comprises an inverter chip SN74LVC1G04 and a control transistor, a voltage output terminal of the chip LTC1983ES6-3 is electrically connected to an input terminal of the inverter chip SN74LVC1G04, an output terminal of the inverter chip SN74LVC1G04 is electrically connected to a base of the control transistor after being connected in series with a current-limiting resistor, an emitter of the control transistor is electrically connected to a negative power terminal of the operational amplifier chip AD8616, a power supply input +5V is connected in series with an inductor and a resistor and then is connected to a G terminal of the chip IRF7416, and a collector of the control transistor is connected in series with another resistor and then is also connected to a G terminal of the chip IRF 7416.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921880840.6U CN210351093U (en) | 2019-11-04 | 2019-11-04 | V-band power amplifying circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921880840.6U CN210351093U (en) | 2019-11-04 | 2019-11-04 | V-band power amplifying circuit |
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| CN210351093U true CN210351093U (en) | 2020-04-17 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111628738A (en) * | 2020-05-20 | 2020-09-04 | 电子科技大学 | V-waveband CMOS power amplifier |
-
2019
- 2019-11-04 CN CN201921880840.6U patent/CN210351093U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111628738A (en) * | 2020-05-20 | 2020-09-04 | 电子科技大学 | V-waveband CMOS power amplifier |
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Address after: Room 704-717, building C, Huirong Business Plaza, No. 26 Hefeng Road, Xinwu District, Wuxi City, Jiangsu Province, 214000 Patentee after: Jiangsu Yixin Aerospace Technology Co.,Ltd. Address before: 211135 2nd floor, unit B, 300 Zhihui Road, Qilin science and Technology Innovation Park, Jiangning District, Nanjing City, Jiangsu Province Patentee before: NANJING YIXIN AEROSPACE TECHNOLOGY Co.,Ltd. |
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