CN210348480U - Interface control circuit, chip and system - Google Patents
Interface control circuit, chip and system Download PDFInfo
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- CN210348480U CN210348480U CN201921568933.5U CN201921568933U CN210348480U CN 210348480 U CN210348480 U CN 210348480U CN 201921568933 U CN201921568933 U CN 201921568933U CN 210348480 U CN210348480 U CN 210348480U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model provides an interface control circuit, chip and system, interface control circuit includes: a processor, a latch, a first device, and a second device; the processor is connected with the latch and used for outputting a latch control signal to the latch, and the latch is used for determining whether the state of the latch is a latch state or a holding state according to the latch control signal; the processor is provided with a first interface, the first interface is respectively connected with the latch and the second equipment, and the latch is connected with the first equipment; and in the latch state, the latch is used for holding a state signal of the first device, and the processor exchanges data with the second device. The embodiment of the utility model provides a need not to increase extension chip and can realize same interface on a plurality of equipment sharing treater, be the interface control circuit of not only simple but also low-power consumption.
Description
Technical Field
The utility model relates to the technical field of circuits, especially, relate to an interface control circuit, chip and system.
Background
In embedded systems, the processor typically requires a connection interface to enable data exchange between the processor and the device module through the interface. With the increase of the complexity of the embedded system, the number of the device modules to be connected by the processor is increased, and correspondingly, the number of the interfaces to be connected by the processor is increased, when the number of the interfaces to be connected by the processor is not enough, the number of the interfaces is usually increased,
in the prior art, the number of interfaces is usually increased by adding an expansion chip, however, the addition of the expansion chip not only makes the hardware cost higher, but also makes the control logic of the interface control circuit more complex, which easily causes extra power consumption and results in larger power consumption.
SUMMERY OF THE UTILITY MODEL
The utility model provides an interface control circuit, chip and system has solved the problem that current interface control circuit hardware cost is higher, control logic is comparatively complicated.
In a first aspect, the utility model discloses an interface control circuit, interface control circuit includes: a processor, a latch, a first device, and a second device; wherein the content of the first and second substances,
the processor is connected with the latch and used for outputting a latch control signal to the latch, the latch is used for determining the state of the latch according to the latch control signal, and the state of the latch comprises a latch state and a holding state;
the processor is provided with a first interface, the first interface is respectively connected with the latch and the second equipment, and the latch is connected with the first equipment;
in the latch state, the processor exchanges data with the first device, in the hold state, the latch is used for holding a state signal of the first device, and the processor exchanges data with the second device.
Optionally, the latch control signal comprises a low level signal and a high level signal;
when the latch control signal is switched from a low-level signal to a high-level signal, the latch is in a latch state;
when the latch control signal is other than a signal switched from a low level to a high level, the latch is in a hold state.
Optionally, the latch comprises: an input terminal and an output terminal;
the input end is connected with the first interface and used for inputting a state signal of the first equipment;
the output end is connected with the first device, the input end is connected with the output end under the condition that the latch is in a latching state, the output end is used for storing the state signal input by the input end, the input end is isolated from the output end under the condition that the latch is in a holding state, and the output end is used for holding the state signal on the output end.
Optionally, the latch comprises: a first power receiving terminal and a ground terminal;
the first power supply receiving end is used for accessing a working power supply of the latch;
the grounding end is used for grounding.
Optionally, the processor comprises: the second power supply receiving end is used for accessing a working power supply of the processor;
the first power supply receiving end is connected with the second power supply receiving end and used for providing working voltage for the latch through a working power supply of the processor.
Optionally, the interface control circuit further includes: and the second interface is respectively connected with the processor and the latch, and is used for outputting the latch control signal to the latch.
Optionally, the first interface and the second interface are general purpose input/output GPIO interfaces.
Optionally, the processor is a Loongson processor.
In a second aspect, the utility model also discloses an interface control chip, including above-mentioned interface control circuit.
The third aspect, the utility model also discloses an interface control system, including above-mentioned interface control chip.
The utility model discloses a following advantage:
the embodiment of the utility model provides an among the interface control circuit, the treater is connected with the latch for to latch control signal is exported to the latch, the latch is used for according to latch control signal, confirms the latch state, the latch state includes latch state and holding state; the processor is provided with a first interface, the first interface is respectively connected with the latch and the second equipment, and the latch is connected with the first equipment; in the latch state, the processor exchanges data with the first device, in the hold state, the latch is used for holding a state signal of the first device, and the processor exchanges data with the second device. The embodiment of the utility model provides an in, through the mode that sets up the latch, make first equipment with second equipment can share first interface on the treater reduces the interface quantity of connecting on the treater, not only the circuit is simple, does not need extra consumption expense moreover, is an interface control circuit of not only simple but also low-power consumption.
Drawings
Fig. 1 is a circuit diagram of an interface control circuit according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a latch according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a processor according to the present invention;
FIG. 4 is a schematic diagram of a processor and latch connection according to the present invention;
fig. 5 is a circuit diagram of another latch provided by an embodiment of the present invention.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.
The embodiment of the utility model provides an interface control circuit, figure 1 shows the utility model provides a pair of interface control circuit's circuit diagram is provided.
As shown in fig. 1, the interface control circuit may include: a processor 10, a latch 11, a first device 13, and a second device 14; the processor 10 is connected to the latch 11, and is configured to output a latch control signal to the latch 11. The latch 11 may be configured to determine a latch state according to the latch control signal, where the latch state includes a latch state and a hold state; the processor 10 may be provided with a first interface 12, the first interface 12 is respectively connected with the latch 11 and the second device 14, and the latch 11 is connected with the first device 13; in the latched state, the processor 10 exchanges data with the first device 13, and in the held state, the latch 11 may be used to hold a status signal of the first device 13, and the processor 10 exchanges data with the second device 14. The embodiment of the present invention provides an embodiment, through the mode of setting up latch 11 between first interface 11 of treater 10 and first equipment 13 for first equipment 13 and second equipment 14 can share first interface 12, reduce the interface quantity of connecting on treater 10, and not only the circuit is simple, does not need extra consumption expense moreover, is an interface control circuit of not only simple but also low-power consumption.
Optionally, the first interface is an interface used by the processor to transmit data to be exchanged to the first device and/or the second device.
In the embodiment of the present invention, when the first device 13 needs to switch states, for example, when the first device 13 is an indicator light, and the first device 13 needs to switch from an off state to an on state, the processor 10 may output a latch control signal to the latch 11, and control the latch state of the latch 11 to switch to the latch state; in the case where the latch 11 is in the latch state, the latch 11 may transmit a state signal transmitted by the processor 10 to the first device 14, so that the first device 14 realizes the state switching. After the first device 13 completes the state switching, the latch state of the latch 11 may be switched to the holding state by the processor 10 outputting the latch control signal to the latch 11, and the state signal of the first device 13 is held on the latch 11, so that the lighting state of the first device 13 may be maintained. Since the second device 14 is connected to the processor 10 via the first interface 12, the processor 10 may be used for exchanging data with the second device 14 via the first interface 12 in case the latch 11 is in the hold state. That is, the first device 13 and the second device 14 can share the first interface 12 to exchange data with the processor 10, and the number of interfaces connected to the processor 10 is reduced.
Specifically, the first device 13 may be a device module that maintains the same state for a longer time. Such as indicator lights, alarms, etc. The second device 14 may be any device in the system that requires data to be exchanged with the processor 10. In practical applications, a person skilled in the art may set the specific types of the first device 13 and the second device 14 according to actual needs, and the embodiment of the present invention is not limited to the specific types of the first device 13 and the second device 14.
In an optional embodiment of the present invention, the latch control signal may include a low level signal and a high level signal; when the latch control signal is switched from a low-level signal to a high-level signal, the latch 11 is in a latch state; in the case where the latch control signal is switched from a low level signal to a high level signal, the latch 11 is in a hold state.
Specifically, the case where the latch control signal is switched from a low-level signal to a high-level signal may include: the latch control signal is switched from a high level signal to a low level signal, or the latch control signal is kept as a high level signal.
For example, when the data exchange between the processor and the first device is a status signal, when the status signal transmitted by the processor 10 needs to be transmitted to the first device 13 so that the first device 13 switches the status, the latch control signal output from the processor 10 to the latch 11 may be switched from a low level signal to a high level signal to control the latch status of the latch 11 to be switched to the latch status. After the first device 13 completes the state switching, the latch control signal output by the processor 10 to the latch 11 may be switched from a high level signal to a low level signal, or may be maintained in a high level state/low level state, the latch state of the latch 11 is switched to a holding state, and the state signal of the first device 13 is held on the latch 11, so that the state of the first device 13 may be maintained.
With the latch 11 in the hold state, the processor 10 can exchange data with the second device 14 through the first interface 12, so that the first interface 12 can be shared by the first device 13 and the second device 14, reducing the number of interfaces connected to the processor 10.
Fig. 2 shows a circuit diagram of a latch according to an embodiment of the present invention. As shown in fig. 2, the latch 11 may include: an input 111 and an output 112; the input end 111 is connected to the first interface 12, and may be used to input a status signal of the first device 13; the output 112 is connected to the first device 13, the input 111 and the output 112 are connected in the case that the latch 11 is in the latch state, the output 112 can be used for storing the status signal input by the input 111, the input 111 and the output 112 are isolated in the case that the latch 11 is in the hold state, and the output 112 can be used for holding the status signal on the output 112, so that the status of the first device 13 connected to the output 112 is maintained. The data exchange between the processor and the first device is the exchange of the status signal of the first device between the processor and the first device.
In practical applications, in case the latch 11 is in the hold state, the first device 13 can hold the state since the output 112 of the latch 11 can hold the state signal of the first device 13 on the output 112. Furthermore, since the input 111 and the output 112 of the latch 11 may be isolated in case the latch 11 is in the hold state, the first interface 12 connected to the input 111 and the first device 13 connected to the output 112 may be isolated accordingly (i.e. isolation between the first interface 12 and the first device), and in case the first interface 12 is used for data exchange between the processor 10 and the second device 14, the state signal at the output 112 of the latch 11 is not affected. In this way, the first device 13 and the second device 14 can share the first interface 12, reducing the number of interfaces connected to the processor 10.
Optionally, the latch 11 may further include: a first power receiving terminal 113 and a ground terminal 114; the first power receiving terminal 113 may be used to access the operating power of the latch 11; the ground terminal 114 may be used for grounding.
Referring to fig. 3, a schematic structural diagram of a processor according to the present invention is shown, as shown in fig. 3, a processor 10 may further include a first conductive layer
A second power receiving end 101, wherein the second power receiving end 101 may be configured to access an operating power of the processor 10.
Referring to fig. 4, which shows a schematic diagram of a processor and latch connection structure according to the present invention, as shown in fig. 4, a first power receiving terminal 113 of the latch 11 is connected to a second power receiving terminal 101 of the processor 10, so as to provide an operating voltage for the latch 11 through an operating power supply of the processor 10.
Specifically, when the first power receiving terminal 113 is connected to the second power receiving terminal 101, the operating voltage may be provided to the latch 11 through the operating power supply of the processor 10, that is, the latch 11 and the processor 10 may share the operating power supply of the processor 10, so that the integration level of the interface control circuit may be improved, and the interface control circuit may be further simplified.
Optionally, the interface control circuit may further include: a second interface 15; the second interface 15 is located on the processor 10 for connecting the processor 10 to the latch 11. In practical applications, the processor 10 may output a latch control signal to the latch 11 through the second interface 15; the second interface 15 is connected to an input 111 of the latch 11.
Specifically, the first interface 12 and the second interface 15 may be General-purpose input/output (GPIO) interfaces. Because the GPIO interface has the advantages of low power consumption, small package, low cost, and simple wiring, the interface package circuit can be made to have the advantages of low power consumption, small package, low cost, flexible light control, and simple wiring when the first interface 12 and the second interface 15 are both GPIO interfaces.
In a specific application, the latch 11 can be used for buffering, so that the problem of driving is solved, and the problem that one GPIO interface can output and input can be solved. The latches may be latches without enable control and latches with enable control. Illustratively, the model of the latch 11 may be SN74ALVCH 16373.
It is understood that the latch 11 may also be other devices capable of implementing a latching function, and the embodiment of the present invention is not particularly limited to the latch 11.
In a particular application, the processor 10 may be a Loongson processor. The Loongson processor may be coupled to the latch 11 for outputting a latch control signal to the latch 11 to control the latch state of the latch 11. In the case that the latch 11 is in the latch state, the latch 11 may transmit a status signal sent by the Loongson processor to the first device 14, so as to implement the state switching of the first device 14. After the first device 13 completes the state switching, the latch control signal may be output to the latch 11 by the Loongson processor, the latch state of the latch 11 may be switched to the hold state, and the state signal of the first device 13 may be held on the output 112 of the latch 11, so that the state of the first device 13 may be maintained. Since the second device 14 is connected to the Loongson processor through the first interface 12, the Loongson processor can be used for data exchange with the second device 14 through the first interface 12 with the latch 11 in the hold state. That is, in the case where the latch 11 is in the hold state, the first device 13 and the second device 14 can share the first interface 12, reducing the number of interfaces connected to the Loongson processor.
Referring to fig. 5, which shows a schematic structural diagram of another latch of the present invention, as shown in fig. 5, the input end 111 of the latch 11 may be provided with a plurality of input pins: pin D1-pin D9, the output 112 may have multiple output pins: pin Q1-pin Q8. In practical application, the condition that each pin is connected to the interface control circuit can be determined according to practical conditions.
Specifically, in the latch shown in fig. 5, at the input end 111 side, the pin D1, the pin D2, the pin D3, and the pin D4 may be connected to the first interface 12, respectively, the pin D5, the pin D6, the pin D7, and the pin D8 may be suspended to access other devices according to actual needs, and the pin D9 may be connected to the second interface 15 on the processor 10. At the output end 112, the pin Q1, the pin Q2, the pin Q3, and the pin Q4 may be connected to the first device 13, respectively, and the pin Q5, the pin Q6, the pin Q7, and the pin Q8 may be suspended to access other devices according to actual needs.
It is understood that, in practical applications, the number of the pins of the input end 111, the number of the pins of the output end 112, and the number of the ground ends 114 may be set according to practical situations, and the present invention is not limited thereto.
To sum up, the embodiment of the present invention provides an interface control circuit including following advantage at least:
the embodiment of the utility model provides an among the interface control circuit, the treater is connected with the latch for to latch control signal is exported to the latch, the latch is used for according to latch control signal, confirms the latch state, the latch state includes latch state and holding state; the processor is provided with a first interface, the first interface is respectively connected with the latch and the second equipment, and the latch is connected with the first equipment; in the latch state, the processor exchanges data with the first device, in the hold state, the latch is used for holding a state signal of the first device, and the processor exchanges data with the second device. The embodiment of the utility model provides an in, through the first interface of treater with set up the mode of latch between the first equipment, make first equipment with the second equipment can share first interface reduces the interface quantity of connecting on the treater, not only the circuit is simple, does not need extra consumption expense moreover, is the interface control circuit of not only simple but also low-power consumption.
In the concrete application, the embodiment of the utility model provides a still provides an interface control chip, including above-mentioned interface control circuit.
The embodiment of the utility model provides a still provide an interface control system, include: the interface control chip.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The interface control circuit, the interface control chip and the interface control system provided by the present invention are introduced in detail, and specific examples are applied to explain the principle and the implementation of the present invention, and the explanation of the above embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.
Claims (10)
1. An interface control circuit, the interface control circuit comprising: a processor, a latch, a first device, and a second device; wherein the content of the first and second substances,
the processor is connected with the latch and used for outputting a latch control signal to the latch, the latch is used for determining the state of the latch according to the latch control signal, and the state of the latch comprises a latch state and a holding state;
the processor is provided with a first interface, the first interface is respectively connected with the latch and the second equipment, and the latch is connected with the first equipment;
in the latch state, the processor exchanges data with the first device, in the hold state, the latch is used for holding a state signal of the first device, and the processor exchanges data with the second device.
2. The interface control circuit of claim 1, wherein the latch control signal comprises a low level signal and a high level signal;
when the latch control signal is switched from a low-level signal to a high-level signal, the latch is in a latch state;
when the latch control signal is other than a signal switched from a low level to a high level, the latch is in a hold state.
3. The interface control circuit of claim 1, wherein the latch comprises: an input terminal and an output terminal;
the input end is connected with the first interface and used for inputting a state signal of the first equipment;
the output end is connected with the first device, the input end is connected with the output end under the condition that the latch is in a latching state, the output end is used for storing the state signal input by the input end, the input end is isolated from the output end under the condition that the latch is in a holding state, and the output end is used for holding the state signal on the output end.
4. The interface control circuit of claim 1, wherein the latch comprises: a first power receiving terminal and a ground terminal;
the first power supply receiving end is used for accessing a working power supply of the latch;
the grounding end is used for grounding.
5. The interface control circuit of claim 4, wherein the processor comprises: the second power supply receiving end is used for accessing a working power supply of the processor;
the first power supply receiving end is connected with the second power supply receiving end and used for providing working voltage for the latch through a working power supply of the processor.
6. The interface control circuit according to any one of claims 1 to 5, wherein a second interface is further provided on the processor, the second interface is connected to the latch, and the second interface is configured to output the latch control signal to the latch.
7. The interface control circuit of claim 6, wherein the first interface and the second interface are General Purpose Input Output (GPIO) interfaces.
8. The interface control circuit of claim 6, wherein the processor is a Loongson processor.
9. An interface control chip comprising the interface control circuit of any one of claims 1 to 8.
10. An interface control system, comprising: the interface control chip of claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921568933.5U CN210348480U (en) | 2019-09-19 | 2019-09-19 | Interface control circuit, chip and system |
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| CN201921568933.5U CN210348480U (en) | 2019-09-19 | 2019-09-19 | Interface control circuit, chip and system |
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| CN210348480U true CN210348480U (en) | 2020-04-17 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113359551A (en) * | 2021-06-03 | 2021-09-07 | 浙江大华技术股份有限公司 | Switch control circuit and electronic equipment |
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2019
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113359551A (en) * | 2021-06-03 | 2021-09-07 | 浙江大华技术股份有限公司 | Switch control circuit and electronic equipment |
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Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |