CN210348365U - Domestic binary star server mainboard based on Shenwei 1621 processor architecture - Google Patents
Domestic binary star server mainboard based on Shenwei 1621 processor architecture Download PDFInfo
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- CN210348365U CN210348365U CN201921897813.XU CN201921897813U CN210348365U CN 210348365 U CN210348365 U CN 210348365U CN 201921897813 U CN201921897813 U CN 201921897813U CN 210348365 U CN210348365 U CN 210348365U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The utility model discloses a domestic binary star server mainboard based on explain in a year and ask 1621 treater framework, which comprises a mainboard, the mainboard includes explain in a year and ask 1621 chip, XL710 chip, FLASH, PCIE extension chip, PCIE extension PEX8748 chip, CPLD communication module, TUSB7340 host controller and BMC card. The utility model discloses in, the utility model discloses an used "L" type version type, version type overall arrangement is more reasonable for it is unreasonable to solve prior art plate-type overall arrangement, and the CPU heat dissipation is poor, consequently need use the water-cooling, or add more powerful fan in the quick-witted case, has raised quick-witted case cost, has wasted the energy, has increased occupation space, and domestic CPU has been used in this application: the Shenwei 1621 chip is good in safety and strong in reliability, is used for solving the problem that an Intel framework is mostly used in the prior art, and the safety and reliability of data are difficult to guarantee, and the ICH2 chip is not used in the design, so that the cost of the whole board is reduced, the structure of the whole board is optimized, and the operation stability is improved.
Description
Technical Field
The utility model belongs to the technical field of server mainboard scope, specifically be a domestic binary star server mainboard based on explain year's worth 1621 treater framework.
Background
Under the background that network and information security are upgraded to national strategy, the security performance requirements for server products are higher and higher;
prior art all need cooperate ICH2 nest plate when designing Shenwei 1621 chip, this has just brought the mainboard with high costs, the unstable and big scheduling problem of heat dissipation of operation, current mainboard of the same type often is difficult to reach online debugging and the installation of multiunit interface, prior art plate shape overall arrangement is unreasonable, the CPU heat dissipation is poor, consequently, need use the water-cooling, or add more powerful fan in the quick-witted case, the quick-witted case cost has been raised, the energy has been wasted and occupation space has been increased, prior art uses Intel framework mostly, the security and the reliability of data are difficult to the guarantee.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a: in order to solve the problems, a domestic binary star server mainboard based on the Shenwei 1621 processor architecture is provided.
The utility model adopts the technical scheme as follows:
a domestic binary star server mainboard based on a Shenwei 1621 processor architecture comprises a mainboard, wherein the mainboard comprises a Shenwei 1621 chip, an XL710 chip, a FLASH, a PCIE expansion chip, a PCIE expansion PEX8748 chip, a CPLD communication module, a TUSB7340 host controller and a BMC card;
the Shenwei 1621 chip is a core cpu of a mainboard, 8 DDR3 slots are arranged on the mainboard, and DDR3 memory banks are built in the 8 DDR3 slots and used for providing a memory space larger than or equal to 32GB for the Shenwei 1621 chip;
the Shenwei 1621 chip is connected with the XL710 chip through a PCIE3.0x8 interface, and four paths of 10 GESFPs and optical modules are led out from a back plate of the XL710 chip to provide an interface for optical fiber communication for a mainboard;
the Shenwei 1621 chip is connected with an external FLASH through an SPI interface, and the FLASH provides a storage medium of related configuration data for the Shenwei 1621 chip;
the Shenwei 1621 chip is connected with a PCIE expansion PEX8748 chip through a PCIE3.0x8 interface, and the PCIE expansion PEX8748 chip provides expansion for the PCIE interface of the Shenwei 1621 chip;
the PCIE extension PEX8748 chip extends a path of PCIE3.0x4 to connect to the PEX8713, and the PCIE3.0x4 is used for communication.
The power-on time sequence of the mainboard is provided with a CPLD large-scale integrated circuit and is controlled by the CPLD large-scale integrated circuit;
the backboard leading-out interface of the mainboard further comprises a VGA port, a serial port and an RJ45 gigabit network port.
The Shenwei 1621 chip is provided with a JTAG, and the JTAG is connected with the main board leading port in an opposite mode and used for internal test of the Shenwei 1621 chip.
The PCIE extended PEX8748 chip leads out a path of PCIE3.0x8 and a path of PCIE3.0x16 to a PCIE extended chip connector of the mainboard, and the PCIE extended chip, the PCIE extended PEX8748 chip and the two paths of PCIE connection connector bases.
Wherein, a path of PCIE2.0x2 to 88SE9230 is led out from the PCIE extension PEX8748 chip, and the 88SE9230 is converted into two paths of SATA3.0 and two paths of m.2 to the motherboard.
The Peripheral Component Interconnect Express (PCIE) extension PEX8748 chip leads out a path of PCIE2.0x1 to TUSB7340 host controller, USB3.0 and USB2.0 are arranged on the TUSB7340 host controller, the TUSB7340 host controller transfers out one path of the USB3.0 to a front panel, the other two paths of the USB3.0 to a back panel and the other path of the USB2.0 to a BMC card, and the BMC card is in USB communication with the application 1621 chip.
The BMC card is connected to a mainboard through a DDR3SODIMM and is communicated with the Shenwei 1621 chip through an I2C and an SPI interface.
To sum up, owing to adopted above-mentioned technical scheme, the beneficial effects of the utility model are that:
1. the utility model discloses in, the utility model discloses an used "L" type version type, version type overall arrangement is more reasonable for it is unreasonable to solve prior art plate-type overall arrangement, and the CPU heat dissipation is poor, consequently need use the water-cooling, or add more powerful fan in the quick-witted case, has raised quick-witted case cost, has wasted the energy, has increased occupation space, and domestic CPU has been used in this application: the Shenwei 1621 chip is good in safety and strong in reliability, and is used for solving the problems that an Intel architecture is mostly used in the prior art, the safety and reliability of data are difficult to guarantee, an ICH2 nest plate is not used in the design, the cost of the whole board is reduced, the whole board structure is optimized, and the operation stability is improved.
Drawings
Fig. 1 is a schematic diagram of the structure of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
Referring to fig. 1, a domestic binary star server motherboard based on a shenwei 1621 processor architecture includes a motherboard, where the motherboard includes a shenwei 1621 chip, an XL710 chip, a FLASH, a PCIE expansion chip, a PCIE expansion PEX8748 chip, a CPLD communication module, a TUSB7340 host controller, and a BMC card, the shenwei 1621 chip is a core cpu of the motherboard, and the motherboard may be externally connected with 6 hard disks or 12 hard disks, and may be compatible with 2.5 inches or 3.5 inches hard disks when being connected with 6 hard disks; when 12 hard disks are connected, a 2.5-inch hard disk can be connected. The mainboard supports hot plug, a single mainboard can control half of the fan of the chassis, the fan can be hot plugged, the mainboard comprises a chassis lug socket, a USB (universal serial bus) and a control button can be connected, 8 DDR3 slots are arranged on the mainboard, DDR3 memory banks are arranged in the 8 DDR3 slots and are used for providing a memory space which is more than or equal to 32GB for the Shenwei 1621 chip, the 8 DDR3 slots of the mainboard are divided into 4 groups which are respectively arranged on two sides of the CPU and are parallel to an air duct, the Layout is favorable for the heat dissipation of a Layout routing and the memory banks, the Shenwei 1621 chip is connected with an XL710 chip through a PCIE3.0x8 interface, four paths of 10 GESFPs and optical modules are led out from the back plate of the XL710 chip, the Shenwei 1621 chip is connected with an external FLASH interface through a JTAG interface, the FLASH is used for providing a storage medium of related configuration data for the Shenwei 1621 chip, the JTAG chip is provided with JTAG and is oppositely connected with the mainboard leading, the detection device is used for internal test of the Shenwei 1621 chip, the Shenwei 1621 chip is connected with a PCIE expansion PEX8748 chip through a PCIE3.0x8 interface, and the PCIE expansion PEX8748 chip provides expansion for the PCIE interface of the Shenwei 1621 chip; one path of PCIE3.0x8 and one path of PCIE3.0x16 are led out from the PEX8748 chip to a PCIE extended chip connector of the mainboard, the PCIE extended chip, the PCIE extended PEX8748 chip and two paths of PCIE connecting plug-in seats are led out from the PCIE extended PEX8748 chip, one path of PCIE2.0x2 to 88SE9230 is led out from the PCIE extended PEX8748 chip, 88SE9230 is converted into two paths of SATA3.0 and two paths of M.2 to the mainboard, one path of PCIE2.0x1 is led out from the PCIE extended PEX8748 chip to a TUSB7340 host controller, USB3.0 and USB2.0 are arranged on the TUSB7340 host controller, the TUSB7340 host controller is converted into one path of USB3.0 to the front panel, the front panel of the mainboard can be connected with 6.5 inches or 3.5 inches of hard disks, the mainboard has more numbers, the other two paths of USB3.0 to the back panel, a four paths of optical fiber communication ports, one path of USB3.0 communication ports and one path of USB3.0 communication ports can be connected with a plurality of USB BMC 3.2 external USB interface, a plurality of USB communication devices, one path of USB3.0, a plurality of USB, The SPI interface is communicated with a Shenwei 1621 chip, the PCIE extension PEX8748 chip is extended to form a path of PCIE3.0x4 to be connected with the PEX8713, the PCIE3.0x4 is used for communication, a CPLD large-scale integrated circuit is arranged on the power-on time sequence of the mainboard and is controlled by the CPLD large-scale integrated circuit, the backboard leading-out interface of the mainboard also comprises a VGA port, a serial port and an RJ45 kilomega network port,
the first embodiment is as follows: the mainboard comprises a Shenwei 1621 chip, an XL710 chip, a FLASH, a PCIE expansion chip, a PCIE expansion PEX8748 chip, a CPLD communication module, a TUSB7340 host controller and a BMC card, wherein the Shenwei 1621 chip is a core cpu of the mainboard, the mainboard can be externally connected with 6 hard disks or 12 hard disks, and can be compatible with 2.5-inch or 3.5-inch hard disks when being connected with 6 hard disks; when 12 hard disks are connected, a 2.5-inch hard disk can be connected. This mainboard supports the hot plug, and the fan of single steerable quick-witted case half, fan hot plug, mainboard contain quick-witted case otic placode socket, joinable otic placode USB and control button, and the mainboard has used "L" type version in this application, and the version is overall arrangement more reasonable. In the prior art, the plate-shaped Layout is unreasonable, the CPU has poor heat dissipation, so that water cooling is needed, or a fan with higher power is added in the chassis, the chassis cost is raised, energy is wasted, and the occupied space is increased, 8 DDR3 slots are arranged on a mainboard, 8 DDR3 slots are internally provided with DDR3 memory banks for providing a memory space larger than or equal to 32GB for Shenwei 1621 chips, the 8 DDR3 slots of the mainboard are divided into 4 groups which are respectively arranged on two sides of the CPU and are parallel to an air duct, the Layout is favorable for heat dissipation of a Layout routing and the memory banks, the Shenwei 1621 chips are connected with an XL710 chip through a PCIE3.0x8 interface, four paths of 10 GESFPs and optical modules are led out from a back plate of the XL710 chip for providing an optical fiber communication interface for the mainboard, the Shenwei 1621 chips are connected with external FLASH through SPI interfaces, the FLASH is used for providing storage media for configuring data for the Shenwei 1621 chips, the Shenwei 1621 chips are connected with PCIE extension PEX8748 chips through PCIE3.0, the application uses a domestic CPU: the Shenwei 1621 chip has good safety and strong reliability. In the prior art, an Intel architecture is mostly used, the safety and reliability of data are difficult to guarantee, and a PCIE extended PEX8748 chip provides expansion for a PCIE interface of a Shenwei 1621 chip;
example two: the PCIE expansion PEX8748 chip expands a path of PCIE3.0x4 to be connected with the PEX8713, the PCIE3.0x4 is used for communication, a CPLD large-scale integrated circuit is arranged on the power-on timing sequence of the mainboard and is controlled by the CPLD large-scale integrated circuit, a backboard leading-out interface of the mainboard further comprises a VGA port, a serial port and an RJ45 kilomega network port, the Shenwei 1621 chip is provided with a JTAG, the JTAG and the mainboard leading-out port are oppositely connected and used for internal test of the Shenwei 1621 chip, the PEX8748 chip leads out a path of PCIE3.0x8 and a path of PCIE3.0x16 to a PCIE expansion chip connector of the mainboard, the PCIE expansion chip, the PCIE expansion PEX8748 chip and two paths of PCIE connector seats, the PCIE expansion PEX8748 chip leads out a path PCIE2.0x2 to an SE9230, the PCIE 88 xSE 30 is converted into two paths of SATA3.0 and SATA.2 to the mainboard, the PCIE expansion PEX8748 chip is led out from a path of PCIE 731 to a USB host, the USB host 730, the USB control mainboard is arranged on the USB host 733.0xSB 3, the USB backplane, the USB 3.0xSB 3, and a path of USB2.0 is communicated with a BMC card, the BMC card is communicated with a USB of the Shenwei 1621 chip, the BMC card is connected into the mainboard through a DDR3SODIMM and is communicated with the Shenwei 1621 chip through an I2C interface and an SPI interface, an ICH2 set sheet is not used in the design, the cost of the whole board is reduced, the structure of the whole board is optimized, and the stability of operation is improved. In the prior art, ICH2 nest plates are required to be matched when a Shenwei 1621 chip is designed; this has brought the mainboard with high costs, the operation is unstable, the heat dissipation capacity scheduling problem greatly.
Example three: the PEX8748 chip leads out one PCIE3.0x8 chip and one PCIE3.0x16 chip to a PCIE connector of a mainboard, two PCIE connection plug-in seats are provided for a client, the personalized requirements of the client can be met, the PEX8748 chip leads out one PCIE2.0x2 to 88SE9230, the 88SE9230 is converted into two SATA3.0 chips and two M.2 chips to the mainboard, the personalized requirements of the client are met, the backboard leading-out interface further comprises a VGA port, a serial port and an RJ45 gigabit network port, the personalized requirements of the client are met, the Shenwei 1621 chip is connected with the PCIE expansion chip PEX8748 chip through the PCIE3.0x8 interface, and the PEX8748 chip provides expansion for the PCIE interface of the Shenwei 1621 chip. The existing same type of mainboard is often difficult to reach so many interfaces.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. A domestic binary star server mainboard based on Shenwei 1621 processor architecture comprises a mainboard and is characterized in that: the mainboard comprises a Shenwei 1621 chip, an XL710 chip, a FLASH, a PCIE expansion chip, a PCIE expansion PEX8748 chip, a CPLD communication module, a TUSB7340 host controller and a BMC card;
the Shenwei 1621 chip is a core cpu of a mainboard, 8 DDR3 slots are arranged on the mainboard, and DDR3 memory banks are built in the 8 DDR3 slots and used for providing a memory space larger than or equal to 32GB for the Shenwei 1621 chip;
the Shenwei 1621 chip is connected with the XL710 chip through a PCIE3.0x8 interface, and four paths of 10 GESFPs and optical modules are led out from a back plate of the XL710 chip to provide an interface for optical fiber communication for a mainboard;
the Shenwei 1621 chip is connected with an external FLASH through an SPI interface, and the FLASH provides a storage medium of related configuration data for the Shenwei 1621 chip;
the Shenwei 1621 chip is connected with a PCIE expansion PEX8748 chip through a PCIE3.0x8 interface, and the PCIE expansion PEX8748 chip provides expansion for the PCIE interface of the Shenwei 1621 chip;
the PCIE extended PEX8748 chip is extended to form a path of PCIE3.0x4 to be connected with the PEX8713, and the PCIE3.0x4 is used for communication;
the power-on time sequence of the mainboard is provided with a CPLD large-scale integrated circuit and is controlled by the CPLD large-scale integrated circuit;
the backboard leading-out interface of the mainboard further comprises a VGA port, a serial port and an RJ45 gigabit network port.
2. A domestic disassex server motherboard based on the processor architecture of shen 1621 as described in claim 1 wherein: the Shenwei 1621 chip is provided with a JTAG, and the JTAG is connected with the main board leading port in an opposite mode and used for internal test of the Shenwei 1621 chip.
3. A domestic disassex server motherboard based on the processor architecture of shen 1621 as described in claim 1 wherein: the PCIE extended PEX8748 chip leads out a path of PCIE3.0x8 and a path of PCIE3.0x16 to a PCIE extended chip connector of the mainboard, and the PCIE extended chip, the PCIE extended PEX8748 chip and the two paths of PCIE connection plug-in seats.
4. A domestic disassex server motherboard based on the processor architecture of shen 1621 as described in claim 1 wherein: the PCIE extended PEX8748 chip leads out a path of PCIE2.0x2 to 88SE9230, and the 88SE9230 is converted into two paths of SATA3.0 and two paths of M.2 to a mainboard.
5. A domestic disassex server motherboard based on the processor architecture of shen 1621 as described in claim 1 wherein: the PCIE extension PEX8748 chip leads out a path of PCIE2.0x1 to TUSB7340 host controller, USB3.0 and USB2.0 are arranged on the TUSB7340 host controller, the TUSB7340 host controller converts out one path of the USB3.0 to a front panel, the other two paths of the USB3.0 to a back panel and the other path of the USB2.0 to a BMC card, and the BMC card is communicated with the USB of the Shenwei 1621 chip.
6. A domestic disassex server motherboard based on the processor architecture of claim 1621 and wherein: the BMC card is connected to a mainboard through a DDR3SODIMM and is communicated with the Shenwei 1621 chip through an I2C and an SPI interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921897813.XU CN210348365U (en) | 2019-11-06 | 2019-11-06 | Domestic binary star server mainboard based on Shenwei 1621 processor architecture |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921897813.XU CN210348365U (en) | 2019-11-06 | 2019-11-06 | Domestic binary star server mainboard based on Shenwei 1621 processor architecture |
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| CN210348365U true CN210348365U (en) | 2020-04-17 |
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| CN201921897813.XU Active CN210348365U (en) | 2019-11-06 | 2019-11-06 | Domestic binary star server mainboard based on Shenwei 1621 processor architecture |
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