CN210328008U - Enhancement mode Lora gateway equipment - Google Patents

Abstract

The utility model discloses an enhancement mode Lora gateway equipment belongs to gateway equipment field, an enhancement mode Lora gateway equipment, including Lora gateway equipment, Lora gateway equipment includes 8 parallel receiving module of way, 2 parallel sending module of way, microprocessor MCU module, USB communication protection interface and power module, 2 parallel sending module of way adopts the SX1278 chip, the bandwidth scope of SX1278 chip is 7.8-500kHz, can realize utilizing the mode that SX1301 and SX1278 combined together, 8 the Lora goes upward the parallel received data of many spreading factors of channel, and the parallel ability of sending data of 2 way Lora down channel, effectively realize receiving and sending data when improving throughput.

Description

Enhancement mode Lora gateway equipment

Technical Field

The utility model relates to a gateway equipment field, more specifically say, relate to an enhancement mode Lora gateway equipment.

Background

The Lora communication technology is distinguished from a plurality of internet of things technologies by virtue of the characteristics of long-distance communication, low power consumption and the like, is accepted by the internet of things boundary, and is widely applied to occasions of meter reading, alarming, wireless data acquisition and the like. The LoRaWAN network architecture is a typical star topology, in which the LoRa gateway device is a transparent relay, and connects the terminal device (LoRa terminal device (1) in fig. 1) and the server (LoRa management device (3) in fig. 1), and the performance of the LoRa gateway directly concerns the transmission performance of the entire network architecture.

Lora gateways in the market at present are divided into two types, one type is a SX 1278-based Lora gateway, only data packets of nodes can be received in series, and the throughput capacity of the gateway is extremely limited; one type is a Lora gateway based on SX1301, which can receive data packets of 8 frequency bands in parallel, thereby greatly improving throughput capacity, but the scheme can only output 1 path of data, and cannot simultaneously send data when receiving data, and the communication mode can only be a semi-working mode.

SUMMERY OF THE UTILITY MODEL

1. Technical problem to be solved

To the problem that exists among the prior art, the utility model aims to provide an enhancement mode Lora gateway equipment, it can realize utilizing the mode that SX1301 and SX1278 combined together, provides 8 Lora and goes up the parallel received data of many spreading factor of channel to and the ability of the parallel data of sending of 2 way Lora down channel, effectively realizes receiving and sending data when improving throughput.

2. Technical scheme

In order to solve the above problems, the utility model adopts the following technical proposal.

The utility model provides an enhancement mode Lora gateway equipment, includes Lora gateway equipment, Lora gateway equipment includes 8 parallel receiving module of way, 2 parallel sending module of way, micro-processing MCU module, USB communication protection interface and power module, can realize utilizing the mode that SX1301 and SX1278 combined together, provides the parallel receipt data of many spreading factors of 8 Lora uplink channel to and the parallel ability of sending data of 2 way Lora downlink channel, effectively realize receiving and sending data when improving throughput.

Further, the 2-path parallel sending module adopts an SX1278 chip, the bandwidth range of the SX1278 chip is 7.8-500kHz, and the spreading factor of the SX1278 chip is 6-12.

Further, the 8-channel parallel receiving module comprises a baseband processing module and a radio frequency front end processing module, and the 8-channel parallel receiving module has the capability of receiving user data in parallel by using 8 channels and multiple spreading factors.

Further, the 2-channel parallel transmission module includes a Lora transmission processing module and a radio frequency front end processing module, and the 2-channel parallel transmission module has a downlink transmission capability of 2 independent channels.

Furthermore, the microprocessing MCU module adopts a Cortex-M4 core MCU, the working frequency of the Cortex-M4 core MCU can reach up to 180MHz, and the microprocessing MCU module is also provided with DSP and FPU instructions, and the microprocessing MCU module mainly processes the control, read and write functions of the 8-path parallel receiving module and the 2-path parallel sending module and the control, read and write functions of USB communication.

3. Advantageous effects

Compared with the prior art, the utility model has the advantages of:

(1) the scheme can realize the mode of combining SX1301 and SX1278, provides the capabilities of parallelly receiving data by 8 Lora uplink channels and parallelly sending data by 2Lora downlink channels, and effectively realizes the purposes of receiving and sending data while improving the throughput capacity.

(2) The 2-path parallel sending module adopts an SX1278 chip, the bandwidth range of the SX1278 chip is 7.8-500kHz, and the spreading factor of the SX1278 chip is 6-12.

(3) The 8-path parallel receiving module comprises a baseband processing module and a radio frequency front-end processing module, and the 8-path parallel receiving module has the capability of receiving user data in parallel by using 8 channels and multiple spreading factors.

(4) The 2-path parallel transmission module comprises a Lora transmission processing module and a radio frequency front-end processing module, and the 2-path parallel transmission module has the downlink transmission capability of 2 independent channels.

(5) The microprocessing MCU module adopts a Cortex-M4 nuclear MCU, the working frequency of the Cortex-M4 nuclear MCU can reach up to 180MHz, and the microprocessing MCU module is also provided with a DSP instruction and a FPU instruction, and the microprocessing MCU module mainly processes the control, read and write functions of an 8-path parallel receiving module and a 2-path parallel sending module and the control, read and write functions of USB communication.

Drawings

Fig. 1 is a main structural block diagram of the present invention;

fig. 2-8 are schematic diagrams of baseband processing modules according to the present invention (fig. 2 is a first part diagram, fig. 3 is a second part diagram, fig. 4 is a third part diagram, fig. 5 is a fourth part diagram, fig. 6 is a fifth part diagram, fig. 7 is a sixth part diagram, and fig. 8 is a seventh part diagram);

fig. 9-17 are schematic diagrams of a radio frequency front end processing module according to the present invention (fig. 9 is a first part diagram, fig. 10 is a second part diagram, fig. 11 is a third part diagram, fig. 12 is a fourth part diagram, fig. 13 is a fifth part diagram, fig. 14 is a sixth part diagram, fig. 15 is a seventh part diagram, fig. 16 is an eighth part diagram, and fig. 17 is a ninth part diagram);

fig. 18 to 24 are schematic diagrams of a 2-way parallel transmission module according to the present invention (fig. 18 is a first part diagram, fig. 19 is a second part diagram, fig. 20 is a third part diagram, fig. 21 is a fourth part diagram, fig. 22 is a fifth part diagram, fig. 23 is a sixth part diagram, and fig. 24 is a seventh part diagram);

fig. 25-30 are schematic diagrams of MCU module according to the present invention (fig. 25 is a first part diagram, fig. 26 is a second part diagram, fig. 27 is a third part diagram, fig. 28 is a fourth part diagram, fig. 29 is a fifth part diagram, and fig. 30 is a sixth part diagram);

fig. 31 to 36 are schematic diagrams of a power module according to the present invention (fig. 31 is a first part diagram, fig. 32 is a second part diagram, fig. 33 is a third part diagram, fig. 34 is a fourth part diagram, fig. 35 is a fifth part diagram, and fig. 36 is a sixth part diagram).

The reference numbers in the figures illustrate:

the system comprises 1Lora terminal equipment, 2Lora gateway equipment, 218 parallel receiving modules, 222 parallel transmitting modules, 23 micro-processing MCU modules, 24USB communication protection interfaces, 25 power supply modules and 3Lora management equipment.

Detailed Description

The technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiment of the present invention; obviously, the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by those skilled in the art without any inventive work are within the scope of the present invention based on the embodiments of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "top/bottom", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted", "provided", "sleeved/connected", "connected", and the like are to be understood in a broad sense, such as "connected", which may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example 1:

please refer to fig. 1, an enhanced Lora gateway device, including Lora gateway device 2, Lora gateway device 2 is connected with Lora terminal device 1 and Lora management device 3, Lora management device 3 configures operation to Lora gateway device 2 through USB communication, Lora gateway device 2 includes 8 parallel receiving module 21, 2 parallel sending module 22, micro-processing MCU module 23, USB communication protection interface 24 and power module 25, Lora gateway device 2 has 8-channel multi-spreading factor parallel receiving, the ability of 2 independent channel downlink sending, USB communication protection interface 24 provides hardware protection for USB communication, power module 25 provides reliable and stable dc power for whole device.

The Lora gateway device 2 is wirelessly connected with the Lora terminal device 1 by adopting a star network structure, the Lora gateway device 2 receives user data from the Lora terminal device 1, the 8-path parallel receiving module 21 comprises a baseband processing module and a radio frequency front end processing module, the 8-path parallel receiving module 21 has the capacity of parallelly receiving the user data by using 8 channels and multiple spreading factors, the 2-path parallel transmitting module 22 comprises a Lora transmitting processing module and a radio frequency front end processing module, the 2-path parallel transmitting module 22 has the capacity of transmitting data by using 2 independent channels, the microprocessing MCU module 23 adopts a Cortex-M4 nuclear MCU, the working frequency of the Cortex-M4 nuclear MCU can reach up to 180MHz, and is also provided with a DSP (digital signal processor) and an FPU (field programmable logic unit) instruction, and the microprocessing MCU module 23 mainly processes the control, reading and writing functions of the 8-path parallel receiving module 21 and the 2-path parallel transmitting module 22 and controls, reading and writing functions of USB (universal serial, A write function.

Please refer to fig. 2-8, which are schematic diagrams of baseband processing modules, and fig. 2-8 are assembled to form a circuit diagram, wherein fig. 2-3 are left diagrams, fig. 4-5 are top diagrams, fig. 6 is a middle diagram, fig. 7 is a right diagram, and fig. 8 is a bottom diagram, the baseband processing module is implemented by a baseband chip SX1301 based on Lora modulation, and the chip has a receiving sensitivity up to-142.5 dBm, 49 Lora "virtual" channels, and ADR technical features. The chip comprises a radio frequency MCU, a data packet MCU and an ASIC (application specific integrated circuit), wherein the radio frequency MCU is connected with 2 SX125x chips through an SPI (serial peripheral interface) bus and mainly responsible for real-time automatic gain control, radio frequency calibration and transceiving switching, the data packet MCU is responsible for distributing 8 LoRa modems to a plurality of channels, and the mechanism for arbitrating the data packet comprises the speed, the channels, the radio frequency and the signal intensity.

The specific pin connection relationship is as follows: HOST _ SCK, HOST _ MISO, HOST _ MOSI and HOST _ CSN pins of a baseband chip U4SX1301 in the baseband processing module are connected with SPI _ SCK, SPI _ MISO, SPI _ MOSI and SPI _ NSS pins of an MCU chip U16STM32F407 in the microprocessing MCU module 23, and the microprocessing MCU module 23 controls, reads and writes the baseband chip through the SPI bus; GPIO0, GPIO2 and GPIO3 pins of the baseband chip U4 are connected with GPIO0, GPIO2 and GPIO3 pins of the MCU chip U16, and the MCU acquires and sets the working state of SX1301 through the three pins; the RADIO frequency chip U5 is controlled, read and written by the baseband processing module through the SPI bus, wherein the RADIO _ A _ SCK, RADIO _ A _ MISO, RADIO _ A _ MOSI and RADIO _ A _ CS pins of the baseband chip U4 are connected with the SCK, MISO, MOSI and NSS of the RADIO frequency chip U5SX1255 in the RADIO frequency front-end processing module; the RADIO frequency chip U10 is controlled, read and written by the baseband processing module through the SPI bus, wherein the RADIO _ B _ SCK, RADIO _ B _ MISO, RADIO _ B _ MOSI and RADIO _ B _ CS pins of the baseband chip U4 are connected with the SCK, MISO, MOSI and NSS of the RADIO frequency chip U10SX1255 in the RADIO frequency front-end processing module; a _ IQ _ RX, A _ QI _ RX, A _ IQ _ TX and A _ QI _ TX pins of the baseband chip U4 are connected with Q _ OUT, I _ IN and Q _ IN pins of the radio frequency chip U5, B _ IQ _ RX, B _ QI _ RX, B _ IQ _ TX and B _ QI _ TX pins of the baseband chip U4 are connected with Q _ OUT, I _ IN and Q _ IN pins of the radio frequency chip U10, and radio frequency signals are acquired by the baseband chip U4 through the pins;

please refer to fig. 9-17, which are schematic diagrams of rf front-end processing modules, fig. 9-17 are assembled into a circuit diagram, wherein fig. 9-11 are assembled from left to right to form a top left diagram, fig. 12-14 are assembled from left to right to form a bottom left diagram, fig. 15-17 are assembled from left to right to form a right diagram, the baseband processing module is implemented based on an rf transceiver chip SX1255, SX1255 is a highly integrated rf front-end to digital I and Q modulator/demodulator multi-PHY mode transceiver capable of supporting multiple constant and non-constant envelope modulation schemes.

The specific pin connection relationship is as follows: SCK, MISO, MOSI and NSS of a RADIO frequency chip U5SX1255 in the RADIO frequency front end processing module are connected with RADIO _ A _ SCK, RADIO _ A _ MISO, RADIO _ A _ MOSI and RADIO _ A _ CS pins of a baseband chip U4; SCK, MISO, MOSI and NSS of a RADIO frequency chip U10SX1255 in the RADIO frequency front end processing module are connected with pins RADIO _ B _ SCK, RADIO _ B _ MISO, RADIO _ B _ MOSI and RADIO _ B _ CS of a baseband chip U4; the Q _ OUT, I _ IN and Q _ IN pins of the radio frequency chip U5 are connected with the A _ IQ _ RX, A _ QI _ RX, A _ IQ _ TX and A _ QI _ TX pins of the baseband chip U4; the Q _ OUT, I _ IN and Q _ IN pins of the radio frequency chip U10 are connected with the B _ IQ _ RX, B _ QI _ RX, B _ IQ _ TX and B _ QI _ TX pins of the baseband chip U4;

please refer to fig. 18-24, which are schematic diagrams of 2-channel parallel transmission module 22, fig. 18-22 are assembled into a circuit diagram, fig. 18 is a left part diagram, fig. 19 is an upper part diagram, fig. 20 is a lower part diagram, fig. 21-22 are sequentially assembled from left to right to form a right part diagram, fig. 23-24 are assembled into a circuit diagram from left to right, 2-channel parallel transmission module 22 is implemented by a loram-based spread spectrum modulation and demodulation chip SX1278, the SX1278 chip adopts loram-based spread spectrum modulation and demodulation technology, so that the transmission distance of the device far exceeds that of the existing system based on FSK or OOK debugging mode, the bandwidth range of the chip is 7.8-500kHz, the spreading factor is 6-12, and all available frequency bands are covered.

The specific pin connection relationship is as follows: the SCK, MISO, MOSI and NSS pins of the Lora chip U14SX1278 are connected with the PC6, PC7, PC8 and PC9 pins of the MCU chip U16 chip in the microprocessing MCU module 23; the DIO0-DIO5 pin of the Lora chip U14SX1278 is connected with the PC0-PC5 pin of the MCU chip U16; the Reset pin of the Lora chip U14SX1278 is connected with the PC11 pin of the MCU chip U16; the SCK, MISO, MOSI and NSS pins of the Lora chip U13SX1278 are connected with the PD6, PD7, PD8 and PD9 pins of the MCU chip U16 chip in the microprocessing MCU module 23; the DIO0-DIO5 pin of the Lora chip U13SX1278 is connected with the PD0-PD5 pin of the MCU chip U16; the Reset pin of the Lora chip U13SX1278 is connected with the PD11 pin of the MCU chip U16;

please refer to fig. 25-30, which are schematic diagrams of the microprocessor MCU module 23, fig. 25-30 are combined to form a complete diagram, wherein fig. 25-27 are sequentially arranged from top to bottom into a left part diagram, fig. 28-29 form a middle part diagram, fig. 30 is a right part diagram, the MCU module is an MCU 32F407 chip based on Cortex-M4 core, the STM32F407 chip adopts Cortex-M4 core, the operating frequency can reach as high as 180MHz, and is further provided with DSP and FPU instructions, and has rich peripherals, which can be adapted to different requirements.

The specific pin connection relationship is as follows: the module is connected to a baseband processing module, a radio frequency front end processing module, and a 2-way parallel transmission module 22, specifically, as shown in schematic diagrams 2, 3, and 4, USB _ DM and USB _ DP pins of an MCU chip U16 chip in the module are connected to D-and D + of a USB communication protection interface 24.

Please refer to fig. 31-36, which are schematic diagrams of the power module 25, wherein fig. 31-32 are assembled into a diagram from left to right, fig. 33-34 are assembled into a diagram from left to right, and fig. 35-36 are assembled into a diagram from left to right, and the module provides stable and reliable 3.3V and 1.8V power for the whole system through the power conversion chips SC283, SC4212 and SC 560.

The above description is only the preferred embodiment of the present invention; the scope of the present invention is not limited thereto. Any person skilled in the art should also be able to cover the technical scope of the present invention by replacing or changing the technical solution and the improvement concept of the present invention with equivalents and modifications within the technical scope of the present invention.

Claims (5)

1. An enhanced Lora gateway device, includes Lora gateway device (2), its characterized in that: lora gateway equipment (2) include 8 way parallel receiving module (21), 2 way parallel sending module (22), microprocessor MCU module (23), USB communication protection interface (24) and power module (25), microprocessor MCU module (23) mainly handle 8 way parallel receiving module (21) and 2 way parallel sending module's (22) control, read, write the function to and the control of USB communication, read, write the function, USB communication protection interface (24) provides hardware protection for the USB communication, power module (25) provide reliable and stable DC power supply for whole equipment.

2. An enhanced Lora gateway device according to claim 1, wherein: the 2-path parallel sending module (22) adopts an SX1278 chip, the bandwidth range of the SX1278 chip is 7.8-500kHz, and the spreading factor of the SX1278 chip is 6-12.

3. An enhanced Lora gateway device according to claim 1, wherein: the 8-path parallel receiving module (21) comprises a baseband processing module and a radio frequency front-end processing module.

4. An enhanced Lora gateway device according to claim 1, wherein: the 2-path parallel transmission module (22) comprises a Lora transmission processing module and a radio frequency front-end processing module.

5. An enhanced Lora gateway device according to claim 1, wherein: the microprocessing MCU module (23) adopts Cortex-M4 nuclear MCU.

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