CN210274674U - PCB (printed circuit board) adapter plate of power module - Google Patents
PCB (printed circuit board) adapter plate of power module Download PDFInfo
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- CN210274674U CN210274674U CN201920789693.5U CN201920789693U CN210274674U CN 210274674 U CN210274674 U CN 210274674U CN 201920789693 U CN201920789693 U CN 201920789693U CN 210274674 U CN210274674 U CN 210274674U
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Abstract
The utility model belongs to the technical field of power module, specifically disclose a power module's PCB keysets, including output routing layer and input routing layer, the PE layer has still been laid between output routing layer and the input routing layer. The utility model discloses a PE layer furthest keeps apart power module's input side and output side, reduces the coupling on the PCB keysets between the two, improves the EMC performance of product.
Description
Technical Field
The utility model belongs to the technical field of power module, concretely relates to power module's PCB keysets.
Background
The input and output of the power module are connected to the PCB adapter plate through a socket or a golden finger, a lead wire and the like, and the PCB adapter plate is wired through a section of PCB and externally led out to an input power supply and an output load through the socket or a terminal and the lead wire.
When the power module works, electromagnetic noise is generated and is transmitted to the outside through the input and the output of the module respectively. Meanwhile, there is coupling between input and output on the PCB adapter board, which affects EMC (electromagnetic compatibility) performance of the whole system, and only two examples are given below, which are not repeated:
in example 1, a single power module with AC input and DC output, or a plurality of power modules connected in parallel, is externally connected through a PCB adapter board. If the noise of the AC input side is strong, the noise of the AC input side is coupled to the DC output side through the PCB adapter plate; if the noise on the DC output side is strong, the noise on the DC output side is coupled to the AC input side through the PCB adapter board. In both cases, the EMC (electromagnetic compatibility) of the system is deteriorated.
In example 2, a single power module with DC input and DC output, or a plurality of power modules connected in parallel, is externally connected through a PCB adapter board. If the noise of the DC input side is strong, the noise of the DC input side can be coupled to the DC output side through the PCB adapter plate; if the noise on the DC output side is strong, the noise on the DC output side is coupled to the DC input side through the PCB adapter board. In both cases, the EMC (electromagnetic compatibility) of the system is deteriorated.
In a multi-module parallel system, due to the existence of noise superposition, input and output noise is more serious through the coupling of a PCB adapter plate, so that the electromagnetic compatibility of the whole system is seriously deteriorated.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is to provide a can obviously improve PCB keysets of product EMC performance.
In order to solve the technical problem, the utility model provides a technical scheme does:
a PCB adapter plate of a power module comprises an output wiring layer and an input wiring layer, wherein a PE layer is further laid between the output wiring layer and the input wiring layer.
Further, the PE layer is a laid complete copper foil.
Furthermore, the PE layer is provided with screw holes for connecting the PE layer to the shell or other PE metal pieces.
Furthermore, the output wiring layer comprises a first sub-output wiring layer and a second sub-output wiring layer which are sequentially stacked from top to bottom; the input wiring layer comprises a first sub input wiring layer, a second sub input wiring layer and a third sub input wiring layer which are sequentially stacked from top to bottom; wherein the PE layer is laid between the second sub-output routing layer and the first sub-input routing layer.
Furthermore, the input routing layer comprises a first sub-input routing layer and a second sub-input routing layer which are sequentially stacked from top to bottom; the output wiring layer comprises a first sub-output wiring layer, a second sub-output wiring layer and a third sub-output wiring layer which are sequentially stacked from top to bottom; wherein the PE layer is laid between the second sub-input routing layer and the first sub-output routing layer.
Furthermore, the input routing layer comprises a first sub input routing layer, a second sub input routing layer and a third sub input routing layer which are sequentially stacked from top to bottom; the output wiring layer comprises a first sub-output wiring layer and a second sub-output wiring layer which are sequentially stacked from top to bottom; wherein the PE layer is laid between the third sub-input routing layer and the first sub-output routing layer.
Furthermore, the output wiring layer comprises a first sub-output wiring layer, a second sub-output wiring layer and a third sub-output wiring layer which are sequentially stacked from top to bottom; the input routing layer comprises a first sub-input routing layer and a second sub-input routing layer which are sequentially stacked from top to bottom; wherein the PE layer is laid between the third sub-output routing layer and the first sub-input routing layer.
Further, the input routing layer comprises a first sub-input routing layer; the output wiring layer comprises a first sub-output wiring layer and a second sub-output wiring layer which are sequentially stacked from top to bottom; wherein the PE layer is laid between the first sub-input routing layer and the first sub-output routing layer.
Further, the output routing layer comprises a first sub-output routing layer; the input routing layer comprises a first sub-input routing layer and a second sub-input routing layer which are sequentially stacked from top to bottom; wherein the PE layer is laid between the first sub-output routing layer and the first sub-input routing layer.
Further, the input routing layer comprises a first sub-input routing layer and a second input routing layer; the output routing layer comprises a first sub-output routing layer; wherein the PE layer is laid between the second input routing layer and the first sub-output routing layer.
The utility model has the advantages that:
the utility model discloses a PE layer furthest keeps apart power module's input side and output side, reduces the coupling on the PCB keysets between the two, improves the EMC performance of product.
Drawings
Fig. 1 is a schematic structural diagram of a PCB adapter board of a power module according to the present invention in embodiment 1;
FIG. 2 is a diagram of EMC radiation emission test results in the prior art;
FIG. 3 is a graph of EMC radiation emission test results of example 1;
FIG. 4 is a diagram of EMC conducted emission test results from the prior art;
FIG. 5 is a graph of EMC conducted emission test results of example 1; fig. 6 is a schematic structural view of a PCB interposer of a power module according to the present invention in embodiment 2;
fig. 7 is a schematic structural view of a PCB interposer of a power module according to the present invention in embodiment 3;
fig. 8 is a schematic structural view of a PCB interposer of a power module according to the present invention in embodiment 4;
fig. 9 is a schematic structural view of a PCB interposer of a power module according to the present invention in embodiment 5;
fig. 10 is a schematic structural view of a PCB interposer of a power module according to the present invention in embodiment 6;
fig. 11 is a schematic structural view of a PCB interposer of a power module according to the present invention in embodiment 7;
fig. 12 is a schematic structural diagram of a PCB interposer of a power module according to the present invention in embodiment 8.
The reference numerals include:
100-output routing layer 110-first sub-output routing layer
120-second sub-output routing layer 130-third sub-output routing layer
200-input routing layer
210-first sub-input routing layer 220-second sub-input routing layer
230-third sub-input routing layer 300-PE layer
Detailed Description
In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Please refer to fig. 1, which illustrates a PCB adapter board of a power module according to the present invention, including an output wiring layer 100 and an input wiring layer 200, a PE layer 300 is further laid between the output wiring layer 100 and the input wiring layer 200. The utility model discloses a power module's input side and output side are kept apart to the utmost on PE layer 300, reduce the coupling on the PCB keysets between the two, improve the EMC performance of product.
In a preferred embodiment of the present application, the PE layer 300 is a full copper foil. In order to facilitate the connection of the PE layer 300 to a chassis or other PE metal pieces, a plurality of screw holes are formed around the copper foil. It is understood, of course, that the PE layer 300 may also be a trace, i.e., not a complete copper foil.
The output routing layer 100 in this application may have only one layer, or may include a plurality of sub-output routing layers, and the specific number of sub-output routing layers in this application is not limited, but should have at least one. Similarly, the input routing layer 200 may have only one layer, or may include a plurality of sub-input routing layers, and the specific number of sub-input routing layers is not limited in this application, but should be at least one. The above components are described in further detail below.
Example 1
As shown in fig. 1, the output routing layer 100 includes a first sub-output routing layer 110 and a second sub-output routing layer 120 stacked in sequence from top to bottom. The input routing layer 200 includes a first sub-input routing layer 210, a second sub-input routing layer 220, and a third sub-input routing layer 230, which are sequentially stacked from top to bottom; wherein the PE layer 300 is laid between the second sub-output routing layer 120 and the first sub-input routing layer 210.
Fig. 2 is a diagram showing an EMC radiation emission test result in the prior art, and fig. 3 is a diagram showing an EMC radiation emission test result. As can be seen from comparison between FIG. 2 and FIG. 3, the actual measurement of the higher frequency point of the overall radiated emission is reduced by more than 10 dB.
Fig. 4 is a diagram showing a test result of EMC conducted emission in the prior art, and fig. 5 is a diagram showing a test result of EMC conducted emission. Comparing fig. 4 and fig. 5, it can be seen that the frequency of the overall conducted transmission is reduced by more than 10 dB.
Example 2
As shown in fig. 6, the input routing layer 200 includes a first sub-input routing layer 210 and a second sub-input routing layer 220 sequentially stacked from top to bottom; the output routing layer 100 comprises a first sub-output routing layer 110, a second sub-output routing layer 120 and a third sub-output routing layer 130 which are sequentially stacked from top to bottom; wherein the PE layer 300 is laid between the second sub-input routing layer 220 and the first sub-output routing layer 110.
Example 3
As shown in fig. 7, the input routing layer 200 includes a first sub-input routing layer 210, a second sub-input routing layer 220, and a third sub-input routing layer 230, which are sequentially stacked from top to bottom; the output routing layer 100 comprises a first sub-output routing layer 110 and a second sub-output routing layer 120 which are sequentially stacked from top to bottom; wherein the PE layer 300 is laid between the third sub-input routing layer 230 and the first sub-output routing layer 110.
Example 4
As shown in fig. 8, the output routing layer 100 includes a first sub-output routing layer 110, a second sub-output routing layer 120, and a third sub-output routing layer 130 stacked in sequence from top to bottom; the input routing layer 200 includes a first sub-input routing layer 210 and a second sub-input routing layer 220 sequentially stacked from top to bottom; wherein the PE layer 300 is laid between the third sub-output routing layer 130 and the first sub-input routing layer 210.
Example 5
As shown in fig. 9, the input routing layer 200 includes a first sub-input routing layer 210; the output routing layer 100 comprises a first sub-output routing layer 110 and a second sub-output routing layer 120 which are sequentially stacked from top to bottom; wherein the PE layer 300 is laid between the first sub-input routing layer 210 and the first sub-output routing layer 110.
Example 6
As shown in fig. 10, the output routing layer 100 includes a first sub-output routing layer 110; the input routing layer 200 includes a first sub-input routing layer 210 and a second sub-input routing layer 220 sequentially stacked from top to bottom; wherein the PE layer 300 is laid between the first sub-output routing layer 110 and the first sub-input routing layer 210.
Example 7
As shown in fig. 11, the input routing layer 200 includes a first sub-input routing layer 210 and a second input routing layer 220 sequentially stacked from top to bottom; the output routing layer 100 comprises a first sub-output routing layer 110; wherein the PE layer 300 is laid between the second input routing layer 220 and the first sub-output routing layer 110.
Example 8
As shown in fig. 12, the output routing layer 100 includes a first sub-output routing layer 110 and a second sub-output routing layer 120 stacked in sequence from top to bottom; the input routing layer 200 includes a first sub-input routing layer 210; wherein the PE layer 300 is laid between the second sub-output routing layer 120 and the first sub-output routing layer 110.
It can be understood that the thickness of the PE layer 300 in the present application can be adjusted according to actual needs, and details are not described in the present application. The layer spacing on both sides of the PE layer 300 can also be adjusted according to the actual situation to achieve the best isolation effect.
The above description is only a preferred embodiment of the present invention, and many changes can be made in the detailed description and the application scope according to the idea of the present invention for those skilled in the art, which all belong to the protection scope of the present invention as long as the changes do not depart from the concept of the present invention.
Claims (10)
1. A PCB pinboard of power module, includes output routing layer (100) and input routing layer (200), its characterized in that: and a PE layer (300) is further laid between the output routing layer (100) and the input routing layer (200).
2. The PCB interposer of a power module of claim 1, wherein: the PE layer (300) is a covered complete copper foil.
3. The PCB interposer of a power module of claim 1, wherein: the PE layer (300) is provided with screw holes for connecting the PE layer (300) to a shell or other PE metal pieces.
4. A PCB interposer of a power module according to any of claims 1 to 3, wherein: the output wiring layer (100) comprises a first sub-output wiring layer (110) and a second sub-output wiring layer (120) which are sequentially stacked from top to bottom; the input wiring layer (200) comprises a first sub-input wiring layer (210), a second sub-input wiring layer (220) and a third sub-input wiring layer (230) which are sequentially stacked from top to bottom; wherein the PE layer (300) is laid between the second sub-output routing layer (120) and the first sub-input routing layer (210).
5. A PCB interposer of a power module according to any of claims 1 to 3, wherein: the input routing layer (200) comprises a first sub-input routing layer (210) and a second sub-input routing layer (220) which are sequentially stacked from top to bottom; the output wiring layer (100) comprises a first sub-output wiring layer (110), a second sub-output wiring layer (120) and a third sub-output wiring layer (130) which are sequentially stacked from top to bottom; wherein the PE layer (300) is laid between the second sub-input routing layer (220) and the first sub-output routing layer (110).
6. A PCB interposer of a power module according to any of claims 1 to 3, wherein: the input wiring layer (200) comprises a first sub-input wiring layer (210), a second sub-input wiring layer (220) and a third sub-input wiring layer (230) which are sequentially stacked from top to bottom; the output wiring layer (100) comprises a first sub-output wiring layer (110) and a second sub-output wiring layer (120) which are sequentially stacked from top to bottom; wherein the PE layer (300) is laid between the third sub-input routing layer (230) and the first sub-output routing layer (110).
7. A PCB interposer of a power module according to any of claims 1 to 3, wherein: the output wiring layer (100) comprises a first sub-output wiring layer (110), a second sub-output wiring layer (120) and a third sub-output wiring layer (130) which are sequentially stacked from top to bottom; the input routing layer (200) comprises a first sub-input routing layer (210) and a second sub-input routing layer (220) which are sequentially stacked from top to bottom; wherein the PE layer (300) is laid between the third sub-output routing layer (130) and the first sub-input routing layer (210).
8. A PCB interposer of a power module according to any of claims 1 to 3, wherein: the input routing layer (200) comprises a first sub-input routing layer (210); the output wiring layer (100) comprises a first sub-output wiring layer (110) and a second sub-output wiring layer (120) which are sequentially stacked from top to bottom; wherein the PE layer (300) is laid between the first sub-input routing layer (210) and the first sub-output routing layer (110).
9. A PCB interposer of a power module according to any of claims 1 to 3, wherein: the output routing layer (100) comprises a first sub-output routing layer (110); the input routing layer (200) comprises a first sub-input routing layer (210) and a second sub-input routing layer (220) which are sequentially stacked from top to bottom; wherein the PE layer (300) is laid between the first sub-output routing layer (110) and the first sub-input routing layer (210).
10. A PCB interposer of a power module according to any of claims 1 to 3, wherein: the input routing layer (200) comprises a first sub-input routing layer (210) and a second input routing layer (220); the output routing layer (100) comprises a first sub-output routing layer (110); wherein the PE layer (300) is laid between the second input routing layer (220) and the first sub-output routing layer (110).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920789693.5U CN210274674U (en) | 2019-05-29 | 2019-05-29 | PCB (printed circuit board) adapter plate of power module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920789693.5U CN210274674U (en) | 2019-05-29 | 2019-05-29 | PCB (printed circuit board) adapter plate of power module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210274674U true CN210274674U (en) | 2020-04-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920789693.5U Active CN210274674U (en) | 2019-05-29 | 2019-05-29 | PCB (printed circuit board) adapter plate of power module |
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| Country | Link |
|---|---|
| CN (1) | CN210274674U (en) |
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