CN210274031U

CN210274031U - Frequency difference approaching high-suppression phase-locked loop crystal oscillator

Info

Publication number: CN210274031U
Application number: CN201920336777.3U
Authority: CN
Inventors: 唐俭英
Original assignee: Guangdong Xinhai Technology Co ltd
Current assignee: Guangdong Xinhai Technology Co ltd
Priority date: 2019-03-18
Filing date: 2019-03-18
Publication date: 2020-04-07
Anticipated expiration: 2029-03-18

Abstract

The utility model provides a pair of frequency difference is close high suppression phase-locked loop crystal oscillator, include: the circuit comprises a processing chip, a crystal oscillator, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor and an S-shaped network circuit, wherein one section of S-shaped wire is connected with an external reference source, the circuit can generate subtle changes through the S-shaped network circuit before the reference source is input, the quality of the input reference signal after amplification and isolation is better, and meanwhile, the optimization effect can be achieved on the phase in a phase-locked loop circuit, so that the simplification and optimization of all performances of a frequency difference crystal oscillator are achieved, and meanwhile, the volume is small, and the economical practicability is high.

Description

Frequency difference approaching high-suppression phase-locked loop crystal oscillator

Technical Field

The utility model relates to an electron device field, in particular to frequency difference is close high suppression phase-locked loop crystal oscillator.

Background

With the change of the scientific and technological industry, electronic equipment is continuously updated, so that various requirements for various electronic components appear, for example, a crystal oscillator with approximate frequency difference exists in the market (namely, a frequency point of 10.23MHz is close to 10MHz, and the frequency point is the frequency difference crystal oscillator). The crystal oscillator in the market generally has high cost, complex manufacture and long period, a frequency synthesizer which is a nominal frequency of 10.23MHz plus 0.23MHz is adopted, and a plurality of electronic components are stacked in a circuit space with small volume to realize the frequency difference crystal oscillator, so that the space position of the circuit is occupied, and the frequency difference crystal oscillator is not in accordance with the trend of convenience and miniaturization of electronic equipment, and therefore the scheme cannot become the mainstream.

SUMMERY OF THE UTILITY MODEL

The utility model provides a pair of frequency difference is close high suppression phase-locked loop crystal oscillator accomplishes simplification, optimization to each performance of frequency difference crystal oscillator, and is small, economical and practical high simultaneously.

The utility model discloses a realize above-mentioned purpose and adopt following technical scheme:

the utility model provides a frequency difference is close high suppression phase-locked loop crystal oscillator, include: the processing chip comprises a processing chip, a crystal oscillator X1, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor and an S-type network circuit, wherein one end of the S-type network circuit is connected with an external reference source, the other end of the S-type network circuit is connected with one end of the third capacitor, the other end of the third capacitor is respectively connected with one end of the third resistor, an external reference source signal input pin of the processing chip and one end of the second resistor, the other end of the third resistor is respectively connected with a ground pin and a grounding end of the processing chip, the other end of the second resistor is respectively connected with a power supply input pin of the processing chip, a signal input pin of the processing chip, one end of the second capacitor and one end of the first resistor, the other end of the first resistor is respectively connected with one end of the first capacitor and an external power supply, the other end of the first capacitor is connected with the other end of the second capacitor and the grounding end respectively, the output pin of the processing chip is connected with one end of the fourth resistor, the other end of the fourth resistor is connected with the input pin of the crystal oscillator, the grounding pin of the crystal oscillator is connected with the grounding end, and the output pin of the crystal oscillator is connected with external equipment.

In an embodiment of the present invention, the model of the processing chip is SN74AHC1G04 DCK.

In an embodiment of the present invention, the crystal oscillator is a VCXO-10.23MHz frequency difference crystal oscillator.

In an embodiment of the present invention, the S-type network circuit is formed by a bent wire.

The utility model has the advantages that:

the utility model provides a pair of frequency difference is close high suppression phase-locked loop crystal oscillator, the wire that adopts one section S type is connected with external reference source, through S-shaped network circuit before the input reference source, the circuit can signal production subtle change, the reference signal quality of input after enlarging the isolation is better, can play the optimal action to phase place in the phase-locked loop circuit simultaneously, thereby accomplish to each performance of frequency difference crystal oscillator simplifying, optimize, make the oscillator possess the high isolation, the high suppression, the characteristics of low phase noise, simultaneously small, economic practicality is high.

Drawings

Fig. 1 is a schematic diagram of a frequency-difference approach high-rejection phase-locked loop crystal oscillator circuit according to an embodiment of the present invention.

Detailed Description

The present invention will be further described with reference to the accompanying drawings and specific embodiments, wherein the exemplary embodiments and the description are only for the purpose of illustrating the present invention, and are not to be construed as limiting the present invention.

It should be noted that the terms "first" and "second" in the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.

In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The utility model provides a frequency difference is close high suppression phase-locked loop crystal oscillator, include: a processing chip U1, a crystal oscillator X1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3 and an S-type network circuit S1, wherein one end of the S-type network circuit S1 is connected to an external reference source, the other end of the S-type network circuit S1 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to one end of the third resistor R3, the external reference source signal input pin B of the processing chip U1 and one end of the second resistor R2, the other end of the third resistor R3 is connected to the ground pin GND and the ground terminal GND of the processing chip U1, the other end of the second resistor R2 is connected to the power source input pin of the processing chip U1, the VCC signal input pin of the processing chip U1, one end of the second capacitor C2 and one end of the first resistor R1, the other end of first resistance R1 is connected with the one end and the external power supply of first electric capacity C1 respectively, the other end of first electric capacity C1 respectively with the other end and the earthing terminal of second electric capacity C2 are connected, handle chip U1's output pin Y with fourth resistance R4's one end is connected, fourth resistance R4's the other end with crystal oscillator X1's input pin IN is connected, crystal oscillator X1's ground pin GND is connected with the earthing terminal, crystal oscillator X1's output pin OUT is connected with external equipment.

In an embodiment of the present invention, the processing chip U1 is SN74AHC1G04 DCK.

In an embodiment of the present invention, the crystal oscillator X1 is a VCXO-10.23MHz frequency difference crystal oscillator.

In an embodiment of the present invention, the S-type network circuit S1 is formed by a bent conducting wire;

furthermore, the S-shaped network circuit S1 is formed by a bent and folded lead, the folding times of the lead are 5-6, namely the number of turns formed by folding the lead is 5-6, the length of the lead folded in one time is 3-5 mm, and the distance between adjacent folded leads is 1.1-2.3 mm.

Specifically, in a specific application scenario of the present invention, the S-type network circuit S1 is composed of a curved wire, when the S-type network circuit S1 is powered on, a magnetic field exists around the wire, the S-type network circuit S1 composed of the curved wire is equivalent to an inductor, so that an external reference source is subjected to signal screening and noise filtering to provide an interference-free reference signal to the phase-locked loop circuit, and meanwhile, the RC circuit formed by connecting the first resistor R1, the second resistor R2 and the third capacitor C3 performs coupling, phase shifting and filtering again on the external reference source, so that the reference signal is compared with the local oscillation signal generated by the processing chip U1 in phase, the signal frequency and phase difference are kept unchanged, the purpose of phase locking is achieved, and the frequency and phase of the crystal oscillator X1 are both kept in a fixed relationship with the input signal, thereby outputting a signal with high isolation, high suppression and low phase noise to be supplied to external equipment.

Obviously, the above examples are only examples for more clearly expressing the technical solutions of the present invention, and are not intended to limit the embodiments of the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made in the above-described embodiments without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A frequency-shifted near high rejection phase locked loop crystal oscillator, comprising: the processing chip comprises a processing chip, a crystal oscillator, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor and an S-type network circuit, wherein one end of the S-type network circuit is connected with an external reference source, the other end of the S-type network circuit is connected with one end of the third capacitor, the other end of the third capacitor is respectively connected with one end of the third resistor, an external reference source signal input pin of the processing chip and one end of the second resistor, the other end of the third resistor is respectively connected with a ground pin and a grounding end of the processing chip, the other end of the second resistor is respectively connected with a power supply input pin of the processing chip, a signal input pin of the processing chip, one end of the second capacitor and one end of the first resistor, and the other end of the first resistor is respectively connected with one end of the first capacitor and an external power supply, the other end of the first capacitor is connected with the other end of the second capacitor and the grounding end respectively, the output pin of the processing chip is connected with one end of the fourth resistor, the other end of the fourth resistor is connected with the input pin of the crystal oscillator, the grounding pin of the crystal oscillator is connected with the grounding end, and the output pin of the crystal oscillator is connected with external equipment.

2. The crystal oscillator of claim 1, wherein the processing chip is model SN74AHC1G04 DCKR.

3. A frequency-offset near high-rejection phase-locked loop crystal oscillator as claimed in claim 1, wherein said crystal oscillator is a VCXO-10.23MHz frequency-offset crystal oscillator.

4. A frequency-difference near high-rejection phase-locked loop crystal oscillator as claimed in claim 1, wherein said S-network circuit is formed by a bent wire.