CN210272364U - Array substrate and display panel - Google Patents
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- CN210272364U CN210272364U CN201921789816.1U CN201921789816U CN210272364U CN 210272364 U CN210272364 U CN 210272364U CN 201921789816 U CN201921789816 U CN 201921789816U CN 210272364 U CN210272364 U CN 210272364U
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Abstract
The utility model provides an array substrate and display panel. The array substrate includes: the transistor comprises a substrate base plate, and at least one metal oxide thin film transistor and at least one low-temperature polycrystalline silicon thin film transistor which are arranged on the substrate base plate; the metal oxide thin film transistor comprises a first grid, at least one buffer layer, a metal oxide semiconductor graph, a silicon oxide film, a grid insulating layer and a metal oxide protective layer which are sequentially arranged, first through holes are formed in the metal oxide protective layer, the grid insulating layer and the silicon oxide film, and a first source electrode and a first drain electrode are in contact with the metal oxide semiconductor graph through the first through holes; the low-temperature polycrystalline silicon thin film transistor comprises at least one buffer layer, a silicon oxide film, a low-temperature polycrystalline silicon semiconductor pattern, a grid electrode insulating layer, a second grid electrode and a metal oxide protective layer which are sequentially arranged, wherein second through holes are formed in the metal oxide protective layer and the grid electrode insulating layer. The utility model discloses can reduce display panel's consumption.
Description
Technical Field
The utility model relates to a flat panel display technology field especially relates to an array substrate and display panel.
Background
The flat display device has the advantages of thin body, power saving, no radiation and the like, and is widely applied. Conventional flat panel Display devices mainly include Liquid Crystal Display (LCD) devices and Organic Light Emitting Diode (OLED) Display devices.
At present, the flat panel display device is developed to a large size, a high integration, a high resolution, and a high driving frequency, and the requirement for mobility is higher and higher, and the polysilicon TFT used at present cannot perform a large size flat panel display, so that a panel technology based on a Low Temperature Polysilicon (LTPS) TFT (Thin Film Transistor) becomes a mainstream. After the improvement of the past years, the LTPS display panel has the advantages of high resolution, high response speed, high brightness, high aperture ratio, etc., so that it becomes the most mature and mainstream TFT panel technology in the market today.
However, although the low-temperature polysilicon TFT has high mobility, the off-state current of the TFT is large, and when a display panel is driven by the TFT, power consumption is high.
SUMMERY OF THE UTILITY MODEL
The utility model provides an array substrate and display panel can reduce display panel's consumption.
In a first aspect, the present invention provides an array substrate, including: the transistor comprises a substrate base plate, and at least one metal oxide thin film transistor and at least one low-temperature polycrystalline silicon thin film transistor which are arranged on the substrate base plate;
the metal oxide thin film transistor comprises a first grid, at least one buffer layer, a metal oxide semiconductor graph, a silicon oxide film, a grid insulating layer and a metal oxide protective layer which are sequentially arranged, the metal oxide thin film transistor also comprises a first source electrode and a first drain electrode, first through holes are formed in the metal oxide protective layer, the grid insulating layer and the silicon oxide film, and the first source electrode and the first drain electrode are in contact with the metal oxide semiconductor graph through the first through holes;
the low-temperature polycrystalline silicon thin film transistor comprises at least one buffer layer, a silicon oxide film, a low-temperature polycrystalline silicon semiconductor pattern, a grid electrode insulating layer, a second grid electrode and a metal oxide protective layer which are sequentially arranged, the low-temperature polycrystalline silicon thin film transistor further comprises a second source electrode and a second drain electrode, second through holes are formed in the metal oxide protective layer and the grid electrode insulating layer, and the second source electrode and the second drain electrode are in contact with the low-temperature polycrystalline silicon semiconductor pattern through the second through holes.
Optionally, the pixel structure further comprises a passivation layer and a pixel electrode, the passivation layer is disposed above the metal oxide protection layer, a conductive via hole is disposed on the passivation layer, and the pixel electrode is electrically connected to the first drain electrode through the conductive via hole.
Optionally, in the at least one buffer layer, a first buffer layer closest to the metal oxide pattern is a silicon oxide layer.
Optionally, the first buffer layer has a thickness of
Optionally, the low temperature polysilicon thin film transistor further includes a light-shielding pattern, and the light-shielding pattern is located between the at least one buffer layer and the substrate and below the low temperature polysilicon semiconductor pattern.
Optionally, the light-shielding pattern and the first gate are formed in the same photolithography process.
Optionally, the light-shielding pattern is located in an area corresponding to the non-display area of the array substrate.
Optionally, the metal oxide semiconductor pattern is indium gallium zinc oxide IGZO.
In a second aspect, the present invention provides a display panel, including the above array substrate.
Optionally, the display panel is a liquid crystal display panel or an organic light emitting diode display panel.
The embodiment of the utility model provides an array substrate and display panel, because metal oxide TFT forms in the region that corresponds with the display area, be used for driving pixel electrode, and metal oxide TFT mobility is high, there is very good off-state current, can reduce display panel's consumption with its driving pixel electrode, use with low temperature polycrystalline silicon TFT cooperation, both can satisfy the requirement of the high mobility of display panel and also can reduce the consumption, can satisfy jumbo size liquid crystal display and organic light emitting diode display device's demand better.
Drawings
In order to illustrate the technical solutions of the present invention or the prior art more clearly, the drawings needed for the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an array substrate in a first state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an array substrate in a second state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an array substrate in a third state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an array substrate in a fourth state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an array substrate in a fifth state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an array substrate in a sixth state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an array substrate in a seventh state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention.
Reference numerals:
1-a glass substrate; 2-shading pattern; 3-a first buffer layer; a 4-metal oxide semiconductor pattern; 5-low temperature polysilicon semiconductor pattern; 6-a gate insulating layer; 7-a first gate; 8-a second gate; 9-a metal oxide protective layer; 10-a first source; 10' -a first drain electrode; 11-a second source; 11' -a second drain electrode; 12-a conductive via; 13-a passivation layer; 14-pixel electrodes; 15-a first via; 16-a second via; 17-silicon oxide film.
Detailed Description
To make the objects, technical solutions and advantages of the present invention clearer, the drawings of the present invention are combined to clearly and completely describe the technical solutions of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Example one
Fig. 1 is a schematic flow chart of a manufacturing method of an array substrate according to an embodiment of the present invention, as shown in fig. 1, the manufacturing method of an array substrate of this embodiment includes:
s10, forming first grid electrodes and shading patterns on the substrate at intervals, wherein the first grid electrodes are positioned in the area corresponding to the display area of the array substrate;
specifically, the glass substrate 1 (which may also be an organic substrate, such as PI, PET, etc.) may be deposited by sputtering or thermal evaporation to a thickness of about
The gate metal layer of (a). The gate metal layer may be made of Cr, W, Cu, Ti, Ta, Mo, etc. or alloy. After a common photolithography process, the first gate electrode 7 and the light-shielding pattern 2 of the low-temperature polysilicon TFT region are formed.
S20, depositing at least one buffer layer on the first grid 7 and the shading pattern 2, and forming a metal oxide semiconductor pattern 4 positioned above the first grid 7 and a low-temperature polysilicon semiconductor pattern 5 positioned above the shading pattern 2 on the buffer layer;
specifically, the first gate electrode 7 and the light shielding pattern 2 are successively deposited by a vapor deposition method of plasma enhanced chemical to a thickness of
The buffer layer of (2). And a metal oxide semiconductor pattern 4 positioned above the first gate electrode 7 and a low temperature polysilicon semiconductor pattern 5 positioned above the light shielding pattern 2 are formed on the buffer layer.
Since the metal oxide semiconductor pattern 4 is located in the area corresponding to the display area of the array substrate, the metal oxide TFT is formed in the area corresponding to the display area and used for driving the pixel electrode 14, the metal oxide TFT has high mobility and very good off-state current, and the driving of the pixel electrode 14 by the metal oxide TFT can reduce the power consumption of the display panel and can better meet the requirements of large-sized liquid crystal displays and organic light emitting diode display devices.
Optionally, a metal oxide semiconductor pattern 4 located above the first gate 7 and a low temperature polysilicon semiconductor pattern 5 located above the light shielding layer are formed on the buffer layer, and the method specifically includes:
depositing an amorphous silicon film on the buffer layer on which the metal oxide semiconductor pattern 4 is formed;
the amorphous silicon film is formed into a polycrystalline silicon film by an annealing process, and a low-temperature polycrystalline silicon semiconductor pattern 5 is formed by a photolithography process.
First, the buffer layer is deposited by sputtering or thermal evaporation to a thickness of about
The metal oxide semiconductor layer of (2) may be IGZO, or Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides, and then forming a metal oxide semiconductor pattern 4 by a one-time photoetching process.
Next, a metal oxide semiconductor pattern 4 is formed on the buffer layer by a plasma enhanced chemical vapor deposition method to be successively deposited in a thickness of
Then, the amorphous silicon film is annealed at high temperature, for example, ELA annealing (excimer laser annealing) is used to melt the amorphous silicon film in a short time, and a polycrystalline silicon film is grown by recrystallization; of course, a rapid annealing furnace may be used to perform high-temperature annealing, such as annealing at a temperature above 600 ℃, to melt the amorphous silicon film and grow it again into a polysilicon film; the low temperature polysilicon semiconductor pattern 5 is formed by one photolithography process.
Or, as another optional implementation, forming the metal oxide semiconductor pattern 4 located above the first gate 7 and the low temperature polysilicon semiconductor pattern 5 located above the light shielding layer on the buffer layer, specifically including:
depositing a silicon oxide film 17 on the buffer layer formed with the metal oxide semiconductor pattern 4, and depositing an amorphous silicon film on the silicon oxide film 17; the amorphous silicon film is formed into a polycrystalline silicon film by an annealing process, and a low-temperature polycrystalline silicon semiconductor pattern 5 is formed by a photolithography process.
Specifically, first, the buffer layer is deposited by sputtering or thermal evaporation to a thickness of about
Oxidation of metal ofThe semiconductor layer may be IGZO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides, and then forming a metal oxide semiconductor pattern 4 by a one-time photoetching process.
Then depositing the metal oxide semiconductor pattern 4 on the substrate by the plasma enhanced chemical vapor deposition method at a low speed and a low temperature to a deposition thickness of
The corresponding reaction gas is SiH4，N2O, the content of H in the silicon oxide film is lower than 6%, preferably between 3% and 4%, so that the influence of H on the metal oxide semiconductor pattern 4 can be reduced; meanwhile, the silicon oxide film deposited at a low speed has high compactness and good flatness, is used as an interface of the polycrystalline silicon TFT, is favorable for the transmission of current carriers, and improves the mobility of the polycrystalline silicon TFT, so that the driving capability of the polycrystalline silicon TFT is improved, the silicon oxide film deposited at a low speed can also protect the metal oxide semiconductor pattern 4 below the silicon oxide film from being damaged when a polycrystalline silicon pattern is formed, and the performance of the metal oxide semiconductor layer is improved, and further preferably, the thickness range of the silicon oxide film 17 is
Then, a film having a thickness of
Then, the amorphous silicon film is annealed at high temperature, for example, ELA annealing (excimer laser annealing) is used to melt the amorphous silicon film in a short time, and a polycrystalline silicon film is grown by recrystallization; of course, a rapid annealing furnace may be used to perform high-temperature annealing, such as annealing at a temperature above 600 ℃, to melt the amorphous silicon film and grow it again into a polysilicon film; by one-shot lithographyThe process forms a low temperature polysilicon semiconductor pattern 5.
S30, sequentially depositing a gate insulating layer 6 and a gate metal layer on the metal oxide semiconductor pattern 4 and the low temperature polysilicon semiconductor pattern 5, and performing a photolithography process to form a second gate electrode 8 above the low temperature polysilicon semiconductor pattern 5.
Specifically, the metal oxide semiconductor pattern 4 and the low-temperature polysilicon semiconductor pattern 5 are deposited by a plasma enhanced chemical vapor deposition method to a thickness of
The gate insulating layer 6 may be silicon oxide, and the corresponding reaction gas may be SiH4，N2O; metal oxides, such as magnetron sputtering, can also be used to form Al2O3。
Then, the gate insulating layer 6 is sequentially deposited to a thickness of about
The gate metal layer can be made of Cr, W, Ti, Ta, Mo, Al, Cu and other metals or alloys, and the gate metal layer consisting of multiple layers of metals can also meet the requirement. A second gate electrode 8 is formed over the low temperature polysilicon semiconductor pattern 5 by a single photolithography process.
S40, depositing a metal oxide protective layer 9 on the second gate electrode 8, forming a first source electrode 10 and a first drain electrode 10 'connected to the metal oxide semiconductor pattern 4 on the metal oxide protective layer 9, and forming a second source electrode 11 and a second drain electrode 11' connected to the low temperature polysilicon semiconductor pattern 5 on the metal oxide protective layer 9.
Specifically, the second grid electrode 8 is deposited by a plasma enhanced chemical vapor deposition method to a thickness of
The metal oxide protective layer 9 may be an oxide or an oxynitride, and a reaction gas corresponding to an oxide of silicon may be used as the metal oxide protective layer 9Is SiH4，N2O; nitride or oxynitride corresponding to SiH as the gas4，NH3，N2Or SiH2Cl2，NH3，N2(ii) a And then forming a first via hole 15 and a second via hole 16 through a photolithography process, wherein the first via hole 15 penetrates through the metal oxide protection layer 9 and the gate insulating layer 6 and extends to the metal oxide semiconductor pattern 4 to form a source electrode and a drain electrode of the metal oxide TFT, and the second via hole 16 penetrates through the metal oxide protection layer 9 and the gate insulating layer 6 and extends to the low-temperature polysilicon semiconductor pattern 5 to form a source electrode and a drain electrode of the low-temperature polysilicon TFT.
After the first via hole 15 and the second via hole 16 are formed, the metal oxide protective layer 9 is sequentially deposited by sputtering or thermal evaporation to a thickness of about
The source and drain metal layer can be Cr, W, Ti, Ta, Mo, Al, Cu and other metals or alloys, and the metal layer consisting of multiple layers of metals can also meet the requirement. The first source electrode 10 and the first drain electrode 10 'of the metal oxide TFT, and the second source electrode 11 and the second drain electrode 11' of the low temperature polysilicon TFT are formed by a photolithography process. Wherein the first source electrode 10, the first drain electrode 10 'are deposited in the first via hole 15 to be in contact with the metal oxide semiconductor pattern 4, and the second source electrode 11 and the second drain electrode 11' are deposited in the second via hole 16 to be in direct contact with the low temperature polysilicon semiconductor pattern 5.
In the above method, since the metal oxide TFT is formed in the region corresponding to the display region and is used for driving the pixel electrode 14, the metal oxide TFT has high mobility and very good off-state current, and the driving of the pixel electrode 14 by using the metal oxide TFT can reduce the power consumption of the display panel and can better meet the requirements of large-sized liquid crystal displays and organic light emitting diode display devices.
Optionally, in the at least one buffer layer, the first buffer layer 3 closest to the metal oxide pattern is a silicon oxide layer, and further, after the first buffer layer 3 is formed, an annealing process is performed on the first buffer layer 3.
Specifically, a film having a thickness of successively deposited on the glass substrate 1 on which the first gate electrode 7 and the light shielding pattern 2 are formed by a vapor deposition method of plasma enhanced chemical
The buffer layer of (1) can be deposited with two buffer layers, the bottom layer near the glass substrate is nitride or oxynitride, and the thickness of the deposited layer is
The corresponding reaction gas should be SiH4、NH3、N2Or SiH2Cl2、NH3、N2(ii) a The first buffer layer 3 closest to the metal oxide semiconductor pattern 4 is made of silicon oxide and deposited to a thickness of
The corresponding gas is SiH4，N2O; thus, silicon oxide is in contact with the oxide semiconductor pattern, and if silicon nitride or silicon oxynitride is used for the first buffer layer 3, hydrogen contained therein will diffuse into the metal oxide semiconductor pattern due to its high hydrogen content, resulting in failure of the TFT device.
In order to improve the stability of the device, after the first buffer layer 3 is formed, a high-temperature annealing process is performed to further reduce hydrogen in the buffer layer, and meanwhile, hydrogen explosion can be avoided during subsequent ELA annealing process, and large hydrogen explosion can be prevented during the process of forming the polysilicon TFT while the performance of the metal oxide TFT is improved.
Further, step S40 is followed by:
depositing a passivation layer 13 on the first drain electrode 10 ', the first source electrode 10, the second drain electrode 11 ', and the second source electrode 11, and forming a conductive via 12 on the passivation layer 13 in a region above the first drain electrode 10 ' by a photolithography process;
a transparent conductive layer is deposited on the passivation layer 13 formed with the conductive via 12, and a pixel electrode 14 is formed through a photolithography process, and the pixel electrode 14 is electrically connected to the first drain electrode 10' via the conductive via 12.
Specifically, the metal oxide protective layer 9 is deposited by a plasma-enhanced chemical vapor deposition method to a thickness of
The passivation layer 13 may be an oxide or an oxynitride, and the reaction gas corresponding to the oxide of silicon may be SiH4，N2O; nitride or oxynitride corresponding to SiH as the gas4，NH3，N2Or SiH2Cl2，NH3，N2(ii) a The conductive vias 12 are then formed by a single photolithographic process.
And then has a thickness of about the passivation layer 13
The transparent conductive layer of (2) may be ITO or IZO, or other transparent metal oxides. The pixel electrode 14 is formed through a general photolithography process, and here, the pixel electrode 14 is electrically connected to the first drain electrode 10' via the conductive via 12.
In addition, it should be noted that, in the present embodiment, the metal oxide semiconductor pattern 4 is located in a region corresponding to a display region of the array substrate, and the low temperature polysilicon semiconductor pattern 5 is located in a region corresponding to a non-display region of the array substrate. In this case, the pixel electrode 14 is driven using the metal oxide TFT corresponding to the driving of the peripheral circuit using the low temperature polysilicon TFT (having a characteristic of high mobility), and the power consumption of the display panel can be effectively reduced.
Or the metal oxide semiconductor pattern 4 (first gate 7) and a part of the low temperature polysilicon semiconductor pattern 5 (light shielding pattern 2) are located in a region corresponding to a display region of the array substrate, and the other part of the low temperature polysilicon semiconductor pattern 5 (light shielding pattern 2) is located in a region corresponding to a non-display region of the array substrate. In this case, in the organic light emitting diode display device, the metal oxide TFT is used as a driving TFT and the low temperature polysilicon TFT is used as a switching TFT in the display region, and the low temperature polysilicon TFT is used to drive the peripheral circuit in the non-display region, which also achieves the purpose of effectively reducing the power consumption of the display panel.
The following describes a manufacturing process of the array substrate according to the present invention by taking a specific example.
The method comprises the following steps: the first gate electrode 7 and the light-shielding pattern 2 are formed on the glass substrate 1. Fig. 2 is a schematic structural diagram of the array substrate in the first state in the manufacturing method of the array substrate according to the first embodiment of the present invention, as shown in fig. 2, a gate metal layer is deposited on the glass substrate 1 by sputtering or thermal evaporation, and a first gate electrode 7 and a light-shielding pattern 2 are formed by a common photolithography process. The array substrate is in a first state as shown in fig. 2.
Step two: at least one buffer layer is deposited on the glass substrate 1 on which the first gate electrode 7 and the light-shielding pattern 2 are formed, and a metal oxide semiconductor pattern 4 is formed on the buffer layer. Fig. 3 is a schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate according to an embodiment of the present invention, as shown in fig. 3, two buffer layers are continuously deposited by a plasma enhanced chemical vapor deposition method on the basis of the array substrate in the first state shown in fig. 2, and a high temperature annealing process is performed on the first buffer layer 3 located on the upper layer. Then, a metal oxide semiconductor layer is deposited on the first buffer layer 3 by sputtering or thermal evaporation, and a metal oxide semiconductor pattern 4 is formed by one photolithography process. To form the array substrate in the second state shown in fig. 3.
Step three: fig. 4 is a schematic structural diagram of the array substrate in the third state in the manufacturing method of the array substrate according to the first embodiment of the present invention, first depositing a silicon oxide film 17 on the array substrate in the second state shown in fig. 3, depositing an amorphous silicon film on the silicon oxide film 17, forming the amorphous silicon film into a polysilicon film by using an annealing process, and forming the low-temperature polysilicon semiconductor pattern 5 by using a photolithography process. To form the array substrate in the third state shown in fig. 4.
Step four: a gate insulating layer 6 and a gate metal layer are sequentially deposited on the metal oxide semiconductor pattern 4 and the low temperature polysilicon semiconductor pattern 5, and photolithography is performed to form a second gate electrode 8 over the low temperature polysilicon semiconductor pattern 5.
Fig. 5 is a schematic structural diagram of the array substrate in a fourth state in the manufacturing method of the array substrate according to the first embodiment of the present invention. On the basis of the array substrate in the third state shown in fig. 4, the gate insulating layer 6 is deposited by a plasma enhanced chemical vapor deposition method, then gate metal layers are sequentially deposited on the gate insulating layer 6 by a sputtering or thermal evaporation method, and then the second gate electrode 8 is formed by a common photolithography process. To form the array substrate in the fourth state shown in fig. 5.
Step five: depositing a metal oxide protective layer 9 on the second gate 8, and forming a first via hole 15 and a second via hole 16, fig. 6 is a schematic structural diagram of the array substrate in a fifth state in the manufacturing method of the array substrate according to an embodiment of the present invention, depositing the metal oxide protective layer 9 by a plasma enhanced chemical vapor deposition method on the basis of the array substrate in the fourth state shown in fig. 5, and forming the first via hole 15 and the second via hole 16 by a photolithography process, so as to form the array substrate in the fifth state shown in fig. 6, wherein the first via hole 15 is used as a contact via hole between the first source 10 and the first drain 10 'and the metal oxide semiconductor pattern 4, and the second via hole 16 is used as a contact via hole between the second source 11 and the second drain 11' and the low temperature polysilicon semiconductor pattern 5.
Step six: forming a first drain electrode 10 ', a first source electrode 10, a second drain electrode 11 ', and a second source electrode 11 on the metal oxide protection layer 9, depositing a passivation layer 13 on the first drain electrode 10 ', the first source electrode 10, the second drain electrode 11 ', and the second source electrode 11, and then forming a conductive via 12 on the passivation layer 13 in a region above the first drain electrode 10 ' by a photolithography process. Fig. 7 is a schematic structural diagram of the array substrate in the sixth state in the manufacturing method of the array substrate according to the first embodiment of the present invention, a source-drain metal layer is sequentially deposited on the array substrate in the fifth state shown in fig. 6 by sputtering or thermal evaporation, and a first drain 10 ', a first source 10, a second drain 11', and a second source 11 are formed by a common photolithography process. Next, a passivation layer 13 is deposited on the first drain electrode 10 ', the first source electrode 10, the second drain electrode 11', and the second source electrode 11 by a plasma enhanced chemical vapor deposition method, and a conductive via 12 is formed by a common photolithography process. To form the array substrate in the sixth state shown in fig. 7.
Step seven: a transparent conductive layer is deposited on the passivation layer 13 formed with the conductive via 12, and a pixel electrode 14 is formed through a photolithography process, and the pixel electrode 14 is electrically connected to the first drain electrode 10' via the conductive via 12. Fig. 8 is a schematic structural diagram of the array substrate in a seventh state in the manufacturing method of the array substrate according to the first embodiment of the present invention. On the basis of the array substrate in the sixth state shown in fig. 7, a transparent conductive layer is deposited and a pixel electrode 14 is formed through a general photolithography process, and a portion of the transparent conductive layer is formed in the conductive via 12 to electrically connect the first drain electrode 10' and the pixel electrode 14. The manufacturing process of the array substrate in this embodiment is completed.
In this embodiment, the method for manufacturing an array substrate includes: forming first grid electrodes and shading patterns on the substrate at intervals, wherein the first grid electrodes are positioned in an area corresponding to a display area of the array substrate; depositing at least one buffer layer on the first grid and the shading layer, and forming a metal oxide semiconductor pattern positioned above the first grid and a low-temperature polysilicon semiconductor pattern positioned above the shading layer on the buffer layer; sequentially depositing a grid insulation layer and a grid metal layer on the metal oxide semiconductor pattern and the low-temperature polycrystalline silicon semiconductor pattern, and photoetching to form a second grid above the low-temperature polycrystalline silicon semiconductor pattern; and depositing a metal oxide protective layer on the second gate electrode, forming a first source electrode and a first drain electrode connected with the metal oxide semiconductor pattern on the metal oxide protective layer, and forming a second source electrode and a second drain electrode connected with the low-temperature polysilicon semiconductor pattern on the metal oxide protective layer. The metal oxide TFT is formed in the area corresponding to the display area and used for driving the pixel electrode, the metal oxide TFT is high in mobility and has very good off-state current, the power consumption of the display panel can be reduced by driving the pixel electrode with the metal oxide TFT, the metal oxide TFT is matched with the low-temperature polysilicon TFT for use, the requirement of the display panel on high mobility can be met, the power consumption can be reduced, and the requirements of large-size liquid crystal displays and organic light emitting diode display devices can be better met.
Example two
The present embodiment provides an array substrate manufactured by the manufacturing method of the first embodiment, fig. 9 is a schematic structural diagram of an array substrate provided by the second embodiment of the present invention, and as shown in fig. 9, the array substrate of the present embodiment includes at least one metal oxide thin film transistor and at least one low temperature polysilicon thin film transistor disposed on a glass substrate 1. The metal oxide thin film transistor comprises a metal oxide semiconductor pattern 4, a grid insulating layer 6, a first grid 7, a metal oxide protective layer 9, at least one buffer layer, a silicon oxide film 17, a first source electrode 10 and a first drain electrode 10 ', wherein the at least one buffer layer covers the first grid 7, the metal oxide semiconductor pattern 4 is arranged on the at least one buffer layer and is positioned above the first grid 7, the silicon oxide film 17 and the grid insulating layer 6 cover the metal oxide semiconductor pattern 4, the metal oxide protective layer 9 covers the grid insulating layer 6, first through holes 15 are arranged on the metal oxide protective layer 9, the grid insulating layer 6 and the silicon oxide film 17, and the first source electrode 10 and the first drain electrode 10' are in contact with the metal oxide semiconductor pattern 4 through the first through holes 15.
The low-temperature polycrystalline silicon thin film transistor comprises a shading graph 2, at least one buffer layer, a silicon oxide film 17, a low-temperature polycrystalline silicon semiconductor graph 5, a grid insulating layer 6, a second grid 8, a metal oxide protective layer 9, a second source electrode 11 and a second drain electrode 11', wherein the at least one buffer layer and the silicon oxide film 17 sequentially cover the shading graph 2, the low-temperature polycrystalline silicon semiconductor graph 5 is arranged on the silicon oxide film 17, and is located above the light-shielding pattern 2, a gate insulating layer 6 is covered on the low temperature polysilicon semiconductor pattern 5, a second gate 8 is disposed on the gate insulating layer 6, and is located above the low temperature polysilicon semiconductor pattern 5, the metal oxide protective layer 9 is covered on the gate insulating layer 6 and the second gate 8, and a second via hole 16 is provided on the metal oxide protective layer 9 and the gate insulating layer 6, and the second source electrode 11 and the second drain electrode 11' are in contact with the low temperature polysilicon semiconductor pattern 5 through the second via hole 16.
In addition, the array substrate further comprises a passivation layer 13 disposed above the metal oxide protective layer 9, and a pixel electrode 14, wherein a conductive via 12 is disposed on the passivation layer 13, and the pixel electrode 14 is electrically connected to the first drain electrode 10' through the conductive via 12.
The array substrate of the embodiment is manufactured by the manufacturing method of the first embodiment, because the metal oxide TFT is formed in the area corresponding to the display area and used for driving the pixel electrode, the metal oxide TFT has high mobility and very good off-state current, the power consumption of the display panel can be reduced by using the metal oxide TFT to drive the pixel electrode, and the metal oxide TFT is matched with the low-temperature polysilicon TFT for use, so that the requirement of the high mobility of the display panel can be met, the power consumption can be reduced, and the requirements of large-size liquid crystal displays and organic light emitting diode display devices can be better met.
EXAMPLE III
The present embodiment provides a display panel, which includes the array substrate in the second embodiment, wherein the specific structure and function of the array substrate have been described in detail in the second embodiment, and thus are not described herein again.
The display panel may be a liquid crystal display panel, and at this time, the display panel includes a color film substrate, a liquid crystal layer, and the array substrate according to the second embodiment, where the liquid crystal layer is sandwiched between the color film substrate and the array substrate.
The display panel may also be an organic light emitting diode display panel, and in this case, the display panel includes the array substrate, the encapsulation layer, and the organic layer described in the second embodiment, where the organic layer is sandwiched between the array substrate and the encapsulation layer.
In the description of the present invention, it is to be understood that the terms "center", "length", "width", "thickness", "top", "bottom", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "inner", "outer", "axial", "circumferential", and the like, which are used to indicate the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplification of the description, and do not indicate or imply that the position or element referred to must have a particular orientation, be of particular construction and operation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; may be mechanically coupled, may be electrically coupled or may be in communication with each other; either directly or indirectly through intervening media, such as through internal communication or through an interaction between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is at a lesser elevation than the second feature.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.
Claims (10)
1. An array substrate, comprising: the transistor comprises a substrate base plate, and at least one metal oxide thin film transistor and at least one low-temperature polycrystalline silicon thin film transistor which are arranged on the substrate base plate;
the metal oxide thin film transistor comprises a first grid, at least one buffer layer, a metal oxide semiconductor graph, a silicon oxide film, a grid insulation layer and a metal oxide protection layer which are sequentially arranged, the metal oxide thin film transistor also comprises a first source electrode and a first drain electrode, first through holes are formed in the metal oxide protection layer, the grid insulation layer and the silicon oxide film, and the first source electrode and the first drain electrode are in contact with the metal oxide semiconductor graph through the first through holes;
the low-temperature polycrystalline silicon thin film transistor comprises at least one buffer layer, a silicon oxide film, a low-temperature polycrystalline silicon semiconductor graph, a grid insulation layer, a second grid and a metal oxide protective layer which are sequentially arranged, the low-temperature polycrystalline silicon thin film transistor further comprises a second source electrode and a second drain electrode, the metal oxide protective layer and the grid insulation layer are provided with second through holes, and the second source electrode and the second drain electrode are in contact with the low-temperature polycrystalline silicon semiconductor graph through the second through holes.
2. The array substrate of claim 1, further comprising a passivation layer disposed over the metal oxide protective layer, wherein a conductive via is disposed on the passivation layer, and a pixel electrode electrically connected to the first drain electrode through the conductive via.
3. The array substrate of claim 1, wherein a first buffer layer of the at least one buffer layer closest to the metal oxide pattern is a silicon oxide layer.
4. The array substrate of claim 3, wherein the first buffer layer has a thickness of
5. The array substrate of claim 1, wherein the low temperature polysilicon thin film transistor further comprises a light shielding pattern between the at least one buffer layer and the substrate base plate and under the low temperature polysilicon semiconductor pattern.
6. The array substrate of claim 5, wherein the light-shielding pattern and the first gate are formed in a same photolithography process.
7. The array substrate of claim 5,
the shading graph is positioned in an area corresponding to the non-display area of the array substrate.
8. The array substrate of any one of claims 1-7, wherein the metal oxide semiconductor pattern is Indium Gallium Zinc Oxide (IGZO).
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. The display panel according to claim 9, wherein the display panel is a liquid crystal display panel or an organic light emitting diode display panel.
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| CN201921789816.1U CN210272364U (en) | 2019-10-23 | 2019-10-23 | Array substrate and display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113113424A (en) * | 2021-03-17 | 2021-07-13 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113113424A (en) * | 2021-03-17 | 2021-07-13 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| CN113113424B (en) * | 2021-03-17 | 2024-02-02 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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Address after: No. 1778, Qinglan Road, Huangjia Street, Shuangliu District, Chengdu, Sichuan 610200 Patentee after: Chengdu BOE Display Technology Co.,Ltd. Country or region after: China Address before: No. 1778, Qinglan Road, Gongxing street, Shuangliu District, Chengdu, Sichuan 610200 Patentee before: CHENGDU ZHONGDIAN PANDA DISPLAY TECHNOLOGY Co.,Ltd. Country or region before: China |