CN210270871U

CN210270871U - Redundant fault-tolerant computer serial port gating device

Info

Publication number: CN210270871U
Application number: CN201921083289.2U
Authority: CN
Inventors: 包健; 王小青; 韩正伟
Original assignee: No 60 Institute of Headquarters of General Staff of PLA
Current assignee: No 60 Institute of Headquarters of General Staff of PLA
Priority date: 2019-07-11
Filing date: 2019-07-11
Publication date: 2020-04-07
Anticipated expiration: 2029-07-11

Abstract

The utility model discloses a redundant fault-tolerant computer serial ports gating device. The device is used in a redundant fault-tolerant computer and consists of an arbitration CPU module, a monostable oscillator module and a serial port conversion module; the arbitration CPU module sends serial port output signal D to the serial port conversion module and sends enable control signal C1 to the monostable oscillator module; the monostable oscillator module sends an enable control signal C2 to the serial port conversion module; the serial port conversion module judges whether the serial port signal is to be output or set to be in a high impedance state according to the enable control signal C2. The device can realize the channel switching of serial port output, prevent that the I/O foot of CPU from causing the false triggering when breaking down or chip level trouble takes place, improves the reliability and the security of redundant fault-tolerant computer.

Description

Redundant fault-tolerant computer serial port gating device

Technical Field

The utility model belongs to redundant fault-tolerant equipment technique and application, specific device that is used for unmanned aerial vehicle redundancy flight control computer that says so.

Background

In order to improve the reliability and fault-tolerant capability of the redundancy flight control computer of the unmanned aerial vehicle, the best method is to take measures from the system, namely, adopt redundancy fault-tolerant technology, such as a dual-channel redundancy fault-tolerant computer with primary fault safety, a three-channel redundancy fault-tolerant computer with primary fault working capability, a four-channel redundancy fault-tolerant computer with secondary fault working capability, and the like. The method comprises the steps that an I/O pin of a CPU is directly used for controlling the enabling of a serial port level conversion chip, once the I/O pin of the CPU fails, an enable invalid signal (low level) is sent out under the condition that an enable valid signal (high level) is normally sent out, or an enable valid signal (high level) is sent out under the condition that the enable invalid signal (low level) is normally sent out, the output logic of the channel serial port data is wrong, the actual output is influenced, and the data finally sent to a communication peripheral device is abnormal.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that, to the shortcoming of above prior art, provide a redundant fault-tolerant computer serial ports gating device, in order to solve above-mentioned technical problem, the technical scheme of the utility model is realized through following mode:

a redundant fault-tolerant computer serial port gating device comprises an arbitration CPU module, a monostable oscillator module and a serial port conversion module, wherein the arbitration CPU module is provided with a serial port signal output end and an enabling control signal output end, the monostable oscillator is provided with an input end and an output end, and the serial port conversion module is provided with an input end, a judgment end and an output end;

the serial port signal output end is connected with the signal input end of the serial port conversion module, the enabling control signal output end is connected with the input end of the monostable oscillator module, the output end of the monostable oscillator is connected with the judging end of the serial port conversion module, and the output end of the serial port module is connected with a communication peripheral.

The enabling control signal output by the arbitration CPU module comprises square waves, a constant low level and a constant high level, and the enabling control signal output by the monostable oscillator module is a constant high level or a constant low level.

If the monostable oscillator module does not receive the edge signal from the arbitration CPU module in the specified period, the output end enables the control signal to output low level; otherwise, a high level is output.

If the enable signal of the arbitration CPU module outputs square waves and the monostable oscillator module outputs high level, the output end of the serial port conversion module outputs signals input by the arbitration CPU module; otherwise, the output end of the serial port conversion module has no output and is in a high impedance state.

Compared with the prior art, the utility model can effectively ensure that the output of the serial port level conversion chip can not be triggered by mistake when the I/O pin of the arbitration CPU for controlling the serial port level conversion chip to enable fails, and the output can not be triggered by mistake when the chip-level failure occurs; meanwhile, the chip fault can be automatically detected and the channel can be automatically switched.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

FIG. 1 is a basic block diagram of the present invention;

FIG. 2 is a schematic diagram of a monostable oscillator module of the present invention;

fig. 3 is a block diagram of embodiment 1 of the present invention;

fig. 4 is a block diagram of embodiment 2 of the present invention.

Detailed Description

The following is a detailed description of the present invention:

in order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail with reference to the accompanying drawings and embodiments. The specific embodiments described are merely illustrative of the invention and should not be used to limit the scope of the invention.

Preferably, the arbitration CPU module is implemented using an FPGA.

Preferably, the serial port conversion module is implemented by selecting a chip with the model number of ADM3076E, and the multiple serial port conversion modules can be controlled by the same enable signal or different enable signals according to actual control requirements.

Preferably, the monostable trigger is realized by selecting a chip with the model number of SN74LVC1G123, the driving current of the chip can reach 100mA, and the driving capability of an output signal meets the requirement of directly controlling the enabling of the multi-path serial port conversion module; the serial port conversion module selects a chip with the model ADM3076E, DE (output enable) and RE (input enable) pins of the chip adopt a hot plug input structure, and the output is in a high impedance state when the chip is forbidden or switched off. The output signal of SN74LVC1G123 is normally steady at a low level and is normally non-steady at a high level.

As shown in FIG. 2, the arbitration CPU module sends an enable control signal C1 to the pin 2 of D2 via a series inductor, the pin 1 of D2 is grounded, the pin 3 is connected to a +3.3V signal power supply, R1 is a 10k Ω resistor, C1 is a 0.1uF capacitor, the two ends of R1 are respectively connected to the pin 7 and the pin 8 of D2, the two ends of C1 are respectively connected to the pin 6 and the pin 7 of D2, and C2 is the pin 5 of the monostable oscillator module, and sends the enable control signal C1 to the serial port conversion module.

Example 1:

as shown in fig. 3, a redundant fault-tolerant computer serial port gating device forms a dual-redundancy system, which is composed of a channel a and a channel B, wherein each channel comprises a monostable trigger module and a serial port conversion module. C1 is the enable signal sent by channel A arbitration CPU module, C2 is the enable signal sent by channel A monostable trigger module, D1 is the serial port signal of channel A, B1 is the feedback of C2 signal; c3 is the enable signal sent by the channel B arbitration CPU module, C4 is the enable signal sent by the channel B monostable trigger module, D2 is the channel B serial signal, B2 is the feedback of the C4 signal; d4 is the two-in-one of the output serial port signals of the channel A and the channel B; BD is the feedback of the D4 signal.

If the channel A is used by default when no fault exists after power-on starting, enabling the channel A to be effective (C1 is square wave and C2 is high), enabling the channel B to be ineffective (C3 is low and C4 is low), and then D4 is not equal to D1; if the arbitration CPU logic switches to channel B, then channel A enable is inactive (C1 is low, C2 is low) while channel B enable is active (C3 is square wave, C4 is high), where D [4] = D [2 ].

If the I/O pin of the arbitration CPU module sending out the enabling signal C1 is failed, the channel A is enabled and disabled (C1 is unstable, at this time, square waves in a specified frequency range cannot be sent out, C2 is low), and meanwhile, the channel B is enabled and disabled (C3 is low, C4 is low), at this time, D4 has no output; the arbitration CPU module detects the channel A is failed (B1 is low, B2 is low, BD is no signal), then switches to using channel B, the channel A enable is invalid (C1 is non-stable, C2 is low), the channel B enable is valid (C3 is square wave, C4 is high), at this time D4 = D2, and identifies the channel A failure.

If the I/O pin of the arbitration CPU module sending out the enable signal C3 is in fault, the arbitration CPU cycle detection logic is switched to the channel B, the channel A is enabled to be invalid (C1 is low, C2 is low), meanwhile, the channel B is enabled to be invalid (C3 is unstable, at this time, square waves in a specified frequency range cannot be sent out, C4 is low), at this time, D4 has no output; the arbitration CPU module detects that channel B has a fault (B1 is low, B2 is low, BD has no signal), then switches to using channel A, so that the enable of channel A is valid (C1 is square wave, C2 is high), and the enable of channel B is invalid (C3 is non-stable, C4 is low), at this time D4 = D1, and identifies the fault of channel B.

If the monostable oscillator module 1 is in fault, the channel A is enabled and disabled (C1 is square wave, C2 is low), meanwhile, the channel B is enabled and disabled (C3 is low, C4 is low), and at this time, D4 has no output; the arbitration CPU module detects that channel A is failed (B1 is low, B2 is low, BD is no signal), then switches to using channel B, so that the channel A enable is invalid (C1 is low, C2 is low), and the channel B enable is valid (C3 is square wave, C4 is high), at which time D4 = D2, and identifies the channel A failure.

If the monostable oscillator module 2 is in fault, the arbitration CPU period detection logic is switched to the use channel B, the channel A is enabled and invalid (C1 is low, C2 is low), meanwhile, the channel B is enabled and invalid (C3 is square wave, C4 is low), and at the moment, D4 has no output; the arbitration CPU module detects that channel B is failed (B1 is low, B2 is low, BD is no signal), then switches to using channel A, so that the channel A enable is valid (C1 is square wave, C2 is high), and the channel B enable is invalid (C3 is low, C4 is low), at which time D4 = D1, and identifies the channel B failure.

If the serial port conversion module 3 is in fault, the channel A is enabled to be effective (C1 is square wave, C2 is high), and the channel B is enabled to be ineffective (C3 is low, C4 is low), but at the moment, D4 has no output; the arbitration CPU module detects that the channel A serial port conversion module 3 has a fault (B1 is high, B2 is low, BD has no signal), then switches to the channel B, so that the channel A is enabled to be invalid (C1 is low, C2 is low), and the channel B is enabled to be valid (C3 is square wave, C4 is high), at this time, D4 is not equal to D2, and identifies the channel A fault.

If the serial port conversion module 4 is in fault, the arbitration CPU period detection logic is switched to the use channel B, the channel A is enabled to be invalid (C1 is low, C2 is low), meanwhile, the channel B is enabled to be valid (C3 is square wave, C4 is high), but at the moment, D4 is not output; the arbitration CPU module detects that the channel B serial port conversion module 4 has a fault (B1 is low, B2 is high, BD has no signal), then switches to the channel A, so that the channel A is enabled to be valid (C1 is square wave, C2 is high), and the channel B is enabled to be invalid (C3 is low, C4 is low), at this time, D4 = D1, and identifies the channel B fault.

Example 2:

as shown in fig. 4, a redundant fault-tolerant computer serial port gating device forms a triple redundancy system, which comprises a channel a, a channel B and a channel C, wherein each channel comprises a monostable trigger module and a serial port conversion module. C1 is the enable signal sent by channel A arbitration CPU module, C2 is the enable signal sent by channel A monostable trigger module, D1 is the serial port signal of channel A, B1 is the feedback of C2 signal; c3 is the enable signal sent by the channel B arbitration CPU module, C4 is the enable signal sent by the channel B monostable trigger module, D2 is the channel B serial signal, B2 is the feedback of the C4 signal; c5 is the enable signal sent by the channel C arbitration CPU module, C6 is the enable signal sent by the channel C monostable trigger module, D3 is the channel C serial port signal, B3 is the feedback of the C6 signal; d4 is the three-in-one of the output serial port signals of the channel A, the channel B and the channel C; BD is the feedback of the D4 signal.

If the channel A is used by default when no fault exists after power-on starting, enabling the channel A to be effective (C1 is a square wave, C2 is high), enabling the channel B to be ineffective (C3 is low, C4 is low), enabling the channel C to be ineffective (C5 is low, C6 is low), and then D4 is = D1; if the arbitration CPU logic switches to channel B, then channel A enable is invalid (C1 is low, C2 is low), while channel B enable is valid (C3 is square wave, C4 is high), while channel C enable is invalid (C5 is low, C6 is low), at which time D [4] = D [2 ]; if the arbitration CPU logic switches to channel C, then channel A is disabled (C1 is low, C2 is low), while channel B is disabled (C3 is low, C4 is low), while channel C is enabled (C5 is a square wave, C6 is high), at which time D [4] = D [3 ].

The detection and control method for arbitrating faults of the I/O pin of the CPU module for sending the enabling signal, the monostable oscillator module 1, the monostable oscillator module 2, the monostable oscillator module 3, the serial port conversion module 4, the serial port conversion module 5 and the serial port conversion module 6 is similar to that of the embodiment 1, and description is omitted.

It will be apparent to those skilled in the art that the block diagrams in the embodiments are primarily intended for redundant fault-tolerant computers, including but not limited to redundant fault-tolerant flight controllers, redundant fault-tolerant data acquisition and storage devices, and the like.

It is clear to those skilled in the art that the serial port conversion module described in the embodiments is an RS422 isolated differential signal transceiver, but is not limited to RS422 signals, and in fact, a slight modification of the serial port level conversion chip with output enable for signal communication of RS232, RS485, etc. may also be used in this output enable mode.

The above embodiments are only for illustrating the preferred embodiments of the present invention, and certainly, the protection scope of the present invention should not be limited thereto, so that the equivalent changes made according to the claims of the present invention or any changes made on the basis of the technical solutions of the present invention all fall within the protection scope of the present invention.

Claims

1. The utility model provides a redundant fault-tolerant computer serial ports gating device, includes arbitration CPU module, monostable oscillator module, serial ports conversion module, its characterized in that: the arbitration CPU module is provided with a serial port signal output end and an enabling control signal output end, the monostable oscillator is provided with an input end and an output end, and the serial port conversion module is provided with an input end, a judgment end and an output end;

2. The redundant fault-tolerant computer serial port gating apparatus of claim 1, wherein: the enabling control signal output by the arbitration CPU module comprises square waves, a constant low level and a constant high level, and the enabling control signal output by the monostable oscillator module is a constant high level or a constant low level.

3. The redundant fault-tolerant computer serial port gating apparatus of claim 1, wherein: if the monostable oscillator module does not receive the edge signal from the arbitration CPU module in the specified period, the output end enables the control signal to output low level; otherwise, a high level is output.

4. The redundant fault-tolerant computer serial port gating apparatus of claim 1, wherein: if the enable signal of the arbitration CPU module outputs square waves and the monostable oscillator module outputs high level, the output end of the serial port conversion module outputs signals input by the arbitration CPU module; otherwise, the output end of the serial port conversion module has no output and is in a high impedance state.