CN210224021U - Peripheral wiring structure of display panel, display panel and display device - Google Patents
Peripheral wiring structure of display panel, display panel and display device Download PDFInfo
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Abstract
The application discloses a display panel and a display device, wherein the display panel is divided into a display area and a non-display area, and comprises peripheral wiring formed in the non-display area; the peripheral routing includes: the display device comprises a plurality of first signal lines, a plurality of second signal lines and a conductive layer, wherein the plurality of first signal lines are vertical to the plurality of second signal lines; the plurality of second signal lines and the plurality of first signal lines are formed on different layers and are insulated from each other, and the plurality of first signal lines are respectively in one-to-one corresponding conduction with the plurality of corresponding second signal lines; the overlapping of the first signal line and the non-conducting second signal line forms an overlapping area, wherein the position of the first signal line corresponding to at least one overlapping area is disconnected to form a notch, correspondingly, the conducting layer is arranged at the notch, and the conducting layer conducts the first signal lines on two sides of the notch; the risk of charge build-up leading to electrostatic shock is reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to a peripheral wiring structure of a display panel, the display panel and a display device.
Background
At present, when the display panel is manufactured, the flexible circuit board and the central control board are attached to the combined section of the display panel, and then the display panel can be lightened. The display panel is divided into a display area and a non-display area, and peripheral wiring is arranged in the non-display area, for example, the display panel needs to infuse signals into the display area through the peripheral wiring in a test stage, such as array test (array test), cell curing (discharge cell repair), celltest (dot screen test) and the like, and at this time, the signals can only be transmitted into the display area through the peripheral wiring, cross lines are generated in the transmission process, namely, metal layers are overlapped, and electrostatic breakdown is easy to cause the short circuit of the metal layers, so that the function is abnormal; especially, at the position of large metal overlapping or metal overline, the routing area is large, more charges are easy to accumulate, and electrostatic explosion at the overlapping position is easier to occur.
How to avoid appearing electrostatic breakdown in overlap position department for the function is normal, improves the yield, becomes the problem that this technical field emptys.
SUMMERY OF THE UTILITY MODEL
The application aims to provide a peripheral wiring structure of a display panel, the display panel and a display device, and static electricity explosion injury in an overlapped area is prevented.
The application discloses a peripheral wiring structure of a display panel, which is formed in a non-display area of the display panel and comprises a plurality of first signal lines, a plurality of second signal lines and a conductive layer; the plurality of first signal lines are perpendicular to the plurality of second signal lines; the plurality of second signal lines and the plurality of first signal lines are formed on different layers and are insulated from each other, and the plurality of first signal lines are respectively in one-to-one corresponding conduction with the plurality of corresponding second signal lines; the first signal line and the second signal line which is not conducted are overlapped to form an overlapping area; the position of the first signal line corresponding to at least one overlapping area is disconnected to form a notch, correspondingly, the conductive layer is arranged at the notch, and the conductive layer is conducted with the first signal lines on two sides of the notch.
Optionally, the first signal lines are parallel to the edge of the display area of the display panel, and the plurality of second signal lines are along a direction perpendicular to the first signal lines; correspondingly, the conductive layer crosses the overlapping area along the extending direction line of the first signal line, and the conductive layer conducts the first signal lines on two sides of the gap.
Optionally, the second signal lines are parallel to the edge of the display area, the plurality of first signal lines are fed into the display area along a direction perpendicular to the second signal lines, correspondingly, the conductive layer crosses over the overlapping area along the direction of the first signal lines, and the conductive layer conducts the first signal lines on two sides of the gap.
Optionally, the second signal line is disconnected corresponding to the overlapping region, and the peripheral routing further includes: and the fourth signal line and the first signal line are arranged on the same layer, the conductive layer crosses the overlapping area, and the conductive layer is conducted with the first signal lines on two sides of the notch. The fourth signal line is conducted with the second signal line.
Optionally, the display panel includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third conductive layer, which are sequentially stacked; the first signal line is formed on the first metal layer, the second signal line is formed on the second metal layer, and the conductive layer is formed on the third conductive layer.
Optionally, the display panel includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third conductive layer, which are sequentially stacked; the first signal line is formed on the second metal layer, the second signal line is formed on the first metal layer, and the conductive layer is formed on the third conductive layer.
Optionally, the line width of the conductive layer is greater than or equal to the line width of the first signal line.
Optionally, the display panel further includes: the display panel comprises a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a transparent conducting layer which are sequentially stacked; the first signal line is formed on the first metal layer and extends along the edge parallel to the display area; the second signal lines are formed on the second metal layers and are fed into the display area perpendicular to the edge of the display area, and the first metal layers are respectively communicated with the corresponding second metal layers one by one;
the first insulating layer is formed on the first metal layer; the second insulating layer is formed on the second metal layer; the thickness of the second insulating layer is greater than that of the first insulating layer; a first via hole penetrating through the first insulating layer and connected to one end of the broken gap of the first metal layer; the second through hole penetrates through the first insulating layer and is connected with the disconnected other end of the first signal line; the conductive layer is formed on the transparent conductive layer, and the transparent conductive layer conducts the first metal layer through a first via hole and a second via hole.
The application also discloses a display panel, the non-display area includes the above peripheral wiring structure.
The application also discloses a display device, which comprises the display panel, a driving circuit for driving the display panel and a chip on film connected with the driving circuit and the display panel.
The first signal line and the second signal line overlap of this application different layers forms the overlap region, the first signal line disconnection of corresponding overlap region, the area on the line is walked to the place periphery that first signal line can reduce static, can prevent that large tracts of land periphery from walking accumulation charge, use the conducting layer to switch on simultaneously, it concatenates to switch on back all walks between the line, the static of accumulation can be fast because the conducting layer switches on periphery and walks the line and disperse to whole display panel, the risk that the charge accumulation leads to the static damage has been reduced, the product yield is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram of a display device according to an embodiment of the present application;
FIG. 2 is a top view of a first signal line broken according to an embodiment of the present application;
FIG. 3 is a broken top view of a first metal layer of an embodiment of the present application;
FIG. 4 is a broken top view of a second metal layer of an embodiment of the present application;
FIG. 5 is a top view of an embodiment of the present application with signal lines simultaneously broken;
FIG. 6 is a cross-sectional view of a routing area of an embodiment of the present application.
100, a display panel; 110. a display area; 120. a non-display area; 130. peripheral wiring; 131. a first signal line; 132. a second signal line; 133. an overlap region; 134. a notch; 135. a first metal line; 136. a second metal line; 140. a conductive layer; 141. a third conductive layer; 142. a fourth signal line; 150. a substrate, 151, a first metal layer; 152. a second metal layer; 153. a first insulating layer; 154. a second insulating layer; 155. a first via hole; 156. a second via hole; 200. a display device.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
As shown in fig. 1 to 2, as an embodiment of the present application, a display device 200 is disclosed, which includes a display panel 100, wherein the display panel 100 is divided into a display area 110 and a non-display area 120, and includes a peripheral trace 130 formed in the non-display area 120; the peripheral trace 130 includes a plurality of first signal lines 131, a plurality of second signal lines 132, and a conductive layer 140; the first signal lines 131 are perpendicular to the second signal lines 132; the plurality of second signal lines 132 and the plurality of first signal lines 131 are formed on different layers and are insulated from each other, and the plurality of first signal lines 131 are respectively in one-to-one correspondence with the plurality of second signal lines 132; the overlapping of the first signal line 131 and the non-conductive second signal line 132 forms an overlapping region 133, wherein the first signal line 131 is disconnected at a position corresponding to at least one overlapping region 133 to form a notch 134, correspondingly, the conductive layer 140 is disposed at the notch 134, and the conductive layer 140 connects the first signal lines 131 on two sides of the notch 134.
For the display panel 100, for the peripheral trace 130 in the routing area in the non-display area 120, the trace can be designed to be wider in order to reduce the trace resistance, and therefore the trace can have a large area. The arrows indicate directions, the present application first corresponds to the overlapping regions 133 of the first signal lines 131 and the second signal lines 132 of different layers, the first signal line 131 is disconnected to form a gap 134 corresponding to at least one overlapping region 133, the gap 134 can reduce the area of the static electricity on the peripheral wiring 130, and can prevent the large-area peripheral wiring 130 from accumulating charges, meanwhile, the conductive layer 140 is used to conduct the first signal lines 131 on both sides of the gap 134 on the uppermost layer, the wirings are connected in series, the static electricity accumulated by depositing the first signal line 131 can be quickly dispersed to the whole display panel 100 because the conductive layer 140 deposited at the last conducts the peripheral wiring 130, the risk of static damage caused by charge accumulation is reduced, and the product yield is improved.
The line width of the conductive layer 140 may be greater than or equal to the line width of the first signal line 131, the width of the conductive layer 140 is d2, and the width of the first signal line 131 is d1, so as to reduce the resistance of the conductive layer 140, conduct the first signal line 131 to quickly take away the accumulated charges to disperse to the display panel 100, avoid the occurrence of charge accumulation due to wire breakage, and reduce the yield; of course, the length of the conductive layer 140 across the overlapping region 133 is greater than or equal to the length of the overlapping region, the width of the overlapping region is w1, the width of the conductive layer 140 is w2, the length of the conductive layer 140 is equal to the length of the opening gap 134, the longer the opening length is, the less the accumulated charges are, the smaller the probability of electrostatic breakdown is, and the static electricity is rapidly dispersed after the opening; of course, the material of the conductive layer 140 may be the same as that of the transparent conductive electrode, so as to save material cost, and the manufacturing process may be performed simultaneously with the pixel electrode in the display panel 100, thereby reducing the manufacturing time and the manufacturing cost.
The display panel has four edges, a first direction C1 and a second direction C2 defined by taking one edge as an example, the first direction C1 and the second direction C2 are only relative to the first signal line and the second signal line at one edge of the display panel, and the first direction C1 of the four edges may be different. As an embodiment shown in fig. 3, the first direction C1 may be parallel to the edge of the display area 110 of the display panel, the first signal line extends along a first direction C1, and the plurality of second signal lines 132 feed into the display area along a direction perpendicular to the first signal line 131; correspondingly, the conductive layer crosses the overlapping region along the extending direction of the first signal line to conduct the first signal line 131 on both sides of the gap 134; particularly, in the overlapping region 133 of the first signal line 131 and the second signal line 132, the risk of electrostatic breakdown is greatest, the first signal line 131 in the first direction is firstly disconnected in the overlapping region, so as to reduce the area of the accumulated charges of the first signal line 131, when the conductive layer 140 conducts the notch 134 of the first signal line 131 along the edge parallel to the display region 110, the conductive layer 140 conducts so that the first signal line 131 is connected in series with the display panel 100, the charges accumulated on both sides of the notch 134 on the first signal line 131 can be quickly taken away, the accumulated charges are dispersed on the display panel 100, electrostatic aggregation cannot be caused, the peripheral wiring 130 is short-circuited, and the signal abnormality of the adjacent peripheral wiring 130 is caused.
Specifically, the display panel 100 includes a first metal layer 151, a first insulating layer 153, a second metal layer 152, a second insulating layer 154, and a third conductive layer 141, which are sequentially stacked; the first signal line 131 is formed on the first metal layer 151, the second signal line 132 is formed on the second metal layer 152, and the conductive layer 140 is formed on the third conductive layer 141; firstly, the first metal layer 151 is deposited, the area is large, static electricity is easily attached to the first metal layer 151, the position, corresponding to the overlapping area 133, on the first metal layer 151 is disconnected to form a notch 134, the probability that the static electricity falls on the first metal layer 151 is reduced, the third conducting layer 141 is used for conducting, charges accumulated on the first metal layer 151 are rapidly taken away, and static electricity breakdown is avoided, secondly, the distance between the first metal layer 151 and the third conducting layer 141 is longest, so that the static electricity area between the first metal layer 151 and the second metal layer 152 is reduced, and the register capacitance is reduced; of course, the overlapping area of the transmission line signal line and the clock signal line may also be broken to form the notch 134, and the third conductive layer 141 is used for conducting, so as to avoid signal transmission errors.
Taking three first metal lines 135 and three second metal lines 136 as an example, the first metal lines 135 and the second metal lines 136 are connected through metal bridging holes, each first metal line 135 and each second metal line 136 are in one-to-one correspondence conduction, the first metal lines 135 and the second metal lines 136 are different layers, the first metal lines 135 and the second metal lines 136 are overlapped to form three overlapping regions, at least two places of the first metal lines 135 corresponding to the overlapping regions 133 are disconnected to form notches 134, the conductive layer 140 is arranged on the second metal lines 136, the first metal lines 135 on two sides of the notches 134 are connected, the three overlapping regions 133 are disconnected to form two notches 134, under the condition that the routing is normal, the area of the first metal lines 135 is maximally reduced, and electrostatic breakdown is maximally prevented; of course, the first metal lines 135 corresponding to the overlapping regions 133 may also be all disconnected, the area of the all disconnected first metal lines 135 is reduced, the probability of static electricity falling on the first metal lines 135 is reduced, electrostatic breakdown is avoided, and the normal function of the wiring is ensured.
Referring to fig. 4, another embodiment is shown, which is different from the above embodiments in that the first direction C1 is directly fed into the display area 110, the second direction C2 is parallel to the edge of the display area 110, the second direction is perpendicular to the first direction, and correspondingly, the conductive layer 140 crosses the overlapping area along the first direction to connect the first signal lines 131 on both sides of the gap 134; avoid causing the electrostatic breakdown in the place that feeds into display area 110 nearer, cause unnecessary repair cost, waste time and energy, at first, correspond the first signal line 131 that disconnection overlap region directly fed into display area 110 in the first direction, the static that first signal line 131 bore at this moment probably directly causes the influence to display area 110, influence the display effect, the disconnection, form breach 134, the area of static has been reduced, and then the existence of electric charge has been reduced, use conducting layer 140 to switch on, directly disperse static to display panel 100 on, promote the yield.
Specifically, the first signal line 131 is formed on the second metal layer 152, the second signal line 132 is formed on the first metal layer 151, and the conductive layer 140 is formed on the third conductive layer 141; the overlapping area of the second metal layer 152 near the display area 110 is disconnected to form the gap 134, so as to reduce the area of the second metal layer 152 contacting with static electricity, and the third conductive layer 141 is used for conducting, taking away the accumulated charges, and dispersing, thereby improving the yield of the display panel 100.
In addition, as shown in fig. 5, another embodiment is further shown, the second signal line 132 is also disconnected corresponding to the overlapping area 133, the peripheral trace 130 further includes a fourth signal line 142, the fourth signal line 142 is disposed on the same layer as the first signal line 131, the conductive layer crosses the overlapping area, and the conductive layer connects the first signal lines 131 on two sides of the notch 134. The fourth signal line 142 connects the second signal line 132; the fourth signal line 142 is formed from the first signal line 131 at the same time, and is in the same layer, and at this time, the signal lines in the overlapped region are simultaneously disconnected, and the signal line disconnected in the previous layer is conducted, and the signal line on the uppermost layer is conducted by the conductive layer 140, so that the electrostatic area falling on the signal line in the assembly is reduced to the maximum, the probability of electrostatic explosion damage is prevented from being reduced, and the yield is improved.
As a specific embodiment of the present application, the display panel 100 includes a peripheral trace 130 formed in the non-display area 120, where the peripheral trace 130 includes: a first metal line 135, a second metal line 136, and a conductive layer 140; the first metal lines 135 extend parallel to the edge of the display area 110, the second metal lines 136 are fed into the display area 110 perpendicular to the edge of the display area 110, the second metal lines 136 are disposed above the first metal lines 135, the first metal lines 135 are respectively in one-to-one conduction with the corresponding second metal lines 136, the first metal lines 135 and the second metal lines 136 are overlapped to form an overlapping region, and the first metal lines 135 are disconnected at the overlapping region 133 corresponding to the second metal lines 136 to form a notch 134;
the first metal line 135 is disconnected at a position corresponding to at least one overlapping area 133 to form a gap 134, correspondingly, the conductive layer 140 is disposed at the gap 134, and the conductive layer 140 connects the first signal lines 131 on two sides of the gap 134; the line width of the conductive layer 140 is greater than or equal to the line width of the first signal line 131, and the length of the conductive layer 140 crossing the overlapping region 133 is greater than or equal to the length of the overlapping region; the conductive layer 140 is a transparent conductive line, and is formed in the same process as the pixel electrode in the display panel 100.
The peripheral wires 130 in the wiring area in the non-display area 120 are designed to be wider in order to reduce the resistance of the wires, and therefore become wires with a large area, because the wires have a large area, more charges are easily accumulated, and particularly, in the overlapping area of the metal wires, electrostatic explosion is more easily caused at the overlapping position, so that the metal is short-circuited, and the function is abnormal; this application is at first corresponding to the overlap region 133 of the first metal wire 135 number line and the second metal wire 136 of different layers, the position disconnection that the first metal wire 135 that extends along first direction corresponds at least one overlap region 133 forms breach 134, breach 134 can reduce the area on the peripheral line 130 of the place of static, can prevent that large tracts of land periphery from walking line 130 and accumulating electric charge, use conducting layer 140 to switch on the first metal wire 135 of breach 134 both sides simultaneously, it is concatenated between the line, the static that accumulates before can be fast because conducting layer 140 switches on peripheral line 130 and disperses to whole big board, the risk that the charge accumulation leads to the static damage has been reduced, improve the product yield.
The line width of the conductive layer 140 is relatively wide, so that the resistance of the conductive layer 140 is reduced, the phenomenon of charge accumulation caused by line breakage is avoided, and the yield is reduced; the length of the conductive layer 140 crossing the overlapping region 133 is greater than or equal to the length of the overlapping region, the length of the conductive layer 140 is equal to the length of the opening gap 134, the longer the opening length is, the less the accumulated charges are, the smaller the probability of electrostatic breakdown is, and the static electricity is rapidly dispersed after the conductive layer is turned on; the transparent conductive electrode is made of the same material, so that the material cost is saved, and the manufacturing process is performed simultaneously with the pixel electrode in the display panel 100, so that the manufacturing time and the manufacturing process cost are reduced.
Specifically, as shown in fig. 6, the display panel 100 includes a substrate 150, a first metal layer 151, a first insulating layer 153, a second metal layer 152, a second insulating layer 154, and a transparent conductive layer, which are sequentially stacked; the first metal layer is formed on the substrate 150, and the first signal line 131 is formed on the first metal layer 151 and extends along an edge parallel to the display region 110; the second signal lines 132 are formed on the second metal layers 152, and are fed into the display region 110 perpendicular to the edge of the display region 110, the first metal layers 151 are respectively in one-to-one conduction with the corresponding second metal layers 152, and the first insulating layers 153 are formed on the first metal layers 151; the second insulating layer 154 is formed on the second metal layer 152; the thickness of the second insulating layer 154 is greater than the thickness of the first insulating layer 153; a first via 155 penetrating the first insulating layer 153 to connect one end of the disconnected gap 134 of the first metal layer 151; and a second via hole 156 penetrating the first insulating layer 153 to connect the other end of the first signal line 131; the conductive layer 140 is formed on the transparent conductive layer, and the transparent conductive layer conducts the first metal layer 151 through a first via 155 and a second via 156. The thickness of the first insulating layer 153 is c1, the thickness of the second insulating layer 154 is c2, and the thickness of the second insulating layer 154 is greater than that of the first insulating layer 153, so that the overall height is increased, the capacitance of the overlapping region of the first metal layer 151 and the second metal layer 152 is reduced, the loading rate is increased, the resistance value is reduced, the rate of taking away accumulated charges is increased under the condition that the area of the first metal layer 151 is reduced, and electrostatic breakdown is prevented.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-emitting diode) display panel, and the above solution can be applied thereto.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A peripheral wiring structure of a display panel is formed in a non-display area of the display panel, and is characterized in that:
the peripheral routing structure includes:
a plurality of first signal lines, a plurality of second signal lines,
a plurality of second signal lines, wherein the plurality of first signal lines are perpendicular to the plurality of second signal lines; the plurality of second signal lines and the plurality of first signal lines are formed on different layers and are insulated from each other, and the plurality of first signal lines are respectively in one-to-one corresponding conduction with the plurality of corresponding second signal lines; the first signal line and the second signal line are overlapped to form an overlapping region, an
A conductive layer;
the position of the first signal line corresponding to at least one overlapping area is disconnected to form a notch, correspondingly, the conductive layer is arranged at the notch, and the conductive layer is conducted with the first signal lines on two sides of the notch.
2. The peripheral trace structure of a display panel according to claim 1, wherein the first signal lines are parallel to edges of a display area of the display panel, and the plurality of second signal lines are fed into the display area along a direction perpendicular to the first signal lines;
correspondingly, the conductive layer crosses the overlapping area along the extending direction of the first signal line, and the conductive layer conducts the first signal lines on two sides of the notch.
3. The peripheral trace structure of a display panel according to claim 1, wherein the second signal lines are parallel to the edges of the display area, and the plurality of first signal lines are fed into the display area along a direction perpendicular to the second signal lines;
correspondingly, the conductive layer crosses the overlapping area along the direction of the first signal line, and the conductive layer conducts the first signal lines on two sides of the notch.
4. The peripheral trace structure of claim 1, wherein the second signal lines are disconnected corresponding to the overlapping regions, the peripheral trace further comprising: and the fourth signal line and the first signal line are arranged on the same layer, the conductive layer crosses the overlapping area, the conductive layer conducts the first signal lines on two sides of the notch, and the fourth signal line conducts the second signal line.
5. The peripheral routing structure of a display panel according to claim 1, wherein the display panel includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third conductive layer, which are sequentially stacked; the first signal line is formed on the first metal layer, the second signal line is formed on the second metal layer, and the conductive layer is formed on the third conductive layer.
6. The peripheral routing structure of a display panel according to claim 1, wherein the display panel includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third conductive layer, which are sequentially stacked; the first signal line is formed on the first metal layer, the second signal line is formed on the second metal layer, and the conductive layer is formed on the third conductive layer.
7. The peripheral trace structure of a display panel according to claim 2 or 3, wherein the line width of the conductive layer is greater than or equal to the line width of the first signal line.
8. The peripheral routing structure of a display panel according to claim 1, wherein the display panel includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a transparent conductive layer, which are sequentially stacked;
the first signal line is formed on the first metal layer and extends along the edge parallel to the display area;
the second signal lines are formed on the second metal layers and are fed into the display area perpendicular to the edge of the display area, the first metal layers are respectively communicated with the corresponding second metal layers one by one,
the first insulating layer is formed on the first metal layer; the second insulating layer is formed on the second metal layer; the thickness of the second insulating layer is greater than that of the first insulating layer;
a first via hole penetrating through the first insulating layer and connected to one end of the broken gap of the first metal layer; and
the second via hole penetrates through the first insulating layer and is connected with the disconnected other end of the first signal line;
the conductive layer is formed on the transparent conductive layer, and the transparent conductive layer conducts the first metal layer through a first via hole and a second via hole.
9. A display panel divided into a display area and a non-display area, wherein the non-display area includes the peripheral trace structure according to any one of claims 1 to 8.
10. A display device comprising the display panel according to claim 9, a driving circuit for driving the display panel, and a flip-chip film for connecting the driving circuit and the display panel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920876960.2U CN210224021U (en) | 2019-06-11 | 2019-06-11 | Peripheral wiring structure of display panel, display panel and display device |
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| CN201920876960.2U CN210224021U (en) | 2019-06-11 | 2019-06-11 | Peripheral wiring structure of display panel, display panel and display device |
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| CN113380166A (en) * | 2021-06-15 | 2021-09-10 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN115050754A (en) * | 2022-06-08 | 2022-09-13 | 湖北长江新型显示产业创新中心有限公司 | Display panel, preparation method of display panel and display device |
| CN115428060A (en) * | 2021-02-22 | 2022-12-02 | 京东方科技集团股份有限公司 | Display substrate and display device |
| WO2023029705A1 (en) * | 2021-08-31 | 2023-03-09 | 惠科股份有限公司 | Signal wiring structure and array substrate |
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| CN113380166A (en) * | 2021-06-15 | 2021-09-10 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| WO2023029705A1 (en) * | 2021-08-31 | 2023-03-09 | 惠科股份有限公司 | Signal wiring structure and array substrate |
| CN115050754A (en) * | 2022-06-08 | 2022-09-13 | 湖北长江新型显示产业创新中心有限公司 | Display panel, preparation method of display panel and display device |
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