CN210199661U - Edge computing array server based on ARM architecture - Google Patents
Edge computing array server based on ARM architecture Download PDFInfo
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- CN210199661U CN210199661U CN201921578321.4U CN201921578321U CN210199661U CN 210199661 U CN210199661 U CN 210199661U CN 201921578321 U CN201921578321 U CN 201921578321U CN 210199661 U CN210199661 U CN 210199661U
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Abstract
The utility model discloses an edge based on ARM framework calculates array server, this backplate based on ARM framework calculates array server's edge includes first circuit board, first power chip, main chip, first PHY chip, at least one giga net interface, a plurality of first giga net interface and a plurality of second giga net interface, the output of main chip of first PHY chip electric connection and first giga net interface, the input of giga net interface is used for being connected with outside internet communication; the bottom plate includes second circuit board, second power chip, nuclear core plate and second PHY chip, and the second PHY chip can dismantle electric connection second giga net interface or first giga net interface. The utility model discloses with the bottom plate integrated to being connected with the backplate of internet, can provide fast-speed network environment and shared resource, still reduce cost, the ultra-low power dissipation is fit for deploying at network edge environment, can better support the calculation task that comes from each type intelligent terminal with the ARM framework.
Description
Technical Field
The utility model relates to a server technical field, in particular to edge calculation array server based on ARM framework.
Background
The blade server in the market at present refers to a server unit which can be inserted into a rack-type chassis with standard height and is provided with a plurality of card types. The main structure of the computer is a large main body case, a plurality of blades can be inserted into the main body case, and each blade is actually a system mainboard. They can boot their own operating system through an "on-board" hard disk, similar to a separate server, in which mode each motherboard runs its own system, serving a designated different user group, without any association between them. However, an administrator may group these motherboards into a server cluster. In the cluster mode, all motherboards can be connected to provide a high-speed network environment, and simultaneously share resources to serve the same user group. Since each "blade" is hot-swappable, the system can be replaced. However, the existing blade server has the defects of high power consumption, expensive cabinets and blades and high cost for enterprise users with one or two blade centers.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an edge calculation array server based on ARM framework aims at providing fast-speed network environment and shared resource, simple structure, low power dissipation, and is with low costs with the integrated backplate that is connected with the internet of bottom plate.
In order to achieve the above object, the present invention provides an edge computing array server based on ARM architecture, which includes a back plate and a plurality of bottom plates detachably and electrically connected to the back plate,
the backboard comprises a first circuit board, wherein a first power supply chip, a main chip, a first PHY chip, at least one gigabit network interface, a plurality of first gigabit network interfaces and a plurality of second gigabit network interfaces are arranged on the first circuit board, the first power supply chip is electrically connected with the main chip, the first PHY chip and the gigabit network interfaces, the first PHY chip is electrically connected with the main chip and the output ends of the first gigabit network interfaces, the output ends of the gigabit network interfaces and the output ends of the second gigabit network interfaces are electrically connected with the main chip, and the input ends of the gigabit network interfaces are used for being in communication connection with the external Internet;
the bottom plate includes the second circuit board, be equipped with second power chip, nuclear core plate and second PHY chip on the second circuit board, second PHY chip electric connection second power chip and nuclear core plate, electric connection can be dismantled to second PHY chip the input of second giga net interface or the first giga net interface of backplate.
Preferably, the core board comprises an ARM processor, a DDR memory and a FLASH chip, the DDR memory and the FLASH chip are electrically connected to the ARM processor, and the second power supply chip and the second PHY chip are electrically connected to the ARM processor.
Preferably, the first power supply chip includes a first backplane power supply chip, a second backplane power supply chip, and a third backplane power supply chip, the first backplane power supply chip, the second backplane power supply chip, and the third backplane power supply chip are all electrically connected to an external access power supply, the first backplane power supply chip is electrically connected to the first PHY chip and the main chip, the second backplane power supply chip is electrically connected to the first PHY chip, the main chip, and the gigabit network interface, and the third backplane power supply chip is electrically connected to the main chip.
Preferably, the second power chip comprises a first bottom plate power chip, a second bottom plate power chip and a third bottom plate power chip, the first bottom plate power chip, the second bottom plate power chip and the third bottom plate power chip are all electrically connected with an external access power supply, the first bottom plate power chip is electrically connected with the second PHY chip and the ARM processor, the second bottom plate power chip is electrically connected with the ARM processor, and the third bottom plate power chip is electrically connected with the ARM processor.
Preferably, the second circuit board is provided with a USB connector, the USB connector is electrically connected to the ARM processor, and the third backplane power supply chip is electrically connected to the USB connector.
Preferably, the first gigabit network interface is a serial 16 to 24 network port; the second gigabit network interface is a serial 1 to 15 network port.
Preferably, the edge computing array server based on the ARM architecture further includes a serial interface, and the serial interface is electrically connected with the main chip.
Preferably, the model of the main chip is BCM56150, the model of the first PHY chip is B50282, the model of the first backplane power chip is RT8120, the model of the second backplane power chip is RT8293A, and the model of the third backplane power chip is RT 8120;
the model of the first backplane power supply chip is RT8272GS, the model of the second backplane power supply chip is ZTP7106T, the model of the third backplane power supply chip is RT8272GS, and the model of the second PHY chip is RTL 8211.
Preferably, the edge computing array server based on the ARM architecture further comprises a housing, an opening is formed in one end of the housing, the back plate is arranged on the inner wall of the housing, the back plate is located at one end, away from the opening, of the housing, the first gigabit network interface and the second gigabit network interface are distributed on the first circuit board in a rectangular array manner, the first gigabit network interface and the second gigabit network interface of the back plate face one end of the opening, the second circuit board is of a rectangular structure, guard plates are arranged on the first edge, the second edge and the third edge of the second circuit board, the guard plate on the first edge of the second circuit board is arranged opposite to the guard plate on the third edge of the second circuit board, the three guard plates and the second circuit board enclose an accommodating area, and the second power chip, the ARM processor and the second PHY chip are located in the accommodating area, the interface of the second PHY chip is located at the fourth edge of the second circuit board, when the bottom plate is connected to the backboard, the end, provided with the interface of the second PHY chip, of the bottom plate penetrates through the opening to be arranged in the accommodating area and is connected with one first gigabit network interface or one second gigabit network interface, and the guard plate part at the second edge of the second circuit board covers the opening.
Preferably, the opening is of a rectangular structure, the guard plate at the second edge of the second circuit board is of a rectangular structure, and the ratio of the area of the guard plate at the second edge of the second circuit board to the area of the opening is 1: 24.
the utility model discloses technical scheme passes through the backplate and can dismantle a plurality of bottom plates of electric connection in backplate, the backplate includes first circuit board, be equipped with first power chip, main chip, first PHY chip, at least one giga net interface, a plurality of first giga net interface and a plurality of second giga net interface on the first circuit board, first power chip electric connection main chip, first PHY chip and giga net interface, the output of first PHY chip electric connection main chip and first giga net interface, the output of giga net interface and the output electric connection main chip of second giga net interface, the input of giga net interface is used for being connected with outside internet communication; the bottom plate includes the second circuit board, be equipped with second power chip, nuclear core plate and second PHY chip on the second circuit board, second PHY chip electric connection second power chip and nuclear core plate, electric connection can be dismantled to second PHY chip the second giga net interface of backplate or the input of first giga net interface to this integrates a plurality of bottom plates to the backplate that is connected with the internet, information exchange between the bottom plate and all can realize through internet transmission with outside information exchange, can provide fast-speed network environment and shared resource, be fit for deploying at network edge environment, the calculation task of multiple intelligent terminal with the ARM framework of support that can be better, and simpler for current blade server structure, the low power dissipation, the cost is also lower.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an embodiment of an edge computing array server based on an ARM architecture according to the present invention;
fig. 2 is a schematic diagram of an internal circuit structure of an embodiment of an edge computing array server based on an ARM architecture according to the present invention;
fig. 3 is a schematic circuit structure diagram of a core board of the edge computing array server based on the ARM architecture in fig. 2.
The reference numbers illustrate:
the objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In the present application, unless expressly stated or limited otherwise, the terms "connected" and "fixed" are to be construed broadly, e.g., "fixed" may be fixedly connected or detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In addition, descriptions in the present application as to "first", "second", and the like are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides an edge calculation array server based on ARM framework.
Referring to fig. 1 to 3, in an embodiment of the present invention, the edge computing array server based on ARM architecture includes a backplane 10 and a plurality of backplanes 20 detachably and electrically connected to the backplane 10,
the backplane 10 includes a first circuit board 11, the first circuit board 11 is provided with a first power chip 12, a main chip 13, a first PHY chip 14, at least one gigabit network interface 15, a plurality of first gigabit network interfaces 16 and a plurality of second gigabit network interfaces 17, the first power chip 12 is electrically connected to the main chip 13, the first PHY chip 14 and the gigabit network interface 15, the first PHY chip 14 is electrically connected to the output ends of the main chip 13 and the first gigabit network interface 16, the output end of the gigabit network interface 15 and the output end of the second gigabit network interface 17 are electrically connected to the main chip 13, and the input end of the gigabit network interface 15 is used for communication connection with the external internet;
the bottom plate 20 includes a second circuit board 21, the second circuit board 21 is provided with a second power chip 22, a core board 23 and a second PHY chip 24, the second PHY chip 24 is electrically connected to the second power chip 22 and the core board 23, and the second PHY chip 24 is detachably electrically connected to the second gigabit network interface 17 of the backplane 10 or the input end of the first gigabit network interface 16.
The input end of the gigabit network interface 15 is used for communication connection with the external internet, specifically, the input end of the gigabit network interface 15 is connected with a computer mainboard, and the computer is accessed to the internet for communication. The model of the main chip 13 is BCM56150, the model of the first PHY chip 14 is B50282, and the model of the second PHY chip 24 is RTL 8211. The core board 23 is an electronic motherboard that packages core functions of the MINI PC, and referring to fig. 3, the core board 23 includes an ARM processor 231, a DDR memory 232, and a FLASH chip 233, the DDR memory 232 and the FLASH chip 233 are electrically connected to the ARM processor 231, and the second power supply chip 22 and the second PHY chip 24 are electrically connected to the ARM processor 231. The ARM processor 231, the DDR memory 232 and the FLASH chip 233 may all be designed conventionally, and when the backplane 20 is powered off, the stored data is not lost, and the function is mainly to store software data. The DDR memory 232 is a random access memory, and when the backplane 10 is powered off, the backplane 10 and the backplane 20 are powered off, and the program stored therein disappears, and it is responsible for transferring data between the ARM processor 231 and the FLASH chip 233 to perform functions of forwarding and buffering. The structure of the edge computing array server based on the ARM architecture is simpler and the relative cost is lower through the core board 23. The first gigabit network interface 16 is a serial 16 to 24 network port; the second gigabit network interface 17 is a serial 1 to 15 network port, so as to meet different use requirements, and since the second gigabit network interface 17 does not need to be connected to the first PHY chip 14, elements can be saved, the structure is simpler, and cost reduction is facilitated.
Therefore, the plurality of bottom plates 20 are integrated on the back plate 10 connected with the Internet, information exchange between the bottom plates 20 and information exchange with the outside can be realized through Internet transmission, a high-speed network environment can be provided, resources can be shared, and compared with the existing blade server, the blade server is simpler in structure, low in power consumption and lower in cost.
Referring to fig. 2, preferably, the first power chip 12 includes a first backplane power chip 121, a second backplane power chip 122, and a third backplane power chip 123, the first backplane power chip 121, the second backplane power chip 122, and the third backplane power chip 123 are all electrically connected to an external access power source, the first backplane power chip 121 is electrically connected to the first PHY chip 14 and the main chip 13, the second backplane power chip 122 is electrically connected to the first PHY chip 14, the main chip 13, and the gigabit network interface 15, and the third backplane power chip 123 is electrically connected to the main chip 13.
Specifically, the type of the first backplane power chip 121 may be RT8120, the type of the second backplane power chip 122 may be RT8293A, and the type of the third backplane power chip 123 may be RT8120, the first backplane power chip 121, the second backplane power chip 122, and the third backplane power chip 123 are all electrically connected to an external access power supply 12V, the first backplane power chip 121 outputs 1V to the first PHY chip 14 and the main chip 13, the second backplane power chip 122 outputs 3.3V to the first PHY chip 14, the main chip 13, and the gigabit network interface 15, and the third backplane power chip 123 outputs 1.5V to the main chip 13, so that the main chip 13, the first PHY chip 14, and the gigabit network interface 15 on the backplane 10 are more stable in operation.
Preferably, the second power chip 22 includes a first backplane power chip 221, a second backplane power chip 222, and a third backplane power chip 223, the first backplane power chip 221, the second backplane power chip 222, and the third backplane power chip 223 are all electrically connected to an external access power source, the first backplane power chip 221 is electrically connected to the second PHY chip 24 and the ARM processor 231, the second backplane power chip 222 is electrically connected to the ARM processor 231, and the third backplane power chip 223 is electrically connected to the ARM processor 231.
Specifically, the model of the first backplane power chip 221 may be RT8272GS, the model of the second backplane power chip 222 may be ZTP7106T, and the model of the third backplane power chip 223 may be RT8272GS, the first backplane power chip 221, the second backplane power chip 222, and the third backplane power chip 223 are all electrically connected to an external access power supply 12V voltage, the first backplane power chip 221 outputs 3.3V to the second PHY chip 24 and the ARM processor 231, the second backplane power chip 222 outputs 1.8V to the ARM processor 231, the third backplane power chip 223 outputs 5V to the ARM processor 231, and the ARM processor 231 calculates a cluster, which can better support calculation tasks from various types of intelligent terminals using the ARM processor 231 as a central processor, so that the second PHY chip 24 and the ARM processor 231 on the backplane 20 are more stable when operating.
Preferably, the second circuit board 21 is provided with a USB connector 25, the USB connector 25 is electrically connected to the ARM processor 231, and the third backplane power chip 223 is electrically connected to the USB connector 25. An external storage device, such as a USB disk or an electronic device with a storage function, can be connected to the USB connector 25, so as to facilitate data exchange between the external device and the edge computing array server based on the ARM architecture.
Preferably, the edge computing array server based on the ARM architecture further includes a serial interface 30, and the serial interface 30 is electrically connected to the main chip 13. The serial interface 30 is an expansion interface adopting a serial communication mode, for example, the serial interface 30 can be RS-232-C, RS-422 or RS485, so as to meet more use requirements of users.
Referring to fig. 3, preferably, the edge computing array server based on the ARM architecture further includes a housing 40, an opening 41 is disposed at one end of the housing 40, the backplane 10 is disposed on an inner wall of the housing 40, the backplane 10 is located at an end of the housing 40 away from the opening, the first gigabit network interface 16 and the second gigabit network interface 17 are distributed on the first circuit board 11 in a rectangular array, the first gigabit network interface 16 and the second gigabit network interface 17 of the backplane 10 face one end of the opening 41, the second circuit board 21 is in a rectangular structure, the first edge, the second edge, and the third edge of the second circuit board 21 are respectively provided with a guard plate 26, the guard plate 26 at the first edge of the second circuit board 21 is opposite to the guard plate 26 at the third edge of the second circuit board 21, and the three guard plates 26 and the second circuit board 21 enclose an accommodation area 27, the second power chip 22, the ARM processor 231, and the second PHY chip 24 are all located in the receiving area 27, an interface connected to the second PHY chip 24 is located at the fourth edge of the second circuit board 21, when the bottom board 20 is connected to the backplane 10, the end of the bottom board 20 where the interface of the second PHY chip 24 is located passes through the opening 41 and is placed in the receiving area 27, and is connected to one first gigabit network interface 16 or one second gigabit network interface 17, and the guard plate 26 at the second edge of the second circuit board 21 partially covers the opening 41.
The housing 40 may be made of metal, the interface connected to the second PHY chip 24 is adapted to the input end of the gigabit network interface 16 or the second gigabit network interface 17, two ends of the guard plate 26 at the second edge of the second circuit board 21 are connected to the corresponding first edge guard plate and the third edge guard plate, and the three guard plates 26 may prevent the interference of the electronic components connected to the two adjacent bottom plates 20 on the back plate 10, so that the structure of the electronic component is more reasonable, and the storage and arrangement of the wires between the electronic components on the second circuit board 21 are facilitated, so that the use of the electronic component is more convenient. Preferably, the opening 41 has a rectangular structure, the protection plate 26 at the second edge of the second circuit board 21 has a rectangular structure, and the ratio of the area of the protection plate 26 at the second edge of the second circuit board 21 to the area of the opening 41 is 1: 24. therefore, after the 24 bottom boards 20 are connected to the corresponding first gigabit network interface 16 or the second gigabit network interface 17, the protection board 26 on the second edge of the second circuit board 21 can just completely cover the opening 41, so that the structure is simpler, dust can be prevented, and the communication is more stable. Furthermore, the protection plate 26 at the second edge of the second circuit board 21 may be provided with a handle (not shown) for facilitating the use thereof.
The above only be the preferred embodiment of the utility model discloses a not consequently restriction the utility model discloses a patent range, all are in the utility model discloses a conceive, utilize the equivalent structure transform of what the content was done in the description and the attached drawing, or direct/indirect application all is included in other relevant technical field the utility model discloses a patent protection within range.
Claims (10)
1. An edge computing array server based on ARM architecture, comprising a backboard and a plurality of bottom boards which are detachably and electrically connected with the backboard, is characterized in that,
the backboard comprises a first circuit board, wherein a first power supply chip, a main chip, a first PHY chip, at least one gigabit network interface, a plurality of first gigabit network interfaces and a plurality of second gigabit network interfaces are arranged on the first circuit board, the first power supply chip is electrically connected with the main chip, the first PHY chip and the gigabit network interfaces, the first PHY chip is electrically connected with the main chip and the output ends of the first gigabit network interfaces, the output ends of the gigabit network interfaces and the output ends of the second gigabit network interfaces are electrically connected with the main chip, and the input ends of the gigabit network interfaces are used for being in communication connection with the external Internet;
the bottom plate includes the second circuit board, be equipped with second power chip, nuclear core plate and second PHY chip on the second circuit board, second PHY chip electric connection second power chip and nuclear core plate, electric connection can be dismantled to second PHY chip the input of second giga net interface or the first giga net interface of backplate.
2. The ARM architecture-based edge computing array server of claim 1, wherein the core board comprises an ARM processor, a DDR memory and a FLASH chip, the DDR memory and the FLASH chip are electrically connected to the ARM processor, and the second power chip and the second PHY chip are electrically connected to the ARM processor.
3. The ARM-based edge computing array server of claim 2, wherein the first power chip comprises a first backplane power chip, a second backplane power chip, and a third backplane power chip, the first backplane power chip, the second backplane power chip, and the third backplane power chip are electrically connected to an external access power source, the first backplane power chip is electrically connected to the first PHY chip and the main chip, the second backplane power chip is electrically connected to the first PHY chip, the main chip, and the gigabit network interface, and the third backplane power chip is electrically connected to the main chip.
4. The ARM architecture based edge computing array server of claim 3, wherein the second power chips comprise a first backplane power chip, a second backplane power chip, and a third backplane power chip, the first backplane power chip, the second backplane power chip, and the third backplane power chip are electrically connected to an external access power source, the first backplane power chip is electrically connected to the second PHY chip and the ARM processor, the second backplane power chip is electrically connected to the ARM processor, and the third backplane power chip is electrically connected to the ARM processor.
5. The ARM architecture based edge computing array server of claim 4, wherein the second circuit board has a USB connector electrically connected to the ARM processor, and the third backplane power chip is electrically connected to the USB connector.
6. The ARM architecture-based edge computing array server of claim 1, wherein the first gigabit interface is a serial 16 to 24 network port; the second gigabit network interface is a serial 1 to 15 network port.
7. The ARM architecture based edge computing array server of claim 1, further comprising a serial interface, the serial interface electrically connected to the main chip.
8. The ARM architecture based edge computing array server of claim 4, wherein the model of the master chip is BCM56150, the model of the first PHY chip is B50282, the model of the first backplane power chip is RT8120, the model of the second backplane power chip is RT8293A, the model of the third backplane power chip is RT 8120;
the model of the first backplane power supply chip is RT8272GS, the model of the second backplane power supply chip is ZTP7106T, the model of the third backplane power supply chip is RT8272GS, and the model of the second PHY chip is RTL 8211.
9. The ARM architecture based edge computing array server of any one of claims 1 to 8, further comprising a housing, wherein an opening is formed at one end of the housing, the back plate is disposed on an inner wall of the housing, the back plate is disposed at an end of the housing away from the opening, the first gigabit network interface and the second gigabit network interface are distributed on the first circuit board in a rectangular array, the first gigabit network interface and the second gigabit network interface of the back plate face the end of the opening, the second circuit board is in a rectangular structure, the first edge, the second edge and the third edge of the second circuit board are respectively provided with a guard plate, the guard plate at the first edge of the second circuit board is opposite to the guard plate at the third edge of the second circuit board, and the three guard plates and the second circuit board enclose an accommodation area, the second power chip, the ARM processor and the second PHY chip are located in the containing area, an interface connected with the second PHY chip is located on the fourth edge of the second circuit board, when the bottom plate is connected to the backboard, one end, provided with the second PHY chip, of the bottom plate penetrates through the opening to be arranged in the containing area and connected with one first gigabit network interface or one second gigabit network interface, and a guard plate portion on the second edge of the second circuit board covers the opening.
10. The ARM architecture-based edge computing array server of claim 9, wherein the opening is rectangular in configuration, the shield at the second edge of the second circuit board is rectangular in configuration, and a ratio of an area of the shield at the second edge of the second circuit board to an area of the opening is 1: 24.
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| CN201921578321.4U CN210199661U (en) | 2019-09-20 | 2019-09-20 | Edge computing array server based on ARM architecture |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110456889A (en) * | 2019-09-20 | 2019-11-15 | 广州市智谱科技有限公司 | Edge calculations array server based on ARM framework |
| CN113473071A (en) * | 2020-03-31 | 2021-10-01 | 武汉雄楚高晶科技有限公司 | Network access type intelligent integrated array terminal |
-
2019
- 2019-09-20 CN CN201921578321.4U patent/CN210199661U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110456889A (en) * | 2019-09-20 | 2019-11-15 | 广州市智谱科技有限公司 | Edge calculations array server based on ARM framework |
| CN113473071A (en) * | 2020-03-31 | 2021-10-01 | 武汉雄楚高晶科技有限公司 | Network access type intelligent integrated array terminal |
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