CN210182397U - Large-size laminated-tile battery structure - Google Patents
Large-size laminated-tile battery structure Download PDFInfo
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- CN210182397U CN210182397U CN201921325107.8U CN201921325107U CN210182397U CN 210182397 U CN210182397 U CN 210182397U CN 201921325107 U CN201921325107 U CN 201921325107U CN 210182397 U CN210182397 U CN 210182397U
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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Abstract
The utility model provides a large-size laminated cell structure, which comprises a front surface and a back surface field, wherein the front surface comprises a plurality of first main grids and second main grids which are arranged in parallel, the first main grids are positioned at the inner side of the front surface, and the second main grids are respectively positioned at the upper edge and the lower edge of the front surface; the back field comprises a plurality of back electrodes arranged in parallel, and the back electrodes are arranged in parallel with the first main grid in a staggered manner; the front surface of the first main grid is also provided with at least one first channel and at least one second channel, and the first channel is vertical to the first main grid and penetrates through the first main grid and the second main grid; the second channel is arranged in parallel with the first main grid and is communicated with the first channel in a crossing way; the back field is also provided with at least one third channel and a fourth channel, the third channel and the first channel are arranged in a back-to-back manner, and the fourth channel and the first main grid are arranged in a back-to-back manner; the back electrode and the second channel are arranged back to back. The utility model provides a crooked and latent problem of splitting of battery, still solved the problem that collides with and the piece when later stage equipment, guarantee the product quality, improve the yield of fold tile battery, reduction in production cost.
Description
Technical Field
The utility model belongs to the technical field of solar cell stack tile subassembly, especially, relate to a jumbo size stack tile battery structure.
Background
The existing laminated cell component is assembled by small-sized silicon wafers, and the side length of each small-sized silicon wafer is 156 mm. However, as the photovoltaic market develops, the requirements for solar modules are higher and higher, and the high power and high conversion rate of the tiled cell module tend to be achieved. The existing small-size silicon wafer has small effective area and low battery conversion rate, and can not meet the technical requirements of the existing solar battery piece on assembly. The effective area of a single large-size silicon wafer is large, the effective power generation area of the solar cell module can be increased, and the trend of current research and development is shown. The screen printing plate for the existing small-size silicon wafer is of an integrated structure, when the large-size silicon wafer is printed by the screen printing plate of the integrated structure, the completeness of different degrees can be realized, the problems of collision and fragments can be caused during later assembly, the product quality is seriously influenced, and the production progress is restricted. The design of a screen printing plate suitable for large-size silicon wafers is a technical problem to be solved urgently.
Disclosure of Invention
The to-be-solved problem of the utility model is to provide a jumbo size stack tile battery structure, be applicable to especially that the silicon chip size is greater than 156 mm's stack tile battery, not only can solve the crooked technical problem of battery that appears in the present silicon chip printing, but also solved when later stage equipment can appear colliding with and the technical problem of piece, guarantee the product quality, improve the yield of stack tile battery, reduction in production cost.
In order to solve the technical problem, the utility model discloses a technical scheme is:
a large-size laminated cell structure comprises a front surface and a back surface field, wherein the front surface comprises a plurality of first main grids and second main grids which are arranged in parallel, the first main grids are positioned on the inner side of the front surface, and the second main grids are respectively positioned on the upper edge and the lower edge of the front surface; the back field comprises a plurality of back electrodes arranged in parallel, and the back electrodes and the first main grid are arranged in parallel and in a staggered mode; the front surface is also provided with at least one first channel and a second channel, and the first channel is perpendicular to the first main grid and penetrates through the first main grid and the second main grid; the second channel is arranged in parallel with the first main grid and is communicated with the first channel in a cross mode; the back surface field is also provided with at least one third channel and a fourth channel, the third channel and the first channel are arranged in a back-to-back mode, and the fourth channel and the first main grid are arranged in a back-to-back mode; the back electrode and the second channel are arranged back to back.
Further, the first channel and the third channel have the same width, and the second channel and the fourth channel have the same width; and the first channel width is greater than the second channel width.
Furthermore, at least one side of the first main grid and the second main grid is provided with a plurality of arc sections with outward opening directions, and the arc sections are alternately arranged side by side; the second main grid and the first main grid are arranged at the same side of the arc section, the opening of the arc section has the same direction and the longitudinal position of the arc section is correspondingly arranged.
Furthermore, the arc sections are arranged on two sides of the first main grid, and the arc sections on two sides of the first main grid are arranged in a staggered mode.
Furthermore, the arc section is arranged on one side, close to the first main grid, of the second main grid.
Furthermore, the number of the first main gates and the number of the second main gates are two, and the width of the first main gate is larger than that of the second main gate.
Further, the back electrode structure is the same as the first main gate structure, and the number of the back electrodes is the same as that of the second channels.
Further, the number of the first channels is the same as that of the third channels.
Further, the number of the fourth channels is the same as that of the first main gates.
Furthermore, a plurality of fine grids which are uniformly arranged side by side are arranged between the first main grids or between the first main grids and the second main grids; the fine grid is respectively vertical to the first main grid and the second main grid.
Adopt the utility model discloses a stack tile battery structure, be applicable to especially that the silicon chip size is greater than 156 mm's stack tile battery, the monoblock battery length dimension has been reduced, the risk that the silicon chip easily appears battery bending deformation in the printing because of length dimension overlength has been reduced, reduce silicon chip stress concentration, reduce the latent production that splits, and then reduced colliding with or the piece volume of silicon chip when later stage equipment, the risk of repairing because of the latent subassembly that splits of silicon chip brings has also been reduced, guarantee the product quality, improve the yield of stack tile battery, and the production cost is reduced.
Drawings
Fig. 1 is a schematic structural view of the front surface of a stack of cells according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a left side of the first main grid according to an embodiment of the present invention;
fig. 3 is a schematic structural view of the left side of the second main grid at the upper edge according to an embodiment of the present invention;
fig. 4 is a schematic structural view of the left side of the second main grid at the lower edge according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a back surface field of a laminated cell according to an embodiment of the present invention.
In the figure:
10. front surface 11, first main grid 12 and second main grid
13. Fine grid 14, first channel 15, second channel
16. Arc segment 20, back field 21, back electrode
22. Third channel 23, fourth channel
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The utility model provides a jumbo size stack tile battery structure, as shown in fig. 1-5, including front 10 and back of the body field 20, front 10 includes a plurality of first main bars 11 and the second main bars 12 that set up in parallel, and first main bars 11 are located front 10 inboards, and second main bars 12 are located the top edge and the lower limb of front 10 respectively, specifically as shown in fig. 1. The back field 20 includes a plurality of back electrodes 21 disposed in parallel, the back electrodes 21 are disposed in parallel and staggered with the first main grid 11, and the structure of the back electrodes 21 is the same as that of the first main grid 11. In this embodiment, the number of the first main grid 11 and the second main grid 12 is two, the first main grid 11 is located on the upper half portion and the lower half portion of the front surface 10, and the width of the first main grid 11 is greater than the width of the second main grid 12 and is twice the width of the second main grid 12. Meanwhile, a plurality of uniform and vertical thin grids 13 are arranged between the first main grids 11 in the middle of the front face 10 or between the first main grids 11 and the second main grids 12 at the upper and lower end parts of the front face 10, the thin grids 13 are respectively perpendicular to the first main grids 11 and the second main grids 12, and preferably, the width of each thin grid is 40-50 um. The number of the back electrodes 21 is three, and the width of the back electrodes 21 is the same as that of the first main gates 11. During printing, a layer of silver paste is printed in the first main grid 11 and the second main grid 12 of the front surface 10, and is mainly used for collecting and conducting battery charges; printing a layer of aluminum paste in the back field 20 for collecting matrix charges and serving as a reflection field of reflected electrons to increase the conversion efficiency of the battery; and a layer of silver paste is required to be printed on the back electrode in the middle of the aluminum paste for collecting and conducting the charge of the battery. When the assembly is welded, welding rods or conductive adhesive are welded on the back electrode 21, and the aluminum paste back field 20 converges the current of each part of the solar cell to the back electrode 21 and then leads out the current through the welding rods.
Further, at least one side of the first main grid 11 and the second main grid 12 is provided with a plurality of arc sections 16 with openings facing outward, the arc sections 16 on each side are arranged side by side in an alternating manner, and the arc sections 16 are used for connecting silicon wafers stacked up and down together by welding at the positions of the arc sections 16 when the components are welded. Preferably, the arc segment 16 has a transverse width of 3-5mm and a longitudinal depth of 0.8-1 mm.
The long sides of the two sides of the first main grid 11 are both provided with arc sections 16, and the arc sections 16 of the two sides of the first main grid 11 are both uniformly staggered; one side of the second main grid 12 close to the first main grid 11 is provided with an arc section 16; and the openings of the circular arc sections 16 on the same side of the second main grid 12 and the first main grid 11 are in the same direction and are correspondingly arranged at the longitudinal positions, as shown in fig. 2-4. The purpose of this structural arrangement is to ensure that the welding points of the cells lying one above the other, i.e. the arc segments 16, are correspondingly positioned.
Further, the front surface 10 is further provided with at least one first channel 14 and one second channel 15, and the first channel 14 is perpendicular to the first main grid 11 and is arranged to penetrate through the first main grid 11 and the second main grid 12. The second channel 15 is disposed in parallel with the first main gate 11 and cross-communicates with the first channel 14. In the present embodiment, the number of the first passages 14 is one, and the number of the second passages 15 is three, and the first passages 14 and the second passages are uniformly arranged at the center line positions of the first main grid 11 and the second main grid 12 at the upper end portion, the center line position between the first main grids 11 at the middle portion, and the center line positions of the first main grid 11 and the second main grid 12 at the lower end portion, as shown in fig. 1. The width of the first channel 14 is greater than the width of the second channel 15, preferably the width of the first channel 14 is 2mm and the width of the second channel 15 is 1 mm. It can be seen that the front surface 10 is divided into six long silicon wafers by the first main gate 11 and the second channel 15, and after printing is finished, the front surface battery silicon wafer can be cut along the second channel 15, the first main gate 11 and the first channel 14, that is, the battery silicon wafer is cut into six long silicon wafers by the second channel 15 and the first main gate 11, and then cut into twelve short silicon wafers by the middle of the first channel 14. Meanwhile, the openings of the arc sections 16 on the same side face the same direction and are correspondingly arranged at the longitudinal positions, so that the twelve cut silicon chips have the same structure, one side of each silicon chip is of a linear structure, and the alignment side of each silicon chip is of a structure with the arc sections 16, thereby ensuring the consistency of the welding structure of the front sides of the vertically stacked batteries.
Meanwhile, a blank channel with a 'feng' structure can be formed by vertically and crosswise arranging the first channel 14 and the three second channels 15, the connecting support and the silicon wafer body are integrally formed, no channel penetrates through the middle of the first channel 14 and the second channels 15, and a stable connecting support can be formed on the structure of the front surface 10 of the silicon wafer, so that the silicon wafer is divided into twelve short silicon wafer structures, the deformation of the transverse and longitudinal structures of the short silicon wafers can be reduced, the deformation of the silicon wafer is further reduced, and the deformation of the silicon wafer during later-period silicon wafer overlaying welding is reduced. Meanwhile, the first channel 14 and the second channel 15 are matched to divide a whole silicon wafer into independent areas which are symmetrically arranged, so that stress concentration inside the silicon wafer can be dispersed, a stress release area can be formed on the blank channels of the first channel 14 and the second channel 15, stress on each blank channel can be relieved, internal stress of the silicon wafer can be reduced, generation of internal hidden cracks is reduced, fragments caused by collision between the silicon wafers are reduced during later assembly, the fragment quantity is greatly reduced, the risk of component repair caused by the hidden cracks of the silicon wafer is also reduced, product quality is guaranteed, the yield of the tiled battery is improved, and production cost is reduced.
Further, as shown in fig. 5, at least one third channel 21 and one fourth channel 22 are further disposed in the back field 20, the third channel 21 is disposed opposite to the first channel 15, the fourth channel 22 is disposed opposite to the first main gate 11, and the back electrode 21 is disposed opposite to the second channel 15. In the present embodiment, the number of the third channels 22 is the same as that of the first channels 14, i.e., one; the number of the third channels 22 is the same as that of the first main gates 11, namely two; the number of the back electrodes 21 is the same as that of the second channels 15, i.e., 3. Wherein, the width of the first channel 14 is the same as that of the third channel 22, and the width of the second channel 15 is the same as that of the fourth channel 23.
Three back electrodes 21 and two fourth channels 23 in the back field 20 transversely divide the back field 20 into six long strip structures, and then the silicon wafer with the six long strip structures is divided into twelve short silicon wafers through the third channels 22, and the structure is arranged opposite to the positions of the second channels 15, the first main gates 11 and the first channels 14 in the front surface 10. Correspondingly, the third channel 22 and the fourth channel 23 are mutually crossed to form two crossed structures which are mutually crossed, vertical and communicated up and down, and the two crossed structures which are communicated up and down form a stable blank crossed bracket channel, so that the deformation of the silicon wafer can be reduced, the stress concentration in the silicon wafer can be relieved, the hidden crack caused by the stress concentration is reduced, the fragment quantity of subsequent production is reduced, and the yield of the laminated assembly is improved.
In the embodiment, due to the block design of the back surface field, the bending degree of the sintered battery piece is reduced by 0.5-1mm, so that the fragment rate of the assembly caused by the bending problem of the battery piece is greatly reduced, and the fragment rate is reduced by about 3-5%.
Adopt the utility model discloses a stack tile battery structure, be applicable to especially that the silicon chip size is greater than 156 mm's stack tile battery, the monoblock battery length dimension has been reduced, the risk that the silicon chip easily appears battery bending deformation in the printing because of length dimension overlength has been reduced, reduce silicon chip stress concentration, reduce the latent production that splits, and then reduced colliding with or the piece volume of silicon chip when later stage equipment, the risk of repairing because of the latent subassembly that splits of silicon chip brings has also been reduced, guarantee the product quality, improve the yield of stack tile battery, and the production cost is reduced.
The embodiments of the present invention have been described in detail, and the description is only for the preferred embodiments of the present invention, and should not be construed as limiting the scope of the present invention. All the equivalent changes and improvements made according to the application scope of the present invention should still fall within the patent coverage of the present invention.
Claims (10)
1. A large-size laminated cell structure comprises a front surface and a back surface field, and is characterized in that the front surface comprises a plurality of first main grids and second main grids which are arranged in parallel, the first main grids are positioned on the inner side of the front surface, and the second main grids are respectively positioned on the upper edge and the lower edge of the front surface; the back field comprises a plurality of back electrodes arranged in parallel, and the back electrodes and the first main grid are arranged in parallel and in a staggered mode; the front surface is also provided with at least one first channel and a second channel, and the first channel is perpendicular to the first main grid and penetrates through the first main grid and the second main grid; the second channel is arranged in parallel with the first main grid and is communicated with the first channel in a cross mode; the back surface field is also provided with at least one third channel and a fourth channel, the third channel and the first channel are arranged in a back-to-back mode, and the fourth channel and the first main grid are arranged in a back-to-back mode; the back electrode and the second channel are arranged back to back.
2. A large-size shingled battery structure according to claim 1, wherein said first channel is the same width as said third channel, and said second channel is the same width as said fourth channel; and the first channel width is greater than the second channel width.
3. A large-size laminated cell structure according to claim 1 or 2, wherein at least one side of the first main grid and the second main grid is provided with a plurality of arc sections with openings facing outwards, and the arc sections are alternately arranged side by side; the second main grid and the first main grid are arranged at the same side of the arc section, the opening of the arc section has the same direction and the longitudinal position of the arc section is correspondingly arranged.
4. A large-size laminated cell structure according to claim 3, wherein the circular arc sections are disposed on both sides of the first main grid, and the circular arc sections on both sides of the first main grid are staggered with each other.
5. A large-size laminated cell structure according to claim 4, wherein the circular arc section is provided on one side of the second main grid close to the first main grid.
6. The large-size laminated cell structure according to claim 5, wherein the number of the first main grid and the second main grid is two, and the width of the first main grid is greater than that of the second main grid.
7. The large-scale laminated cell structure of claim 6, wherein the back electrode structure is the same as the first main gate structure, and the number of back electrodes is the same as the number of the second channels.
8. A large-size shingled battery structure according to claim 7, wherein said first channels are the same in number as said third channels.
9. A large-size shingled cell structure according to claim 8, wherein said fourth channels are equal in number to said first primary grid.
10. A large-size shingled cell structure according to any of claims 1-2 and 4-9, wherein a plurality of fine grids are uniformly arranged side by side between the first main grids or between the first main grid and the second main grid; the fine grid is respectively vertical to the first main grid and the second main grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921325107.8U CN210182397U (en) | 2019-08-15 | 2019-08-15 | Large-size laminated-tile battery structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921325107.8U CN210182397U (en) | 2019-08-15 | 2019-08-15 | Large-size laminated-tile battery structure |
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| CN210182397U true CN210182397U (en) | 2020-03-24 |
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| CN201921325107.8U Active CN210182397U (en) | 2019-08-15 | 2019-08-15 | Large-size laminated-tile battery structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110459624A (en) * | 2019-08-15 | 2019-11-15 | 东方环晟光伏（江苏）有限公司 | A kind of large scale imbrication battery structure |
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2019
- 2019-08-15 CN CN201921325107.8U patent/CN210182397U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110459624A (en) * | 2019-08-15 | 2019-11-15 | 东方环晟光伏（江苏）有限公司 | A kind of large scale imbrication battery structure |
| CN110459624B (en) * | 2019-08-15 | 2024-06-25 | 环晟光伏(江苏)有限公司 | Large-size laminated tile battery structure |
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