CN210136879U - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN210136879U CN210136879U CN201920904236.6U CN201920904236U CN210136879U CN 210136879 U CN210136879 U CN 210136879U CN 201920904236 U CN201920904236 U CN 201920904236U CN 210136879 U CN210136879 U CN 210136879U
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Abstract
The application discloses a semiconductor device, this semiconductor device includes: the semiconductor substrate, the second electrode end is drawn out on the second surface of the semiconductor substrate; an epitaxial layer on the first surface of the semiconductor substrate; the base region extends into the epitaxial layer from the surface of the epitaxial layer; the emitter region extends from the surface of the base region into the base region to lead out a first electrode end; the first doping region extends into the epitaxial layer from the surface of the epitaxial layer, and the first doping region and the base region are separated by the epitaxial layer; the second doping region is positioned in the epitaxial layer and is respectively contacted with the base region and the first doping region; and an electrically conductive path for electrically connecting the first doped region with the epitaxial layer, wherein the doping types of the semiconductor substrate, the epitaxial layer and the emitter region are a first doping type, the doping types of the base region, the first doped region and the second doped region are a second doping type, and the first doping type is opposite to the second doping type.
Description
Technical Field
The utility model relates to a semiconductor device makes the field, and more specifically relates to a semiconductor device.
Background
The constant current diode is a two-terminal constant current device made of silicon material. The constant current diode is connected into a circuit loop according to polarity, the forward constant current is conducted, the reverse constant current is cut off, the constant current is output, and the application is simple. Currently, a constant current diode is widely used in electronic circuits such as an ac/dc amplifier, a dc stabilized power supply, a waveform generator, and a protection circuit.
A current regulative diode in the prior art generally adopts a Junction Field Effect Transistor (JFET) structure, as shown in fig. 1, the current regulative diode includes: a P-type substrate 10, an N-type epitaxial layer 11, a P-type gate region 12a, an N-type source region 12b, an N-type drain region 12c, a P-type isolation region 12d, and a front electrode 13. The P-type gate region 12a and the N-type source region 12b are connected by a front electrode 13, the P-type isolation region 12d penetrates through the N-type epitaxial layer 11 and is connected with the P-type substrate 10, and the constant current diode forms a constant current characteristic by short-circuiting the P-type gate region 12a and the N-type source region 12 b.
However, in the prior art, the constant current of the constant current diode is sensitive to the thickness of the N-type epitaxial layer 11, the resistivity of the N-type epitaxial layer 11, and the junction depth of the P-type gate region 12a, so that the uniformity of the final constant current value is poor, and the yield is low.
In addition, the current capacity of the planar channel JFET structure mainly depends on the channel width, the channel width is limited by the front electrode pattern, the channel width in unit area is small, and therefore the current in unit area is small, and the cost is high.
SUMMERY OF THE UTILITY MODEL
In view of the above, the present invention provides a semiconductor device, thereby solving the above problems.
The utility model provides a semiconductor device, include: the semiconductor substrate, draw the second electrode terminal on the second surface of the said semiconductor substrate; an epitaxial layer on a first surface of the semiconductor substrate; the base region extends from the surface of the epitaxial layer into the epitaxial layer; the emitter region extends from the surface of the base region into the base region to lead out a first electrode end; a first doped region extending from the surface of the epitaxial layer into the epitaxial layer, the first doped region being separated from the base region by the epitaxial layer; the second doping region is positioned in the epitaxial layer and is respectively contacted with the base region and the first doping region; and an electrically conductive path for electrically connecting the first doped region and the epitaxial layer, wherein the doping types of the semiconductor substrate, the epitaxial layer and the emitter region are a first doping type, the doping types of the base region, the first doped region and the second doped region are a second doping type, and the first doping type is opposite to the second doping type.
Preferably, the electrically conductive path includes an electrical connection structure on the epitaxial layer and contacting the first doped region to electrically connect the first doped region with the epitaxial layer.
Preferably, the electrically conductive path further includes a third doped region extending from the surface of the epitaxial layer into the epitaxial layer, and the electrical connection structure is in contact with the third doped region, so that the first doped region is electrically connected to the epitaxial layer sequentially through the electrical connection structure and the third doped region, where the third doped region is of the first doping type.
Preferably, the device further comprises a fourth doping region extending into the base region from the surface of the base region, the fourth doping region is at least located on one side of the emitter region, the fourth doping region and the emitter region are separated by the base region, and the fourth doping region is of the second doping type.
Preferably, the device further comprises an oxide layer located on the epitaxial layer and covering the base region, at least part of the first doped region and at least part of the emitter region, wherein the oxide layer has at least one connection hole, and the first electrode end is in contact with the emitter region through the connection hole.
Preferably, the semiconductor device further comprises a scribing region, wherein the scribing region corresponds to the third doped region in position and exposes at least part of the third doped region.
Preferably, the epitaxial layer, the first doped region, the second doped region, the electrically conductive path and the base region form a constant current diode, the emitter region, the base region and the epitaxial layer form a triode, the constant current diode provides a constant base current to the triode, and the triode is used for amplifying the base current to generate an output current of the semiconductor device.
Preferably, the second doped region extends laterally along a first direction by a predetermined length to contact the first doped region and the base region, respectively, where the predetermined length corresponds to a breakdown voltage of the constant current diode.
Preferably, the plurality of second doped regions are distributed along a second direction, and the epitaxial layer surrounds each second doped region to separate each second doped region, wherein the first direction is perpendicular to the second direction, and the first direction and the second direction are both perpendicular to the longitudinal direction of the semiconductor device.
Preferably, the doping concentration of the second doping region is smaller than that of the first doping region.
Preferably, the doping dosage range of the second doping region comprises 1.0E 11-3.0E 12cm-2。
Preferably, the thickness range of the epitaxial layer comprises 3-50 um.
Preferably, the resistivity range of the epitaxial layer comprises 0.5-20 ohm.
Preferably, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.
Preferably, the junction depth of the third doped region is greater than the junction depth of the base region.
According to the utility model discloses a semiconductor device produces invariable electric current through epitaxial layer, first doping region, electric conduction route, second doping region, base region, enlargies invariable electric current through emitter region, base region and epitaxial layer again to semiconductor device output constant current's function has been realized.
According to the utility model discloses a semiconductor device, through the breakdown voltage of the thickness control constant current diode of control second doping area along the resistivity of first direction horizontal extension predetermined length, epitaxial layer and epitaxial layer, second doping area concentration, junction depth are controlled by even better high energy injection equipment's injection dosage, energy to constant current value homogeneity has been improved constant current diode.
According to the utility model discloses a semiconductor device forms the triode through epitaxial layer, base region, emitter region, enlargies the invariable base current that constant current diode provided, has solved the less problem of prior art constant current diode unit area electric current.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.
Fig. 1 shows a schematic diagram of a current regulative diode of the prior art.
Fig. 2 shows a top view of a semiconductor device according to an embodiment of the present invention.
Fig. 3 shows a cross-sectional view along line AA of fig. 2.
Fig. 4 shows an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 5 to 12 show cross-sectional views of a method of manufacturing a semiconductor device at various stages according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, a semiconductor device obtained after several steps can be described in one drawing.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.
Numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be presented in a variety of forms, some of which are described below.
Fig. 2 shows a top view of a semiconductor device according to an embodiment of the present invention, and fig. 3 shows a cross-sectional view of fig. 2 along line AA. For the sake of clarity, the electrodes, oxide layers and epitaxial layer portions are not shown in fig. 2.
As shown in fig. 2 and 3, the semiconductor device according to the embodiment of the present invention includes: the semiconductor substrate 101, the epitaxial layer 110, the base region 120, the emitter region 150, the first doped region 140, the second doped region 170, the oxide layer 102, the first electrode terminal 180, the electrical conduction path, and the scribe region 103, and further include a second electrode terminal (not shown) led out from the back surface of the semiconductor substrate 101.
The epitaxial layer 110 is located on the surface of the semiconductor substrate 101. The base region 120 extends from the surface of the epitaxial layer 110 into the epitaxial layer 110. The emitter region 150 extends from the surface of the base region 120 into the base region 120. In the embodiment of the present invention, the semiconductor substrate 101, the epitaxial layer 110 and the emitter region 150 are of a first doping type, and the base region 120 is of a second doping type.
The first doped region 140 extends from the surface of the epitaxial layer 110 into the epitaxial layer 110, and the second doped region 170 is located in the epitaxial layer 110 and covered by the epitaxial layer 110. In the embodiment of the present invention, the first doping region 140 and the second doping region 170 are both of the second doping type, wherein the doping concentration of the second doping region 170 is less than that of the first doping region 140. The first doped region 140 and the base region 120 are separated by the epitaxial layer 110, and the second doped region 170 is in contact with the base region 120 and the first doped region 140, respectively, so that the first doped region 140 is electrically connected with the base region 120. Wherein the second doped regions 170 extend laterally along a first direction (X-direction) and are in contact with the base region 120 and the first doped regions 140, respectively, and a plurality of second doped regions 170 are distributed in the epitaxial layer along a second direction (Y-direction), and each second doped region 170 is separated from each other because the epitaxial layer 110 surrounds each second doped region 170, wherein the first direction is perpendicular to the second direction and perpendicular to the longitudinal direction of the semiconductor device, respectively.
The electrically conductive path is used to electrically connect the first doped region 140 with the epitaxial layer 110, and includes an electrical connection structure 190 located on the epitaxial layer 110, the electrical connection structure 190 is in contact with the first doped region 140, and the material of the electrical connection structure 190 includes, but is not limited to, aluminum metal, so as to electrically connect the first doped region 140 with the epitaxial layer 110.
In some preferred embodiments, the electrical conduction path further comprises a third doped region 160 extending from the surface of the epitaxial layer 110 into the epitaxial layer 110, wherein the third doped region 160 is the same as the epitaxial layer 110 and is of the first doping type. The electrical connection structure 190 is in contact with the third doped region 160, so that the first doped region 140 is electrically connected to the epitaxial layer 110 sequentially through the electrical connection structure 190 and the third doped region 160. More preferably, the third doped region 160 contacts the first doped region 140 to reduce the area of the semiconductor device.
The oxide layer 102 is disposed on the epitaxial layer 110 and covers the base region 120, at least a portion of the first doped region 140, and at least a portion of the emitter region 150, wherein the oxide layer 102 has at least one connection hole, and the first electrode terminal 180 contacts the emitter region 150 through the connection hole, so that the emitter region 150 is connected to an external circuit. The second electrode terminal is led out from the back surface of the semiconductor substrate 101, and is electrically connected to the epitaxial layer 110 via the semiconductor substrate 101.
The scribe region 103 is located corresponding to the third doped region 160 and exposes at least a portion of the third doped region 160. The scribe region 103 serves as an indicator of a subsequent cutting position, and its corresponding third doped region 160 needs to be exposed without being covered by other materials such as silicon dioxide and metal, so as to improve the cutting efficiency.
In the present embodiment, the range of the resistivity of the semiconductor substrate 101 includes 0.001 to 0.1ohm. The thickness range of the epitaxial layer 110 comprises 3-50 um, the resistivity range of the epitaxial layer comprises 0.5-20 ohm.cm, and the doping metering range of the base region 120 comprises 1.0E 13-5.0E 14cm-2The doping dosage range of the first doping region 140 includes 1.0E 15-5.0E 16cm-2The doping dosage range of the second doping region 170 is 1.0E 11-3.0E 12cm-2The thickness range of oxide layer 102 includes
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other settings on the above parameters as needed.
The first doping type is opposite to the second doping type, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping. In the following description, the first doping type is selected from P-type doping, and the second doping type is selected from N-type doping. However, the embodiments of the present invention are not limited thereto, and other configurations may be performed by those skilled in the art as needed, for example, the first doping type is selected from N-type doping, and the second doping type is selected from P-type doping.
Fig. 4 shows an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention.
As shown in fig. 2 to 4, the emitter region 150, the base region 120, the epitaxial layer 110 and the third doped region 160 form a PNP triode Q1, wherein the epitaxial layer 110 serves as a collector region of the PNP triode Q1, the epitaxial layer 110, the third doped region 160, the first doped region 140, the second doped region 170 and the base region 120 form a JFET structure, and the third doped region 160 is shorted to the first doped region 140 by the electrical connection structure 190, so as to form a constant current diode VDH, wherein the second doped region 170 serves as a conduction channel, the emitter of the triode Q1 is connected to the first electrode terminal, the anode of the constant current diode VDH is connected to the base of the triode Q1, and the cathode of the constant current diode is connected to the collector of the triode Q1, in this embodiment, the constant current diode provides a constant base current I1 to the base of the triode Q1, and the triode Q1 amplifies the base current I1 to generate an emitter current I2, the emitter current I634 is equal to the base current I24, the base current I1 is equal to the base current I24, wherein the base current I36150 is amplified by the primary junction concentration of the emitter region 3610 and the emitter region 3610.
The base current I1 sequentially flows through the second doped region 170, the first doped region 140, the third doped region 160, and the epitaxial layer 110 via the base region 120 to the second electrode end on the back surface of the semiconductor substrate 101, and the emitter current I2 sequentially flows through the emitter region 150, the base region 120, and the epitaxial layer 110 via the first electrode end 180 to the second electrode end on the back surface of the semiconductor substrate 101.
In the present embodiment, the resistivity of the epitaxial layer 110, the thickness of the epitaxial layer 110, and the length of each second doping region 170 in the first direction are determined according to the breakdown voltage of the constant current diode VDH. Generally, the larger the thickness of the epitaxial layer 110, the larger the breakdown voltage, and the larger the length of the second doped region 170, the larger the breakdown voltage. The approximate mathematical relationship is that for smaller parameters, the breakdown voltage increases linearly with the parameter, and increases almost smoothly with increasing parameter.
In some preferred embodiments, the semiconductor device of the present invention further includes a fourth doped region 130, as shown in fig. 2 and 3. The fourth doped region 130 extends from the surface of the base region 120 into the base region 120 and is located at least on one side of the emitter region 150, and the fourth doped region 130 is separated from the emitter region 150 by the base region 120. By providing the fourth doped region 130, the start voltage of the constant current diode can be reduced to a small extent, so that the constant current diode enters a constant current operating state at a lower voltage, and more preferably, the fourth doped region 130 is in contact with the second doped region 170, wherein the fourth doped region 130 is generally used as one electrode of the transistor Q1 to reduce the series resistance on the base region 120.
Fig. 5 to 12 are sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention at various stages.
The method of the embodiment of the present invention starts with a semiconductor substrate 101, and forms an epitaxial layer 110 on the surface of the semiconductor substrate 101, as shown in fig. 5.
In this step, a P-type doped epitaxial layer 110 is formed on the surface of the P-type doped semiconductor substrate 101 by, for example, a Chemical Vapor Deposition (CVD) process or a Physical Vapor Deposition (PVD) process. Wherein the doping concentration of the epitaxial layer 110 is less than the doping concentration of the semiconductor substrate 101. In the present embodiment, the resistivity of the semiconductor substrate 101 ranges from 0.001 to 0.1 ohm-cm, the thickness of the epitaxial layer 110 ranges from 3 to 50um, the resistivity of the epitaxial layer 110 ranges from 0.5 to 20 ohm-cm, and the corresponding breakdown voltage ranges from 20 to 300V.
However, the embodiment of the present invention is not limited to this, and the resistivity and the thickness of the epitaxial layer 110 depend on the withstand voltage requirement (the breakdown voltage threshold of the present application) of the constant current diode, and the higher the withstand voltage requirement is, the larger the resistivity and the thickness are. Those skilled in the art may make other settings for the resistivity and thickness of epitaxial layer 110 as desired.
Further, an oxide layer 102 is formed on the surface of the epitaxial layer 110, as shown in fig. 6.
In this step, an oxide layer 102 is formed on the surface of the P-type doped epitaxial layer 110 by using a CVD process or a PVD process. In the present embodiment, the material of the oxide layer 102 includes silicon dioxide, and the thickness of the oxide layer 102 ranges from 3 μm to 50 μm.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art can make other settings on the material and thickness of the oxide layer 102 as needed.
Further, for example, a first photoresist mask is formed on the surface of the oxide layer 102, and then anisotropic etching is performed to pattern the oxide layer 102 to form an opening, so that a portion of the epitaxial layer 110 is exposed through the opening of the oxide layer, as shown in fig. 7.
In this step, the anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. The first photoresist mask is removed by dissolving or ashing in a solvent after etching.
Further, an opening through the oxide layer extends from the surface of the epitaxial layer 110 into the epitaxial layer 110 to form a base region 120, as shown in fig. 8.
In this step, N-type dopant ions, such as phosphorous ions, are implanted into the epitaxial layer 110 through the opening by an ion implantation process, wherein the implantation dose range includes 1.0E 13-5.0E 14cm-2The base region 120 is then formed via an annealing process.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other settings on the type of implanted ions and the implantation dosage as needed.
Further, a first doped region 140 is formed extending from the surface of the epitaxial layer 110 into the epitaxial layer 110, and a fourth doped region 130 is formed extending from the surface of the base region 120 into the base region 120, as shown in fig. 9.
In this step, for example, the oxide layer 102 having the opening is removed, and the oxide layer 102 is reformed on the surface of the epitaxial layer 110 by a CVD process or a PVD process. In the present embodiment, the material of the reformed oxide layer 102 includes silicon dioxide, and the thickness of the oxide layer 102 ranges from 0.01 μm to 0.1 μm. Then, for example, a second photoresist mask is formed on the surface of the oxide layer 102, and the opening region of the second photoresist mask corresponds to the positions of the first doped region 140 and the fourth doped region 130. Then, for example, an ion implantation process is used to implant N-type dopant ions, such as phosphorus ions, into the epitaxial layer 110 and the base region 120 through the opening of the photoresist mask and the newly formed oxide layer 102, respectively, wherein the implantation energy range includes 50KeV to 200KeV, preferably 120keV, and the implantation dosage range includes 1.0E15 to 5.0E16cm-2Thereby forming the first doped region 140 and the fourth doped region 130. The second photoresist mask is removed by dissolving or ashing in a solvent after the implantation process.
However, the present invention is not limited thereto, and those skilled in the art can make other settings for the material and thickness of the newly formed oxide layer 102, the type of implanted ions, the implantation energy, and the implantation dosage as needed.
Further, a third doped region 160 is formed in the epitaxial layer 110 and an emitter region 150 is formed in the base region 120, respectively, via the oxide layer 102, as shown in fig. 10.
In this step, a third photoresist mask is formed, for example, on the surface of the oxide layer 102, and the opening regions of the third photoresist mask correspond to the positions of the third doped regions 160 and the emitter regions 150. Then, for example, an ion implantation process is used to implant P-type dopant ions into the epitaxial layer 110 and the base region 120 through the opening of the third photoresist mask and the oxide layer 102, and then an annealing process is performed to form a third doped region 160 extending from the surface of the epitaxial layer 110 into the epitaxial layer 110 and an emitter region 150 extending from the surface of the base region 120 into the base region 120. The temperature range of the annealing process is preferably 950-1100 ℃, and the gas of the annealing process is preferably nitrogen. The third photoresist mask is removed by dissolving or ashing in a solvent after the implantation process.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings for the temperature range and the gas of the annealing process as needed.
Further, a second doped region 170 is formed in the epitaxial layer 110 via the oxide layer 102, as shown in fig. 11.
In this step, a patterned fourth photoresist mask is formed, for example, on the surface of the oxide layer 102. Then, for example, a high energy ion implantation process is used to implant N-type dopant ions into the epitaxial layer 110 through the patterned fourth photoresist mask and the oxide layer 102, thereby forming a plurality of second doped regions 170, wherein the dopant ions are, for example, phosphorus ions, the dopant concentration is less than that of the first doped region 140, the implantation energy range includes 500-3000 keV, preferably 800keV, and the implantation dosage range includes 1.0E 11-3.0E 12cm-2. Due to the high ion implantation energy, the second doped region 170 is formed below the surface of the epitaxial layer 110, surrounded by the epitaxial layer 110. The length of each second doping region 170 along the first direction corresponds to the breakdown voltage of the constant current diode VDH, for example, the implantation energy and the implantation dosage of the second doping region 170 are controlled to control the constant current diode VDHThe constant current is adjusted by adjusting the length of the second doped region 170 along the first direction and the resistivity of the epitaxial layer 110, so that the constant current diode VDH can adapt to different breakdown voltages. The fourth photoresist mask is removed by dissolving or ashing in a solvent after the implantation process.
Further, a first electrode terminal 180 is formed on the emitter region 150 through the oxide layer 102, and an electrical connection structure 190 is formed on the first doped region 140 and the third doped region 160 through the oxide layer 102, as shown in fig. 12.
In this step, for example, the Oxide layer 102 formed in the previous step is removed, and the Oxide layer 102 is re-formed on the surface of the epitaxial layer 110 by using a Low Pressure Chemical Vapor Deposition (LPCVD) process or a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, in which the material of the re-formed Oxide layer 102 includes Low temperature silicon dioxide (LTO) and the process temperature for forming the Low temperature silicon dioxide is not more than 850 ℃, wherein the temperature for using the LPCVD process is about 700 ℃, the temperature for using the PECVD process is about 400 ℃, and the thickness range of the Low temperature silicon dioxide includes
The junction depth of the third doped region 160 is then made not less than the junction depth of the base region 120, for example, using a rapid thermal (RAT) process. The deeper the junction depth of the third doped region 160, the smaller the series resistance of the constant current diode with the semiconductor substrate, the smaller the start voltage of the constant current diode, and the slightly larger the constant current operating voltage range.
Then, for example, a fifth photoresist mask is formed on the surface of the oxide layer 102, and the opening regions of the fifth photoresist mask correspond to the positions of the emitter region 150 and the first and third doped regions 140 and 160, respectively, and then anisotropic etching is performed to pattern the oxide layer 102 to form a plurality of connection holes and remove a portion of the oxide layer 102 to form a scribe region 103, as shown in fig. 12. Exposing a portion of the emitter region 150, a portion of the first doped region 140, and a portion of the third doped region 160 through a connection hole of an oxide layer, and then forming a first electrode terminal 180 and an electrical connection structure 190 at the connection hole, wherein the materials of the first electrode terminal 180 and the electrical connection structure 190 are preferably metallic aluminum, the first electrode terminal 180 connects the emitter region 150 with an external circuit through the connection hole, and the electrical connection structure 190 is electrically connected with the first doped region 140 and the third doped region 160, respectively. The scribe region 103 corresponds in position to the third doped region 160 and exposes a portion of the third doped region 160 through the scribe region 103. The fifth photoresist mask is removed by dissolving or ashing in a solvent after etching.
In some preferred embodiments, the third doped region 160 may be formed simultaneously with the base region 120, thereby reducing one photolithography, etching and implantation process and reducing the cost. In order to avoid the problem that the withstand voltage of the triode is too low due to the fact that the spacing distance between the base region 120 and the semiconductor substrate 101 is too small, the junction depth of the base region 120 can be properly reduced compared with the prior art.
In other preferred embodiments, to reduce the start voltage of the constant current diode, the annealing process may be controlled to contact the third doped region 160 with the semiconductor substrate 101.
In addition, if the production cost is not considered, the base region 120 and the third doped region 160 may be formed separately, for example, the third doped region 160 is formed first, and then the base region 120 is formed.
According to the utility model discloses a semiconductor device and manufacturing method thereof produces invariable undercurrent through epitaxial layer, first doping area, electric conduction route, second doping area and base region, enlargies invariable undercurrent through emitter region, base region and epitaxial layer again to semiconductor device's constant current function has been realized.
According to the utility model discloses a semiconductor device and manufacturing method thereof, through the breakdown voltage of the thickness control constant current diode of control second doping area along the first direction horizontal extension predetermined length, the resistivity of epitaxial layer and epitaxial layer, second doping area concentration, junction depth are controlled by even better high energy injection equipment's injection dosage, energy to constant current value homogeneity of constant current diode has been improved.
According to the utility model discloses a semiconductor device and manufacturing method thereof forms the triode through epitaxial layer, base region, emitter region, enlargies the invariable base current that constant current diode provided, has solved the less problem of prior art constant current diode unit area electric current.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present invention, and these alternatives and modifications are intended to fall within the scope of the present invention.
Claims (15)
1. A semiconductor device, comprising:
the semiconductor substrate, draw the second electrode terminal on the second surface of the said semiconductor substrate;
an epitaxial layer on a first surface of the semiconductor substrate;
the base region extends from the surface of the epitaxial layer into the epitaxial layer;
the emitter region extends from the surface of the base region into the base region to lead out a first electrode end;
a first doped region extending from the surface of the epitaxial layer into the epitaxial layer, the first doped region being separated from the base region by the epitaxial layer;
the second doping region is positioned in the epitaxial layer and is respectively contacted with the base region and the first doping region; and
an electrically conductive path for electrically connecting the first doped region with the epitaxial layer,
the doping types of the semiconductor substrate, the epitaxial layer and the emitter region are a first doping type, the doping types of the base region, the first doping region and the second doping region are a second doping type, and the first doping type is opposite to the second doping type.
2. The semiconductor device of claim 1, wherein the electrically conductive path comprises an electrical connection structure on the epitaxial layer and in contact with the first doped region to electrically connect the first doped region to the epitaxial layer.
3. The semiconductor device of claim 2, wherein the electrical conduction path further comprises a third doped region extending from the epitaxial layer surface into the epitaxial layer,
the electric connection structure is contacted with the third doped region so that the first doped region is electrically connected with the epitaxial layer through the electric connection structure and the third doped region in sequence,
wherein the third doped region is of a first doping type.
4. The semiconductor device of claim 3, further comprising a fourth doped region extending from the base region surface into the base region, the fourth doped region being located on at least one side of the emitter region, the fourth doped region being separated from the emitter region by the base region,
wherein the fourth doped region is of a second doping type.
5. The semiconductor device of claim 3, further comprising an oxide layer on the epitaxial layer covering the base region, at least a portion of the first doped region, and at least a portion of the emitter region,
wherein the oxide layer has at least one connection hole, and the first electrode terminal is in contact with the emitter region via the connection hole.
6. The semiconductor device of claim 5, further comprising a scribe region located to correspond to the third doped region and exposing at least a portion of the third doped region.
7. The semiconductor device according to claim 3, wherein the epitaxial layer, the first doped region, the second doped region, the electrically conductive path, and the base region constitute a constant current diode, the emitter region, the base region, and the epitaxial layer constitute a transistor, the constant current diode supplies a constant base current to the transistor, and the transistor is configured to amplify the base current to generate an output current of the semiconductor device.
8. The semiconductor device according to claim 7, wherein the second doped region extends laterally in a first direction by a predetermined length to contact the first doped region and the base region, respectively,
wherein the predetermined length corresponds to a breakdown voltage of the constant current diode.
9. The semiconductor device of claim 8, wherein a plurality of the second doped regions are distributed along a second direction, the epitaxial layer surrounds each of the second doped regions to separate each of the second doped regions,
wherein the first direction is perpendicular to the second direction, and the first direction and the second direction are both perpendicular to a longitudinal direction of the semiconductor device.
10. The semiconductor device according to any one of claims 1 to 9, wherein the second doped region has a doping concentration smaller than that of the first doped region.
11. The semiconductor device as claimed in any one of claims 1 to 9, wherein the second doped region has a doping profile in a range including 1.0E 11-3.0E 12cm-2。
12. The semiconductor device according to any one of claims 1 to 9, wherein a thickness of the epitaxial layer is in a range including 3 to 50 um.
13. The semiconductor device of any of claims 1-9, wherein the epitaxial layer has a resistivity in a range comprising 0.5 to 20ohm.
14. The semiconductor device of any of claims 1-9, wherein the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.
15. A semiconductor device according to any of claims 3 to 9, wherein the junction depth of the third doped region is greater than the junction depth of the base region.
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