CN210110756U - Memory cell and anti-fuse structure - Google Patents
Memory cell and anti-fuse structure Download PDFInfo
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- CN210110756U CN210110756U CN201921375981.2U CN201921375981U CN210110756U CN 210110756 U CN210110756 U CN 210110756U CN 201921375981 U CN201921375981 U CN 201921375981U CN 210110756 U CN210110756 U CN 210110756U
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- 230000005291 magnetic effect Effects 0.000 claims abstract description 46
- 238000002955 isolation Methods 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 18
- 230000001681 protective effect Effects 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 230000006870 function Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 20
- 239000000463 material Substances 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 5
- 229910000838 Al alloy Inorganic materials 0.000 description 4
- 229910019236 CoFeB Inorganic materials 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000005415 magnetization Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- 229910003321 CoFe Inorganic materials 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Abstract
The present disclosure provides a memory cell and an antifuse structure. The antifuse structure may include a first conductive layer, an antifuse layer, and a second conductive layer. The antifuse layer is disposed on the first conductive layer, and the antifuse layer includes a magnetic tunnel junction. The second conductive layer is arranged on one side of the antifuse layer far away from the first conductive layer. The present disclosure enables a memory cell to have a function of being programmable a plurality of times.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a memory cell and an antifuse structure.
Background
With the exponential increase of memory capacity, a Dynamic Random Access Memory (DRAM) chip manufactured by a semiconductor process inevitably generates defective memory cells. A repair technique commonly used in the art is to use redundant memory cells to permanently replace such defective memory cells. The repair technique needs to be completed by means of an Anti-fuse structure (Anti-fuse) which is nonvolatile on a chip, and data is stored by utilizing the principle that resistance changes after a dielectric layer in the Anti-fuse structure is broken down.
However, the existing antifuse structure enables only one-time programming (OTP) of the memory cell. How to design an antifuse structure to make a memory cell have a multi-time programmable function is a problem to be solved in the art.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
SUMMERY OF THE UTILITY MODEL
The present disclosure provides a memory cell and an antifuse structure, which can make the memory cell have a multi-time programmable function.
According to an aspect of the present disclosure, there is provided an antifuse structure, comprising:
a first conductive layer;
an antifuse layer disposed on the first conductive layer, the antifuse layer including a magnetic tunnel junction;
and the second conducting layer is arranged on one side, far away from the first conducting layer, of the antifuse layer.
In an exemplary embodiment of the present disclosure, the antifuse structure further includes:
the substrate is provided with a bearing surface, and a groove is formed on the bearing surface;
and the isolation structure body is filled in the groove, the first conducting layer is arranged on the isolation structure body, and the projection of the first conducting layer on the substrate is positioned in the projection area of the isolation structure body on the substrate.
In an exemplary embodiment of the present disclosure, a projection of the second conductive layer on the substrate is not coincident with a projection of the first conductive layer on the substrate.
In an exemplary embodiment of the present disclosure, the antifuse structure further includes:
a spacer on sidewalls of the first conductive layer and the antifuse layer, the spacer partially surrounding the first conductive layer.
In an exemplary embodiment of the present disclosure, the antifuse structure further includes:
a first contact electrode connected to the first conductive layer;
a second contact electrode connected with the second conductive layer.
In an exemplary embodiment of the present disclosure, the antifuse structure further includes:
and the protective top layer is arranged on one side, far away from the antifuse layer, of the second conducting layer, and the second contact electrode is embedded into the protective top layer.
In an exemplary embodiment of the present disclosure, the antifuse structure further includes:
and the gate oxide layer is arranged between the isolation structure body and the first conducting layer.
In an exemplary embodiment of the present disclosure, the magnetic tunnel junction includes:
the magnetic reference layer is arranged on the first conducting layer;
the tunnel barrier layer is arranged on one side, far away from the first conducting layer, of the magnetic reference layer;
and the free layer is arranged on one side of the tunnel barrier layer, which is far away from the magnetic reference layer.
According to an aspect of the present disclosure, there is provided a memory cell comprising the antifuse structure of any one of the above.
The memory cell and the antifuse structure have the function of being programmable for multiple times by changing the resistance value of the antifuse layer through changing the voltage or current applied between the two conductive layers because the antifuse layer between the first conductive layer and the second conductive layer is provided with the magnetic tunnel junction.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
FIG. 1 is a schematic diagram of an antifuse structure according to an embodiment of the present disclosure;
FIG. 2 is a cross-sectional view taken along the line A-A of the structure shown in FIG. 1;
FIG. 3 is a cross-sectional view taken in the direction B-B of the structure shown in FIG. 1;
FIG. 4 is a schematic diagram of a magnetic tunnel junction of an embodiment of the present disclosure;
FIG. 5 is a flow chart of a method of fabricating an antifuse structure according to an embodiment of the present disclosure;
fig. 6 is a flowchart of step S160 in the method for manufacturing the antifuse structure according to the embodiment of the present disclosure;
FIG. 7 is a flow chart of a programming method of an embodiment of the present disclosure.
In the figure: 1. a first conductive layer; 2. an antifuse layer; 21. a magnetic reference layer; 22. a tunnel barrier layer; 23. a free layer; 3. a second conductive layer; 4. a substrate; 5. an isolation structure; 6. a first contact electrode; 7. a second contact electrode; 8. a spacer; 9. a protective top layer; 10. and (4) a gate oxide layer.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, materials, devices, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. The terms "a" and "the" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
The disclosed embodiments provide an antifuse structure. As shown in fig. 1 to 3, the antifuse structure may include a first conductive layer 1, an antifuse layer 2, and a second conductive layer 3, wherein:
the antifuse layer 2 is disposed on the first conductive layer 1, and the antifuse layer 2 includes a magnetic tunnel junction. The second conductive layer 3 is disposed on a side of the antifuse layer 2 remote from the first conductive layer 1.
The antifuse structure of the embodiment of the present disclosure, since the antifuse layer 2 between the first conductive layer 1 and the second conductive layer 3 is provided with a magnetic tunnel junction, the resistance value of the antifuse layer 2 can be changed by changing the voltage or current applied between the two conductive layers, so that the memory cell having the antifuse structure has a multi-time programmable (MTP) function.
The following describes each part of the embodiments of the present disclosure in detail:
as shown in fig. 2 and fig. 3, the material of the first conductive layer 1 may be tungsten, titanium-aluminum alloy, but is not limited thereto, and may also be titanium nitride, tantalum nitride, or the like.
As shown in fig. 2 and 3, the antifuse layer 2 is provided on the first conductive layer 1. Specifically, the antifuse layer 2 is covered on the first conductive layer 1. As shown in FIG. 4, the antifuse layer 2 includes a magnetic tunnel junction. The magnetic tunnel junction may include a magnetic reference layer 21(reference layer), a tunnel barrier layer 22(tunnel barrier), and a free layer 23(free layer). The magnetic reference layer 21 may be provided on the first conductive layer 1. Wherein, the magnetic reference layer 21 covers the first conductive layer 1. The tunnel barrier layer 22 is disposed on a side of the magnetic reference layer 21 away from the first conductive layer 1, i.e., the magnetic reference layer 21 is disposed between the first conductive layer 1 and the tunnel barrier layer 22. The free layer 23 is disposed on a side of the tunnel barrier layer 22 away from the magnetic reference layer 21, i.e., the tunnel barrier layer 22 is disposed between the magnetic reference layer 21 and the free layer 23.
In one embodiment, the free layer 23 may also be provided on the first conductive layer 1. The tunnel barrier layer 22 is disposed on a side of the free layer 23 away from the first conductive layer 1, that is, the free layer 23 is disposed between the first conductive layer 1 and the tunnel barrier layer 22. The magnetic reference layer 21 is provided on the side of the tunnel barrier layer 22 remote from the free layer 23.
The material of the magnetic reference layer 21 can be CoFeB and the thickness can be CoFeB
The tunnel barrier layer 22 may be MgO and may have a thickness ofThe material of the free layer 23 may be CoFeB and the thickness may be CoFeB
The thickness of the magnetic tunnel junction may be 4nm at the minimum, but the embodiment of the present disclosure is not limited thereto. When the current through the antifuse layer 2 is changed from 10 to 100 μ a, its magnetoresistance ratio may be changed from 10 to 200. When the magnetization directions of the magnetic reference layer 21 and the free layer 23 are consistent, the electron spin directions in a plurality of states in the two layers of ferromagnetic materials are the same, the tunneling probability is higher, and the magnetic tunnel junction is in a low resistance state; conversely, when the magnetization directions of the magnetic reference layer 21 and the free layer 23 are not the same, the magnetic tunnel junction exhibits a high resistance state.
In addition, as shown in fig. 2 to 4, the antifuse layer 2 may further include a pinned layer (pinned layer) and a non-magnetic metal layer (non-magnetic metal). The fixed layer covers the first conductive layer 1, the non-magnetic metal layer covers the fixed layer, and the magnetic reference layer 21 covers the non-magnetic metal layer. The material of the fixed layer may be CoFe and the thickness may be
The nonmagnetic metal layer may be ruthenium (Ru) and may have a thickness of
As shown in fig. 2 and 3, the second conductive layer 3 is disposed on a side of the antifuse layer 2 away from the first conductive layer 1, that is, the antifuse layer 2 is disposed between the second conductive layer 3 and the first conductive layer 1. Wherein the second conductive layer 3 covers the antifuse layer 2. Specifically, the second conductive layer 3 covers the free layer 23. The material of the second conductive layer 3 may be tungsten, titanium-aluminum alloy, polysilicon, etc. Of course, the material of the second conductive layer 3 may also be titanium nitride, tantalum nitride, tungsten nitride, or the like.
As shown in fig. 1 to 3, the antifuse structure of the embodiment of the present disclosure may further include a substrate 4 and an isolation structure 5. The material of the substrate 4 may be undoped single crystal silicon, or may be impurity-doped single crystal silicon, but is not limited thereto, and may be silicon on insulator or the like. The substrate 4 may have a carrying surface. The carrying surface is opposite to the first conductive layer 1. The bearing surface is provided with a groove. The material of the isolation structure 5 may be silicon oxide, but may be silicon nitride. The isolation structure 5 may be filled in the trench. The region of the carrying surface of the substrate 4 outside the trench is flush with the surface of the isolation structure 5 facing the first conductive layer 1, that is, the trench on the carrying surface is filled up by the isolation structure 5, and the isolation structure 5 does not extend out of the carrying surface. The first conductive layer 1 may be provided on the isolation structure 5. The projection of the first conductive layer 1 onto the substrate 4 is located within the projection area of the isolation structure 5 onto the substrate 4. The projections are both orthographic projections. When the first conductive layer 1 is used as a gate electrode, a gate oxide layer 10 may be provided between the first conductive layer 1 and the isolation structure 5.
Further, as shown in fig. 1 to 3, the projection of the second conductive layer 3 on the substrate 4 is not coincident with the projection of the first conductive layer 1 on the substrate 4, so that the first conductive layer 1 and the second conductive layer 3 can be easily connected to a power supply, respectively. The antifuse structure of the embodiment of the present disclosure may further include a first contact electrode 6 and a second contact electrode 7. The first contact electrode 6 may be connected to the first conductive layer 1. The second contact electrode 7 may be connected to the second conductive layer 3. The first contact electrode 6 and the second contact electrode 7 are used for connection to a power supply to apply a voltage or current between the first conductive layer 1 and the second conductive layer 3. The antifuse structure of the disclosed embodiments may also include a protective top layer 9. The protective top layer 9 is disposed on a side of the second conductive layer 3 away from the antifuse layer 2, and the second contact electrode 7 is embedded in the protective top layer 9 and contacts the second conductive layer 3. The antifuse structure of the embodiments of the present disclosure may further include a spacer 8. The spacer 8 is located on the sidewalls of the first conductive layer 1 and the antifuse layer 2, and the spacer 8 partially surrounds the first conductive layer 1. Wherein the protruding area of the surface of the first conductive layer 1 not surrounded by the spacer 8 is available for connection with the first contact electrode 6.
For example, as shown in fig. 1 to 3, the antifuse structure of the embodiment of the present disclosure includes a substrate 4, an isolation structure body 5, a gate oxide layer 10, a first conductive layer 1, an antifuse structure, a second conductive layer 3, a spacer 8, a protective top layer 9, a first contact electrode 6, and a second contact electrode 7. The isolation structure 5 is filled in the trench of the substrate 4. The gate oxide layer 10 covers the isolation structure 5. The first conductive layer 1 covers the gate oxide layer 10. The antifuse layer 2 covers the first conductive layer 1. The second conductive layer 3 covers the antifuse layer 2. The spacer 8 is located on the sidewalls of the first conductive layer 1 and the antifuse layer 2, and the spacer 8 partially surrounds the first conductive layer 1. The first contact electrode 6 is connected to the first conductive layer 1. The second contact electrode 7 is connected to the second conductive layer 3.
The embodiment of the disclosure also provides a storage unit. The memory cell includes the antifuse structure described in the above embodiments. The antifuse structure employed in the memory cell of the embodiment of the present disclosure is the same as that in the above embodiment, and therefore, has the same beneficial effects, and is not described herein again.
The embodiment of the disclosure also provides a preparation method of the anti-fuse structure. The preparation method is used for preparing the anti-fuse structure of any one of the above embodiments. As shown in fig. 5, the method for manufacturing the antifuse structure may include steps S120 to S140, wherein:
step S120, forming a first conductive layer.
The first conductive layer may be made of tungsten, titanium-aluminum alloy, or polysilicon, but is not limited thereto, and may also be made of titanium nitride, tantalum nitride, tungsten nitride, or the like. The first conductive layer may be prepared by vapor deposition on a substrate.
Step S130 is to form an antifuse layer on the first conductive layer, and the antifuse layer includes a magnetic tunnel junction.
The antifuse layer may be formed by a vapor deposition method, but the embodiments of the present disclosure are not limited thereto. Specifically, step S130 may include: forming a magnetic reference layer on the first conductive layer; forming a tunnel barrier layer on one side of the magnetic reference layer far away from the magnetic reference layer; a free layer is formed on a side of the tunnel barrier layer away from the magnetic reference layer. The magnetic reference layer, the tunnel barrier layer and the free layer form a magnetic tunnel junction to form an antifuse layer.
Step S140 is to form a second conductive layer on the side of the antifuse layer away from the first conductive layer.
The material of the second conductive layer can be tungsten, titanium-aluminum alloy and the like. Of course, the material of the second conductive layer may also be titanium nitride, tantalum nitride, or the like. The second conductive layer may be formed by a vapor deposition method, but the embodiments of the present disclosure are not limited thereto. The formation process of the second conductive layer may be the same process as the formation process of the bit line in the memory cell array.
According to the method for manufacturing the antifuse structure, the antifuse layer between the first conductive layer and the second conductive layer is provided with the magnetic tunnel junction, so that the resistance value of the antifuse layer can be changed by changing the voltage or current applied between the two conductive layers, and a memory cell with the antifuse structure has a multi-time programmable function.
As shown in fig. 5, before step S120, the method for preparing an antifuse structure according to the embodiment of the present disclosure may further include step S100 and step S110, where:
step S100, a substrate having a carrying surface is provided.
The material of the substrate may be undoped single crystal silicon, or may be impurity-doped single crystal silicon, but is not limited thereto, and may be silicon on insulator or the like.
Step S110, forming a trench on the bearing surface, filling the trench with an isolation structure, and forming a gate oxide layer on the isolation structure.
The trench may be formed by etching. The material of the isolation structure may be silicon oxide, but may also be silicon nitride. The bearing surface of the substrate is located in the region outside the groove and is flush with the surface of the isolation structure body facing the first conductive layer, namely the groove on the bearing surface is filled up by the isolation structure body, and the isolation structure body does not extend out of the bearing surface. The gate oxide layer may be prepared by vapor deposition. The first conductive layer may be formed on a side of the gate oxide layer away from the substrate, and a projection of the first conductive layer on the substrate is located in a projection region of the isolation structure body on the substrate.
As shown in fig. 5, after step S140, the method for manufacturing an antifuse structure according to the embodiment of the present disclosure may further include step S150 and step S160, wherein:
step S150, forming a first contact electrode, wherein the first contact electrode is connected to the first conductive layer.
The material of the first contact electrode may be copper, but not limited thereto, and may also be other materials.
Step S160, forming a second contact electrode, wherein the second contact electrode is connected to the second conductive layer.
The material of the second contact electrode may be the same as the material of the first contact electrode, but not limited thereto, and may also be different. For example, the material of the second contact electrode is copper.
As shown in fig. 6, the step S160 may include:
and step S1601, forming a protective top layer on the side, away from the antifuse layer, of the second conductive layer.
The protective top layer can be prepared by vapor deposition.
Step S1602, forming electrode holes in the protective top layer, wherein the electrode holes penetrate through the protective top layer.
The electrode hole may be formed by etching, for example, by bombardment with high-density plasma, but the embodiments of the present disclosure are not limited thereto.
Step S1603 is to form a second contact electrode in the electrode hole, and the second contact electrode is filled in the electrode hole.
The two ends of the second contact electrode can also extend out of the electrode hole, one end of the second contact electrode can extend out of the contact surfaces of the protective top layer and the second conducting layer and is in contact with the second conducting layer, and the other end of the second contact electrode can extend out of the surface of the protective top layer and is used for being in contact with an external power supply.
In addition, before forming the electrode hole in the protective top layer, the method for manufacturing the antifuse structure according to the embodiment of the present disclosure may further include: covering the protruding region of the surface of the first conductive layer with a first mask; forming a gap wall, wherein the gap wall is positioned on the side walls of the first conductive layer, the antifuse layer and the protective top layer, the portion of the gap wall surrounds the first conductive layer, and the surface of the gap wall is flush with the upper surface of the protective top layer; the first mask is removed, exposing the protruding region of the surface of the first conductive layer.
The embodiment of the disclosure also provides a programming method. The programming method is based on the antifuse structure described in any of the above embodiments. As shown in fig. 7, the programming method may include a step a100 and a step a110, in which:
step A100, a first voltage or a first current is applied to the first conductive layer and the second conductive layer to change the resistance value of the antifuse layer to a first resistance value.
Step a110, applying a second voltage or a second current to the first conductive layer and the second conductive layer to change the resistance value of the antifuse layer to a second resistance value.
In the programming method according to the embodiment of the disclosure, since the antifuse layer between the first conductive layer and the second conductive layer is provided with the magnetic tunnel junction, when a voltage between the first conductive layer and the second conductive layer is changed from a first voltage to a second voltage or when a current between the first conductive layer and the second conductive layer is changed from a first current to a second current, a resistance value of the antifuse layer may be changed from a first resistance value to a second resistance value, so that the antifuse structure has a function of being programmable a plurality of times.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (9)
1. An antifuse structure, comprising:
a first conductive layer;
an antifuse layer disposed on the first conductive layer, the antifuse layer including a magnetic tunnel junction;
and the second conducting layer is arranged on one side, far away from the first conducting layer, of the antifuse layer.
2. The antifuse structure of claim 1, further comprising:
the substrate is provided with a bearing surface, and a groove is formed on the bearing surface;
and the isolation structure body is filled in the groove, the first conducting layer is arranged on the isolation structure body, and the projection of the first conducting layer on the substrate is positioned in the projection area of the isolation structure body on the substrate.
3. The antifuse structure of claim 2, wherein a projection of the second conductive layer on the substrate is non-coincident with a projection of the first conductive layer on the substrate.
4. The antifuse structure of claim 3, further comprising:
a spacer on sidewalls of the first conductive layer and the antifuse layer, the spacer partially surrounding the first conductive layer.
5. The antifuse structure of claim 3, further comprising:
a first contact electrode connected to the first conductive layer;
a second contact electrode connected with the second conductive layer.
6. The antifuse structure of claim 5, further comprising:
and the protective top layer is arranged on one side, far away from the antifuse layer, of the second conducting layer, and the second contact electrode is embedded into the protective top layer.
7. The antifuse structure of claim 2, further comprising:
and the gate oxide layer is arranged between the isolation structure body and the first conducting layer.
8. The antifuse structure of claim 1, wherein the magnetic tunnel junction comprises:
the magnetic reference layer is arranged on the first conducting layer;
the tunnel barrier layer is arranged on one side, far away from the first conducting layer, of the magnetic reference layer;
and the free layer is arranged on one side of the tunnel barrier layer, which is far away from the magnetic reference layer.
9. A memory cell comprising the antifuse structure of any one of claims 1 to 8.
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| GR01 | Patent grant |