CN210075080U - Output control circuit with power supply priority - Google Patents
Output control circuit with power supply priority Download PDFInfo
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- CN210075080U CN210075080U CN201921347540.1U CN201921347540U CN210075080U CN 210075080 U CN210075080 U CN 210075080U CN 201921347540 U CN201921347540 U CN 201921347540U CN 210075080 U CN210075080 U CN 210075080U
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Abstract
The utility model discloses an output control circuit with power supply priority, include: the first sampling comparison module is used for sampling the voltage at the first priority voltage output end Vo1, comparing the sampled voltage with a reference voltage and outputting a high level or a low level; the first output control module is used for receiving the high level or the low level output by the first sampling comparison module and judging whether to output a second priority voltage; the second sampling comparison module is used for sampling the voltage at the input end of the first output control module, comparing the sampled voltage with a reference voltage and outputting a high level or a low level; and the second output control module is used for receiving the high level or the low level output by the second sampling comparison module and judging whether to output a third priority voltage. The utility model discloses make switching power supply's a plurality of output interface's power supply realize priority output, only can make other interfaces have the output under the condition that the interface output current of high priority satisfies.
Description
Technical Field
The utility model relates to a control circuit specifically is an output control circuit with power supply priority.
Background
For the conventional multi-interface parallel output switching power supply at present, each structure cannot realize the priority of power supply, so that the interface needing preferential power supply can equally divide and change the output current of the switching power supply to cause a protection state, and terminal equipment can suddenly stop or abnormally work.
At present, switching power supplies with multiple interface outputs are connected in parallel, fig. 5 is a circuit diagram of the prior art, and a switching power supply with three USB interfaces (UP1, UP2, UP3) connected in parallel cannot realize the priority of power supply, which brings great inconvenience to people in the using process.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an output control circuit with power supply priority to solve the problem that proposes among the above-mentioned background art.
In order to achieve the above object, the utility model provides a following technical scheme:
an output control circuit having a power supply priority, comprising:
the first sampling comparison module is used for sampling the voltage at the first priority voltage output end Vo1, comparing the sampled voltage with a reference voltage and outputting a high level or a low level;
the first output control module is used for receiving the high level or the low level output by the first sampling comparison module and judging whether to output a second priority voltage;
the second sampling comparison module is used for sampling the voltage at the input end of the first output control module, comparing the sampled voltage with a reference voltage and outputting a high level or a low level;
and the second output control module is used for receiving the high level or the low level output by the second sampling comparison module and judging whether to output a third priority voltage.
As a further technical scheme of the invention: the first sampling comparison module comprises a resistor R8, a resistor R9 and a comparator U2A, the first output control module comprises a triode Q3 and a MOS transistor Q1, the second sampling comparison module comprises a triode Q4, a resistor R18, a resistor R19 and a comparator U2B, and the second output control module comprises a triode Q5 and a MOS transistor Q2;
the first priority voltage output end Vo1 is connected with a voltage input end Vi through a fuse F2, the voltage input end Vi is further respectively connected with a resistor R8, a fuse F3, a resistor R15, an emitter of a triode Q4, a resistor R18 and a fuse F4, the other end of the resistor R8 is respectively connected with a grounding resistor R9 and the same-phase end of a comparator U2A, the inverting end of the comparator U2A is connected with a resistor R6 through the resistor R7, the other end of the resistor R6 is connected with the resistor R13 and grounded, the other end of the resistor R13 is connected with the resistor R14, the output end of the comparator U2A is connected with a resistor R10 and a resistor R16 respectively, the other end of the resistor R10 is connected with the base of a triode Q3, the emitter of the triode Q3 is grounded, the collector of the triode Q3 is connected with a resistor R12, the other end of the resistor R12 is connected with a resistor R11 and the G pole of an MOS transistor Q1 respectively, the D pole of the MOS transistor Q1 is connected with the other end of a fuse F3 and the other end of a resistor R11 respectively, and the S pole of the MOS transistor Q1 is a second priority voltage output end Vo 2;
the other end of the resistor R16 is connected with the base of a triode Q4 and the other end of the resistor R15 respectively, the collector of the triode Q4 is connected with the resistor R17, the other end of the resistor R17 is connected with the other end of the resistor R14 and the inverting end of the comparator U2B respectively, the same-phase end of the comparator U2B is connected with the other ends of a grounding resistor R19 and a resistor R10 respectively, the output end of the comparator U2B is connected with the base of the triode Q5 through a resistor R20, the emitter of the triode Q5 is grounded, the collector of the triode Q5 is connected with a resistor R22, the other end of the resistor R22 is connected with the G pole of a resistor R21 and a MOS tube Q2 respectively, the D pole of the MOS tube Q2 is connected with the other end of a fuse F4 and the other.
As a further technical scheme of the invention: and the voltage input end Vi is a voltage output end of the switching power supply.
As a further technical scheme of the invention: the switching power supply comprises a chip IC1, an inductor L1, a capacitor CD1 and a fuse F1, one end of the fuse F1 is connected with a live wire, the other end of the fuse F1 is respectively connected with a capacitor CD1 and an inductor L1, the other end of the inductor L1 is respectively connected with a capacitor C1, a capacitor CD1, a resistor R1 and a pin 2 of the chip IC1, a pin 7 of the chip IC1 is connected with the other end of a resistor R1, a pin 6 of the chip IC1 is connected with the resistor R2, the other end of the resistor R2 is connected with a capacitor C2, a pin 8 of the chip IC1 is connected with a capacitor C1, a pin 1 of the chip IC1 is connected with a capacitor C1, the other ends of the capacitor C1 are respectively connected with a pin 3 of the chip IC1, a capacitor C1 and an inductor L1, the other end of the capacitor C1 is connected with a resistor R1, the other end of the inductor L1 is respectively connected with a resistor R1, a capacitor CD1, the other end of the capacitor, The chip IC1 pin 9, the chip IC1 pin 4, the other end of the capacitor C3, the other end of the capacitor C2, the other end of the capacitor C1, the other end of the capacitor CD2, the other end of the capacitor CD1 and a zero line end, wherein the other end of the resistor R5b is respectively connected with the other end of the resistor R5a and the pin 5 of the chip IC 1; chip IC1 is model APW 7304.
Compared with the prior art, the beneficial effects of the utility model are that: the utility model discloses can make the power supply of a plurality of output interfaces of switching power supply realize the priority of certain order, only can make other interfaces have the output under the condition that the interface output current of high priority satisfies, and then realize the power supply priority.
Drawings
Fig. 1 is a schematic block diagram of the circuit of the present invention.
Fig. 2 is a circuit diagram of the present invention.
Fig. 3 is a circuit diagram of an exemplary embodiment of the present invention.
Fig. 4 is a circuit diagram of a switching power supply used in cooperation with the present invention.
Fig. 5 is a schematic diagram of the prior art.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, the present invention provides an output control circuit with power supply priority, including:
the first sampling comparison module is used for sampling the voltage at the first priority voltage output end Vo1, comparing the sampled voltage with a reference voltage and outputting a high level or a low level;
the first output control module is used for receiving the high level or the low level output by the first sampling comparison module and judging whether to output a second priority voltage;
the second sampling comparison module is used for sampling the voltage at the input end of the first output control module, comparing the sampled voltage with a reference voltage and outputting a high level or a low level;
and the second output control module is used for receiving the high level or the low level output by the second sampling comparison module and judging whether to output a third priority voltage.
Preferably, referring to fig. 2, the first sampling comparison module includes a resistor R8, a resistor R9, and a comparator U2A, the first output control module includes a transistor Q3 and a MOS transistor Q1, the second sampling comparison module includes a transistor Q4, a resistor R18, a resistor R19, and a comparator U2B, and the second output control module includes a transistor Q5 and a MOS transistor Q2; the first priority voltage output end Vo1 is connected with a voltage input end Vi through a fuse F2, the voltage input end Vi is further respectively connected with a resistor R8, a fuse F3, a resistor R15, an emitter of a triode Q4, a resistor R18 and a fuse F4, the other end of the resistor R8 is respectively connected with a grounding resistor R9 and the same-phase end of a comparator U2A, the inverting end of the comparator U2A is connected with a resistor R6 through the resistor R7, the other end of the resistor R6 is connected with the resistor R13 and grounded, the other end of the resistor R13 is connected with the resistor R14, the output end of the comparator U2A is connected with a resistor R10 and a resistor R16 respectively, the other end of the resistor R10 is connected with the base of a triode Q3, the emitter of the triode Q3 is grounded, the collector of the triode Q3 is connected with a resistor R12, the other end of the resistor R12 is connected with a resistor R11 and the G pole of an MOS transistor Q1 respectively, the D pole of the MOS transistor Q1 is connected with the other end of a fuse F3 and the other end of a resistor R11 respectively, and the S pole of the MOS transistor Q1 is a second priority voltage output end Vo 2; the other end of the resistor R16 is connected with the base of a triode Q4 and the other end of the resistor R15 respectively, the collector of the triode Q4 is connected with the resistor R17, the other end of the resistor R17 is connected with the other end of the resistor R14 and the inverting end of the comparator U2B respectively, the inverting end of the comparator U2B is connected with the other ends of a grounding resistor R19 and a resistor R10 respectively, the output end of the comparator U2B is connected with the base of the triode Q5 through a resistor R20, the emitter of the triode Q5 is grounded, the collector of the triode Q5 is connected with a resistor R22, the other end of the resistor R22 is connected with the G poles of a resistor R21 and an MOS tube Q2 respectively, the D pole of the MOS tube Q2 is connected with the other end of a fuse F4 and the other end of a resistor R21 respectively, the S pole.
As an exemplary embodiment of the present invention, a circuit diagram of the control circuit applied to three USB interfaces of the present invention is shown in fig. 3.
In the figure: one end of a fuse F is respectively connected with a voltage input end Vi, a resistor R, a fuse F, a resistor R, an emitting electrode of a triode Q, a resistor R and the fuse F, the other end of the fuse F is connected with a power supply VCC end of a USB interface UP, the other end of the resistor R is respectively connected with a grounding resistor R and a same-phase end of a comparator U2, an inverting end of the comparator U2 is connected with the resistor R, the other end of the resistor R is respectively connected with grounding ends of the resistor R and the USB interface UP, the other end of the resistor R is respectively connected with the resistor R and grounded, the other end of the resistor R is connected with the grounding ends of the resistor R and the USB interface UP, the output end of the comparator U2 is respectively connected with the resistor R and the resistor R, the other end of the resistor R is connected with a base electrode of the triode Q, the emitting electrode of the triode Q, the D pole of the MOS tube Q1 is respectively connected with the other end of the fuse F3 and the other end of the resistor R11, and the S pole of the MOS tube Q1 is connected with the power VCC end of the USB interface UP 2; the other end of the resistor R16 is connected with the base of a triode Q4 and the other end of the resistor R15 respectively, the collector of the triode Q4 is connected with the resistor R17, the other end of the resistor R17 is connected with the other end of the resistor R14 and the inverting end of the comparator U2B respectively, the inverting end of the comparator U2B is connected with the other ends of a grounding resistor R19 and a resistor R10 respectively, the output end of the comparator U2B is connected with the base of the triode Q5 through a resistor R20, the emitter of the triode Q5 is grounded, the collector of the triode Q5 is connected with a resistor R22, the other end of the resistor R22 is connected with the G poles of a resistor R21 and an MOS tube Q2 respectively, the D pole of the MOS tube Q2 is connected with the other end of a fuse F4 and the other end of a resistor R21 respectively, the S pole of.
When the circuit works, when the USB interface UP1 has no overcurrent (normal output current and voltage), the USB interface UP2 and the USB interface UP3 can normally supply power, and when the USB interface UP1 has overcurrent, the triode Q3 and the MOS tube Q4 are output and controlled by the operational amplifier U2A, so that the USB interface UP2 and the USB interface UP3 stop supplying power.
Similarly, when the USB interface UP1 is not overcurrent, the USB interface UP2 is not overcurrent, so that the USB interface UP3 outputs normally, and when the USB interface UP2 is overcurrent, the operational amplifier U2B controls the transistor Q5 to turn off the MOS transistor Q2, thereby turning off the output of the USB interface UP 3.
The utility model discloses control circuit can cooperate switching power supply to use, provides a switching power supply as the example below, as shown in fig. 4, the utility model discloses be not limited to following example.
The switching power supply comprises a chip IC1, an inductor L1, a capacitor CD1 and a fuse F1, one end of the fuse F1 is connected with a live wire, the other end of the fuse F1 is respectively connected with a capacitor CD1 and an inductor L1, the other end of the inductor L1 is respectively connected with a capacitor C1, a capacitor CD1, a resistor R1 and a pin 2 of the chip IC1, a pin 7 of the chip IC1 is connected with the other end of a resistor R1, a pin 6 of the chip IC1 is connected with the resistor R2, the other end of the resistor R2 is connected with a capacitor C2, a pin 8 of the chip IC1 is connected with a capacitor C1, a pin 1 of the chip IC1 is connected with a capacitor C1, the other ends of the capacitor C1 are respectively connected with a pin 3 of the chip IC1, a capacitor C1 and an inductor L1, the other end of the capacitor C1 is connected with a resistor R1, the other end of the inductor L1 is respectively connected with a resistor R1, a capacitor CD1, the other end of the capacitor, The circuit comprises a chip IC1 pin 9, a chip IC1 pin 4, the other end of a capacitor C3, the other end of a capacitor C2, the other end of a capacitor C1, the other end of a capacitor CD2, the other end of a capacitor CD1 and a zero line end, the other end of a resistor R5b is respectively connected with the other end of a resistor R5a and a chip IC1 pin 5, and the model of the chip IC1 is APW 7304.
To sum up, the utility model discloses can make switching power supply's a plurality of output interface's power supply realize the priority of certain order, only can make other interfaces have the output under the condition that the interface output current of high priority satisfies, and then realize the power supply priority.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (4)
1. An output control circuit having a power supply priority, comprising:
the first sampling comparison module is used for sampling the voltage at the first priority voltage output end Vo1, comparing the sampled voltage with a reference voltage and outputting a high level or a low level;
the first output control module is used for receiving the high level or the low level output by the first sampling comparison module and judging whether to output a second priority voltage;
the second sampling comparison module is used for sampling the voltage at the input end of the first output control module, comparing the sampled voltage with a reference voltage and outputting a high level or a low level;
and the second output control module is used for receiving the high level or the low level output by the second sampling comparison module and judging whether to output a third priority voltage.
2. The output control circuit with power supply priority as claimed in claim 1, wherein the first sampling comparison module comprises a resistor R8, a resistor R9 and a comparator U2A, the first output control module comprises a transistor Q3 and a MOS transistor Q1, the second sampling comparison module comprises a transistor Q4, a resistor R18, a resistor R19 and a comparator U2B, and the second output control module comprises a transistor Q5 and a MOS transistor Q2;
the first priority voltage output end Vo1 is connected with a voltage input end Vi through a fuse F2, the voltage input end Vi is further respectively connected with a resistor R8, a fuse F3, a resistor R15, an emitter of a triode Q4, a resistor R18 and a fuse F4, the other end of the resistor R8 is respectively connected with a grounding resistor R9 and the same-phase end of a comparator U2A, the inverting end of the comparator U2A is connected with a resistor R6 through the resistor R7, the other end of the resistor R6 is connected with the resistor R13 and grounded, the other end of the resistor R13 is connected with the resistor R14, the output end of the comparator U2A is connected with a resistor R10 and a resistor R16 respectively, the other end of the resistor R10 is connected with the base of a triode Q3, the emitter of the triode Q3 is grounded, the collector of the triode Q3 is connected with a resistor R12, the other end of the resistor R12 is connected with a resistor R11 and the G pole of an MOS transistor Q1 respectively, the D pole of the MOS transistor Q1 is connected with the other end of a fuse F3 and the other end of a resistor R11 respectively, and the S pole of the MOS transistor Q1 is a second priority voltage output end Vo 2;
the other end of the resistor R16 is connected with the base of a triode Q4 and the other end of the resistor R15 respectively, the collector of the triode Q4 is connected with the resistor R17, the other end of the resistor R17 is connected with the other end of the resistor R14 and the inverting end of the comparator U2B respectively, the same-phase end of the comparator U2B is connected with the other ends of a grounding resistor R19 and a resistor R10 respectively, the output end of the comparator U2B is connected with the base of the triode Q5 through a resistor R20, the emitter of the triode Q5 is grounded, the collector of the triode Q5 is connected with a resistor R22, the other end of the resistor R22 is connected with the G pole of a resistor R21 and a MOS tube Q2 respectively, the D pole of the MOS tube Q2 is connected with the other end of a fuse F4 and the other.
3. Output control circuit with power supply priority according to claim 2, characterized in that the voltage input Vi is a voltage output of a switching power supply.
4. The output control circuit with power supply priority as claimed in claim 3, wherein the switching power supply comprises a chip IC, an inductor L, a capacitor CD and a fuse F, one end of the fuse F is connected with a live wire, the other end of the fuse F is respectively connected with the capacitor CD and the inductor L, the other end of the inductor L is respectively connected with the capacitor C, the capacitor CD, the resistor R and a chip IC pin 2, a chip IC pin 7 is connected with the other end of the resistor R, a chip IC pin 6 is connected with the resistor R, the other end of the resistor R is connected with the capacitor C, a chip IC pin 8 is connected with the capacitor C, a chip IC pin 1 is connected with the capacitor C, the other end of the capacitor C is respectively connected with a chip IC pin 3, the capacitor C and the inductor L, the other end of the capacitor C is connected with the resistor R, the other end of the inductor L is respectively connected with the voltage output ends of, The circuit comprises the other end of a capacitor CD3, a resistor R5b, a resistor R5a, the other end of a resistor R3, a pin 9 of a chip IC1, a pin 4 of a chip IC1, the other end of a capacitor C3, the other end of a capacitor C2, the other end of a capacitor C1, the other end of a capacitor CD2, the other end of a capacitor CD1 and a zero line end, the other end of the resistor R5b is connected with the other end of the resistor R5a and the pin 5 of the chip IC1 respectively, and the chip IC1 is APW.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921347540.1U CN210075080U (en) | 2019-08-19 | 2019-08-19 | Output control circuit with power supply priority |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921347540.1U CN210075080U (en) | 2019-08-19 | 2019-08-19 | Output control circuit with power supply priority |
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| CN210075080U true CN210075080U (en) | 2020-02-14 |
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| CN201921347540.1U Active CN210075080U (en) | 2019-08-19 | 2019-08-19 | Output control circuit with power supply priority |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114784783A (en) * | 2022-06-22 | 2022-07-22 | 广州市保伦电子有限公司 | Automatic identification selection input power supply system |
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2019
- 2019-08-19 CN CN201921347540.1U patent/CN210075080U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114784783A (en) * | 2022-06-22 | 2022-07-22 | 广州市保伦电子有限公司 | Automatic identification selection input power supply system |
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