CN210041777U - Circuit structure with first-order filtering and circuit time constant calibration functions - Google Patents
Circuit structure with first-order filtering and circuit time constant calibration functions Download PDFInfo
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- CN210041777U CN210041777U CN201921206228.0U CN201921206228U CN210041777U CN 210041777 U CN210041777 U CN 210041777U CN 201921206228 U CN201921206228 U CN 201921206228U CN 210041777 U CN210041777 U CN 210041777U
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Abstract
The utility model provides a circuit structure with first-order filtering and circuit time constant calibration function relates to integrated circuit technical field. The circuit comprises a clock generating circuit, a circuit time constant acquisition circuit, a comparator and a digital processing unit; three paths of clock signals generated by the clock generating circuit are respectively connected with the circuit time constant acquisition circuit, the output of the circuit time constant acquisition circuit is connected with the comparator, the output of the comparator is connected with the digital processing unit, and the digital processing unit is connected with the circuit time constant acquisition circuit. The utility model discloses can realize the effect of first-order filtering and circuit time constant calibration, have the low power dissipation, area occupied is little, the reliable characteristics of simple structure.
Description
Technical Field
The utility model relates to an integrated circuit technical field especially indicates a circuit structure with first-order filtering and circuit time constant calibration function.
Background
The calibration of the circuit time constant is widely applied to the design of integrated circuits, and is an indispensable part for ensuring the stable and reliable operation of the whole system. The circuit time constant determines the working bandwidth of the system, and the system can be ensured to work in the required optimal state by calibrating the circuit time constant so as to achieve the best system performance.
In the manufacturing and working processes of the chip, the resistance and capacitance values of the circuit are interfered by unstable factors such as production process, voltage fluctuation and temperature, so that the generated circuit time constant is different, the bandwidth of the circuit is different from the designed value, and therefore the calibration circuit is required to calibrate the generated circuit time constant. The traditional circuit time constant calibration circuit with the automatic calibration function realizes calibration in a simulation mode, has high power consumption, needs to additionally design a circuit time constant acquisition circuit, and has large system area and high complexity.
The inventor of the present invention finds that, in actual work, a system usually needs to filter signals, and filter out noise and interference outside a signal bandwidth, and since calibration of a circuit time constant is completed before the system does not process signals at the initial power-on of the system, the time for calibrating the filter function and the circuit time constant is not in conflict, and if the circuit for calibrating the filter circuit and the circuit time constant is multiplexed, the chip area and the power consumption can be greatly reduced.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a circuit structure with first-order filtering and circuit time constant calibration function, its calibration mode consumption is little to realized the circuit and multiplexed, can reduce chip area, simplify circuit structure, improve the reliability of chip.
In order to realize the purpose, the utility model discloses the technical scheme who adopts is:
a circuit structure with first-order filtering and circuit time constant calibration functions comprises a clock generation circuit, a circuit time constant acquisition circuit, a comparator and a digital processing unit;
the clock generating circuit is used for generating three paths of clocks, wherein a first path of clock and a second path of clock are phase orthogonal signals, and a third path of clock is respectively a non-overlapping clock with the first path of clock and the second path of clock; the digital processing unit is a programmable digital circuit;
the circuit time constant acquisition circuit comprises a front-end circuit, an operational amplifier, a first adjustable capacitor circuit and a second adjustable capacitor circuit; the first adjustable capacitor circuit is connected between the input positive end and the output negative end of the operational amplifier in parallel, and the second adjustable capacitor circuit is connected between the input negative end and the output positive end of the operational amplifier in parallel; the front-end circuit is provided with a reference high-level end, a reference low-level end, a signal input positive end, a signal input negative end and a calibration enabling end, the output negative end of the operational amplifier is the signal output negative end of the circuit time constant acquisition circuit, and the output positive end of the operational amplifier is the signal output positive end of the circuit time constant acquisition circuit;
the three paths of clock outputs generated by the clock generating circuit are respectively transmitted to the circuit time constant acquisition circuit through the front-end circuit, the signal output positive end of the circuit time constant acquisition circuit is connected with the input positive end of the comparator, the signal output negative end of the circuit time constant acquisition circuit is connected with the input negative end of the comparator, the output of the comparator is connected with the sampling input end of the digital processing unit, the control output end of the digital processing unit is connected with the first adjustable capacitor circuit and the second adjustable capacitor circuit and used for adjusting the capacitance values of the first adjustable capacitor circuit and the second adjustable capacitor circuit, and therefore the adjustment of the circuit time constant is completed.
Optionally, the circuit time constant acquisition circuit is composed of an operational amplifier, a plurality of switches, a resistor, a capacitor and an inverter; the reference high level end is respectively connected with one end of a first switch, one end of a second switch and one end of a fifth switch; the reference low level end is respectively connected with one end of the third switch, one end of the fourth switch and one end of the sixth switch; the positive signal input end is connected with one end of the fifth resistor, and the negative signal input end is connected with one end of the sixth resistor; the other end of the first switch is respectively connected with the other end of the third switch and one end of the third resistor, and the control end of the first switch is respectively connected with the control end of the fourth switch and the output end of the first phase inverter; the other end of the second switch is respectively connected with the other end of the fourth switch and one end of the first resistor, and the control end of the second switch is respectively connected with the control end of the third switch, the input end of the first phase inverter and the second path of clock output of the clock generating circuit; the other end of the fifth switch is respectively connected with one end of the seventh switch and the input negative end of the comparator, and the control end of the fifth switch is respectively connected with the control end of the sixth switch and the third path of clock output of the clock generation circuit; the other end of the sixth switch is respectively connected with one end of the eighth switch and the input positive end of the comparator; the other end of the first resistor is connected with one end of a ninth switch, the other end of the third resistor is connected with one end of a tenth switch, the other end of the fifth resistor is connected with one end of an eleventh switch, and the other end of the sixth resistor is connected with one end of a twelfth switch; the other end of the ninth switch is respectively connected with an input positive end of the operational amplifier, one end of the first capacitor, one end of the tenth capacitor, one end of the eleventh capacitor, one end of the twelfth capacitor, one end of the thirteenth capacitor, one end of the second resistor and the other end of the eleventh switch; the control end of the ninth switch is respectively connected with the control end of the tenth switch, the input end of the second inverter and the calibration enabling end; the other end of the tenth switch is respectively connected with the negative input end of the operational amplifier, one end of the second capacitor, one end of the twentieth capacitor, one end of the twenty-first capacitor, one end of the twenty-second capacitor, one end of the twenty-third capacitor, one end of the fourth resistor and the other end of the twelfth switch; the control end of the eleventh switch is respectively connected with the control end of the twelfth switch and the output end of the second phase inverter; the other end of the first capacitor is connected with one end of a thirteenth switch, one end of a fourteenth switch, one end of a fifteenth switch, one end of a sixteenth switch, the other end of the second resistor, the negative output terminal of the operational amplifier, the other end of the seventh switch and the negative signal output terminal respectively; the other end of the tenth capacitor is connected with the other end of the thirteenth switch, the other end of the eleventh capacitor is connected with the other end of the fourteenth switch, the other end of the twelfth capacitor is connected with the other end of the fifteenth switch, and the other end of the thirteenth capacitor is connected with the other end of the sixteenth switch; the other end of the second capacitor is respectively connected with one end of a twentieth switch, one end of a twenty-first switch, one end of a twenty-second switch, one end of a twentieth switch, the other end of a fourth resistor, an operational amplifier output positive end, the other end of an eighth switch and a signal output positive end; the other end of the twenty-first capacitor is connected with the other end of the twenty-first switch, the other end of the twenty-second capacitor is connected with the other end of the twenty-second switch, and the other end of the twenty-third capacitor is connected with the other end of the twenty-third switch; the seventh switch control end is respectively connected with the eighth switch control end and the first clock output of the clock generation circuit; the control output end of the digital processing unit is respectively connected with the thirteenth switch control end, the fourteenth switch control end, the fifteenth switch control end, the sixteenth switch control end, the twentieth switch control end, the twenty-first switch control end, the twenty-second switch control end and the twenty-third switch control end.
Compared with the prior art, the utility model discloses following beneficial effect has:
1. the utility model discloses a circuit time constant calibration circuit pass through the selection of switch and can realize the effect of first-order filtering and the effect of circuit time constant calibration, and then realize that the module is multiplexing. Compared with the traditional analog calibration mode, the chip area is reduced.
2. The utility model discloses can adopt digital mode to realize the calibration to clock circuit, the low power dissipation, calibration control unit can get into sleep mode after accomplishing the calibration to further reduce system's consumption and noise interference have higher practical application and worth.
Drawings
Fig. 1 is a block diagram of a circuit structure with first-order filtering and circuit time constant calibration functions according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a circuit structure with first-order filtering and circuit time constant calibration functions according to an embodiment of the present invention.
Fig. 3 is a control flow chart of the digital processing unit according to the embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
FIG. 1 is a block diagram of a circuit structure with first-order filtering and circuit time constant calibration functions, including a clock generating circuit, a circuit time constant collecting circuit, a comparator and a digital processing unit; wherein the content of the first and second substances,
the clock generating circuit is used for generating three paths of clocks, wherein a first path of clock and a second path of clock are phase orthogonal signals, and a third path of clock is respectively a non-overlapping clock with the first path of clock and the second path of clock; the digital processing unit is a programmable digital circuit with automatic calibration and automatic sleep functions;
the circuit time constant acquisition circuit comprises a front-end circuit, an operational amplifier, a first adjustable capacitor circuit and a second adjustable capacitor circuit; the first adjustable capacitor circuit is connected between the input positive end and the output negative end of the operational amplifier in parallel, and the second adjustable capacitor circuit is connected between the input negative end and the output positive end of the operational amplifier in parallel; the front-end circuit is provided with a reference high-level end, a reference low-level end, a signal input positive end, a signal input negative end and a calibration enabling end, the output negative end of the operational amplifier is the signal output negative end of the circuit time constant acquisition circuit, and the output positive end of the operational amplifier is the signal output positive end of the circuit time constant acquisition circuit;
three clock outputs generated by the clock generating circuit are respectively transmitted to the circuit time constant acquisition circuit through the front-end circuit, the signal output positive end of the circuit time constant acquisition circuit is connected with the input positive end of the comparator, the signal output negative end of the circuit time constant acquisition circuit is connected with the input negative end of the comparator, the output of the comparator is connected with the sampling input end of the digital processing unit, the control output end of the digital processing unit is connected with the first adjustable capacitor circuit and the second adjustable capacitor circuit and used for adjusting the capacitance values of the first adjustable capacitor circuit and the second adjustable capacitor circuit, and therefore the adjustment of the circuit time constant is completed;
the digital processing unit outputs a lock signal after the calibration is completed.
The digital processing unit can be realized by adopting an FPGA, for example, the FPGA with the model of xc7v2000tflg 1925-2. Thus, the sampling input end of the digital processing unit is connected with the A3 port of the FPGA, the control output end is respectively connected with the M25, A24, E23 and K27 ports of the FPGA, and the locking signal output port is connected with the A5 port of the FPGA.
Fig. 2 is a schematic diagram of a specific implementation of the clock generation circuit. In the circuit, a capacitor is marked by C plus a serial number, an inverter is marked by INV plus a serial number, a resistor is marked by R plus a serial number, and a switch is marked by S plus a serial number.
In the circuit, a reference high level is respectively connected with one end of a first switch S1, one end of a second switch S2 and one end of a fifth switch S5; the reference low level is respectively connected with one end of the third switch S3, one end of the fourth switch S4 and one end of the sixth switch S6; the positive end of the signal input is connected with one end of a fifth resistor R5, and the negative end of the signal input is connected with one end of a sixth resistor R6; the other end of the first switch S1 is connected to the other end of the third switch S3 and one end of the third resistor R3, respectively, and the control end of the first switch S1 is connected to the control end of the fourth switch S4 and the output end of the first inverter INV1, respectively; the other end of the second switch S2 is connected to the other end of the fourth switch S4 and one end of the first resistor R1, respectively, and the control end of the second switch S2 is connected to the control end of the third switch S3, the input end of the first inverter INV1, and the second output of the clock generation circuit, respectively; the other end of the fifth switch R5 is connected to one end of the seventh switch S7 and the negative input terminal of the comparator, respectively, and the control terminal of the fifth switch S5 is connected to the control terminal of the sixth switch S6 and the third output of the clock generation circuit, respectively; the other end of the sixth switch S6 is connected to one end of the eighth switch S8 and the positive input terminal of the comparator, respectively; the other end of the first resistor R1 is connected with one end of a ninth switch S9, the other end of the third resistor R3 is connected with one end of a tenth switch S10, the other end of the fifth resistor R5 is connected with one end of an eleventh switch S11, and the other end of the sixth resistor R6 is connected with one end of a twelfth switch S12; the other end of the ninth switch S9 is connected to the positive terminal of the operational amplifier, one end of the first capacitor C1, one end of the tenth capacitor C10, one end of the eleventh capacitor C11, one end of the twelfth capacitor C12, one end of the thirteenth capacitor C13, one end of the second resistor R2, and the other end of the eleventh switch S11, respectively; a control end of the ninth switch S9 is connected to a control end of the tenth switch S10, an input end of the second inverter INV2, and a calibration enable, respectively; the other end of the tenth switch S10 is connected to the negative terminal of the operational amplifier, one end of the second capacitor C2, one end of the twentieth capacitor C20, one end of the twenty-first capacitor C21, one end of the twenty-second capacitor C22, one end of the twenty-third capacitor C23, one end of the fourth resistor R4, and the other end of the twelfth switch S12, respectively; a control end of the eleventh switch S11 is connected to a control end of the twelfth switch S12 and an output end of the second inverter INV2, respectively; the other end of the first capacitor C1 is connected to one end of a thirteenth switch S13, one end of a fourteenth switch S14, one end of a fifteenth switch S15, one end of a sixteenth switch S16, the other end of the second resistor R2, an output negative terminal of the operational amplifier, the other end of the seventh switch S7 and a signal output negative terminal respectively; the other end of a tenth capacitor C10 is connected with the other end of a thirteenth switch S13, the other end of an eleventh capacitor C11 is connected with the other end of a fourteenth switch S14, the other end of a twelfth capacitor C12 is connected with the other end of a fifteenth switch S15, and the other end of a thirteenth capacitor C13 is connected with the other end of a sixteenth switch S16; the other end of the second capacitor C2 is connected to one end of a twentieth switch S20, one end of a twenty-first switch S21, one end of a twenty-second switch S22, one end of a twentieth switch S23, the other end of a fourth resistor R4, an operational amplifier output positive terminal, the other end of an eighth switch S8 and a signal output positive terminal respectively; the other end of the twentieth capacitor C20 is connected with the other end of a twentieth switch S20, the other end of the twenty-first capacitor C21 is connected with the other end of a twenty-first switch S21, the other end of the twenty-second capacitor C22 is connected with the other end of a twenty-second switch S22, and the other end of the twenty-third capacitor C23 is connected with the other end of a twenty-third switch S23; the control end of the seventh switch S7 is respectively connected with the control end of the eighth switch S8 and the first output end of the clock generating circuit; the output end of the comparator is connected with the input end of the digital processing unit; the output end of the digital processing unit is respectively connected with a control end of a thirteenth switch S13, a control end of a fourteenth switch S14, a control end of a fifteenth switch S15, a control end of a sixteenth switch S16, a control end of a twentieth switch S20, a control end of a twenty-first switch S21, a control end of a twenty-second switch S22 and a control end of a twenty-third switch S23; the other end of the digital processing unit output is a locking signal.
FIG. 3 is a control flow diagram of a digital processing unit, comprising the steps of:
(1) electrifying initial configuration, writing in a default calibration word, and setting a calibration locking signal to be zero;
(2) judging the level of the sampling input signal I, and if the level I is high, switching to the step (3), and if the level I is low, switching to the step (4);
(3) subtracting 1 from the calibration word and outputting the calibration word through a control output end, judging whether the calibration word is 0 or the calibration word changes in the opposite direction, if so, turning to the step (5), otherwise, turning to the step (2);
(4) adding 1 to the calibration word and outputting the calibration word through a control output end, judging whether the calibration word is 1111 or the calibration word changes in the opposite direction, if so, turning to the step (5), otherwise, turning to the step (2);
(5) and locking the calibration word, outputting a calibration locking signal through a locking output end, and enabling the digital processing unit to enter a sleep mode.
The specific working principle of the circuit structure with the first-order filtering and circuit time constant calibration functions is as follows:
the calibration of the circuit time constant is initially carried out when the system is electrified, the automatic calibration is carried out when the enabling signal is in a high level, the digital processing unit writes in a default calibration word, and the calibration locking signal is set to be zero. The clock generating circuit generates three paths of clocks, wherein the first path of clock and the second path of clock are orthogonal to each other, the third path of clock is respectively a non-overlapping clock with the first path of clock and the second path of clock, an input differential square wave signal is generated through the control of the second path of clock on and off of a reference high level and a reference low level, and the switching time of the high level and the low level of the square wave signal is the same as the high level time of the second path of clock. The generated differential square wave input signal passes through a charge-discharge network formed by an operational amplifier and a resistor capacitor and then is output through a seventh switch and an eighth switch, the seventh switch and the eighth switch are controlled by a first clock generated by a clock generating circuit, and finally, a charge-discharge signal in a time period in which the first clock and a second clock are orthogonal passes through a comparator; and resetting the comparator input signal within the high level time of the third path of clock generated by the clock generation circuit. The output of the comparator is input into a digital processing unit, an input signal is sampled and marked as I, the level of the input signal I is judged, if the I is high level, the circuit time constant is larger than the time that a first path of clock and a second path of clock are orthogonal, the circuit time constant is reduced by subtracting 1 from a calibration word, then the output signal of the comparator is sampled and judged until the calibration word is 0 or the calibration word changes in the opposite direction, and the calibration of the circuit time constant is completed at this moment; if the I is low level, the circuit time constant is smaller than the mutual orthogonal time of the first path clock and the second path clock, the circuit time constant is increased by adding 1 to the calibration word, then sampling is carried out, the output signal of the comparator is judged until the calibration word is 1111 or the calibration word changes in the opposite direction, and the calibration of the circuit time constant is completed at this moment; and finally, locking the calibration word, outputting a calibration locking signal, and enabling the digital processing unit to enter a sleep mode to finish calibration. And after the automatic calibration of the circuit time constant is completed, the circuit works in a normal working state, the enable signal is set to be at a high level, the signal input is completed, and the first-order filtering effect is realized.
In summary, in the manufacturing process of the integrated circuit, the resistance and capacitance values may deviate from their designed values under the interference of unstable factors such as the production process, voltage fluctuation and temperature, which causes the deviation of the circuit time constant. To this, the utility model discloses a circuit structure that has first-order filtering and circuit time constant calibration function realizes the calibration to circuit time constant, the effect of the effect that can realize first-order filtering and the effect of circuit time constant calibration through the selection of switch, compare with traditional simulation calibration mode, can realize that the module is multiplexing, the chip area has been reduced, the mode that adopts digital calibration can reduce the consumption, calibration control unit gets into the consumption and the noise interference that the dormancy mode then can further reduce the system after accomplishing the calibration, higher practical application is worth.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment, but all equivalent modifications or changes made by those skilled in the art according to the present invention should be included in the protection scope of the claims.
Claims (2)
1. A circuit structure with first-order filtering and circuit time constant calibration functions is characterized by comprising a clock generation circuit, a circuit time constant acquisition circuit, a comparator and a digital processing unit;
the clock generating circuit is used for generating three paths of clocks, wherein a first path of clock and a second path of clock are phase orthogonal signals, and a third path of clock is respectively a non-overlapping clock with the first path of clock and the second path of clock; the digital processing unit is a programmable digital circuit;
the circuit time constant acquisition circuit comprises a front-end circuit, an operational amplifier, a first adjustable capacitor circuit and a second adjustable capacitor circuit; the first adjustable capacitor circuit is connected between the input positive end and the output negative end of the operational amplifier in parallel, and the second adjustable capacitor circuit is connected between the input negative end and the output positive end of the operational amplifier in parallel; the front-end circuit is provided with a reference high-level end, a reference low-level end, a signal input positive end, a signal input negative end and a calibration enabling end, the output negative end of the operational amplifier is the signal output negative end of the circuit time constant acquisition circuit, and the output positive end of the operational amplifier is the signal output positive end of the circuit time constant acquisition circuit;
the three paths of clock outputs generated by the clock generating circuit are respectively transmitted to the circuit time constant acquisition circuit through the front-end circuit, the signal output positive end of the circuit time constant acquisition circuit is connected with the input positive end of the comparator, the signal output negative end of the circuit time constant acquisition circuit is connected with the input negative end of the comparator, the output of the comparator is connected with the sampling input end of the digital processing unit, the control output end of the digital processing unit is connected with the first adjustable capacitor circuit and the second adjustable capacitor circuit and used for adjusting the capacitance values of the first adjustable capacitor circuit and the second adjustable capacitor circuit, and therefore the adjustment of the circuit time constant is completed.
2. The circuit structure with first-order filtering and calibration of circuit time constant as claimed in claim 1,
the circuit time constant acquisition circuit consists of an operational amplifier, a plurality of switches, a resistor, a capacitor and a phase inverter; the reference high level end is respectively connected with one end of a first switch, one end of a second switch and one end of a fifth switch; the reference low level end is respectively connected with one end of the third switch, one end of the fourth switch and one end of the sixth switch; the positive signal input end is connected with one end of the fifth resistor, and the negative signal input end is connected with one end of the sixth resistor; the other end of the first switch is respectively connected with the other end of the third switch and one end of the third resistor, and the control end of the first switch is respectively connected with the control end of the fourth switch and the output end of the first phase inverter; the other end of the second switch is respectively connected with the other end of the fourth switch and one end of the first resistor, and the control end of the second switch is respectively connected with the control end of the third switch, the input end of the first phase inverter and the second path of clock output of the clock generating circuit; the other end of the fifth switch is respectively connected with one end of the seventh switch and the input negative end of the comparator, and the control end of the fifth switch is respectively connected with the control end of the sixth switch and the third path of clock output of the clock generation circuit; the other end of the sixth switch is respectively connected with one end of the eighth switch and the input positive end of the comparator; the other end of the first resistor is connected with one end of a ninth switch, the other end of the third resistor is connected with one end of a tenth switch, the other end of the fifth resistor is connected with one end of an eleventh switch, and the other end of the sixth resistor is connected with one end of a twelfth switch; the other end of the ninth switch is respectively connected with an input positive end of the operational amplifier, one end of the first capacitor, one end of the tenth capacitor, one end of the eleventh capacitor, one end of the twelfth capacitor, one end of the thirteenth capacitor, one end of the second resistor and the other end of the eleventh switch; the control end of the ninth switch is respectively connected with the control end of the tenth switch, the input end of the second inverter and the calibration enabling end; the other end of the tenth switch is respectively connected with the negative input end of the operational amplifier, one end of the second capacitor, one end of the twentieth capacitor, one end of the twenty-first capacitor, one end of the twenty-second capacitor, one end of the twenty-third capacitor, one end of the fourth resistor and the other end of the twelfth switch; the control end of the eleventh switch is respectively connected with the control end of the twelfth switch and the output end of the second phase inverter; the other end of the first capacitor is connected with one end of a thirteenth switch, one end of a fourteenth switch, one end of a fifteenth switch, one end of a sixteenth switch, the other end of the second resistor, the negative output terminal of the operational amplifier, the other end of the seventh switch and the negative signal output terminal respectively; the other end of the tenth capacitor is connected with the other end of the thirteenth switch, the other end of the eleventh capacitor is connected with the other end of the fourteenth switch, the other end of the twelfth capacitor is connected with the other end of the fifteenth switch, and the other end of the thirteenth capacitor is connected with the other end of the sixteenth switch; the other end of the second capacitor is respectively connected with one end of a twentieth switch, one end of a twenty-first switch, one end of a twenty-second switch, one end of a twentieth switch, the other end of a fourth resistor, an operational amplifier output positive end, the other end of an eighth switch and a signal output positive end; the other end of the twenty-first capacitor is connected with the other end of the twenty-first switch, the other end of the twenty-second capacitor is connected with the other end of the twenty-second switch, and the other end of the twenty-third capacitor is connected with the other end of the twenty-third switch; the seventh switch control end is respectively connected with the eighth switch control end and the first clock output of the clock generation circuit; the control output end of the digital processing unit is respectively connected with the thirteenth switch control end, the fourteenth switch control end, the fifteenth switch control end, the sixteenth switch control end, the twentieth switch control end, the twenty-first switch control end, the twenty-second switch control end and the twenty-third switch control end.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921206228.0U CN210041777U (en) | 2019-07-29 | 2019-07-29 | Circuit structure with first-order filtering and circuit time constant calibration functions |
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| CN201921206228.0U CN210041777U (en) | 2019-07-29 | 2019-07-29 | Circuit structure with first-order filtering and circuit time constant calibration functions |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110266288A (en) * | 2019-07-29 | 2019-09-20 | 中国电子科技集团公司第五十四研究所 | A kind of circuit time constant auto-calibration circuits with first-order filtering effect |
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2019
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110266288A (en) * | 2019-07-29 | 2019-09-20 | 中国电子科技集团公司第五十四研究所 | A kind of circuit time constant auto-calibration circuits with first-order filtering effect |
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