CN210040201U - High-reliability wafer-level packaging structure of image sensor - Google Patents
High-reliability wafer-level packaging structure of image sensor Download PDFInfo
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- CN210040201U CN210040201U CN201921082388.9U CN201921082388U CN210040201U CN 210040201 U CN210040201 U CN 210040201U CN 201921082388 U CN201921082388 U CN 201921082388U CN 210040201 U CN210040201 U CN 210040201U
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Abstract
The utility model discloses a high reliability image sensor wafer level packaging structure belongs to integrated circuit encapsulation field. The high-reliability image sensor wafer-level packaging structure comprises an image sensor wafer and a glass carrier plate, wherein the glass carrier plate comprises a glass substrate, and the glass substrate is bonded with the image sensor wafer through a bonding layer; the back of the image sensor wafer is provided with a TSV through hole, and a first passivation layer, a second passivation layer, a metal circuit layer and a solder mask layer are sequentially formed in the back of the image sensor wafer and the TSV through hole. The utility model discloses a packaging technology is simple, and is with low costs, and encapsulation efficiency and yield are high, are fit for extensive volume production and use.
Description
Technical Field
The utility model relates to an integrated circuit packaging technology field, in particular to high reliability image sensor wafer level packaging structure.
Background
With the development of automatic driving and the internet of things, the application of the image sensor in the fields of vehicle-mounted, security and the like is more and more; these applications also typically have high reliability requirements due to safety concerns.
The conventional wafer level packaging technology for an image sensor with a cavity structure, as disclosed in patent CN105244359B, is increasingly unable to meet the reliability requirements of vehicle-mounted and security systems. In addition, in view of performance, the current wafer flow process level of the image device is continuously improved, the pixel points of a single chip are gradually increased, the photosensitive area occupies higher and higher proportion of the chip area, and therefore, sufficient space is not provided for manufacturing the cofferdam so as to form a cavity structure.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a high reliability image sensor wafer level packaging structure to improve the anti high temperature and high humidity's of packaging structure reliability ability, the bonding layering problem that appears easily in the solution reliability.
In order to solve the technical problem, the utility model provides a high reliability image sensor wafer level packaging structure, include:
an image sensor wafer;
the glass carrier plate comprises a glass substrate, and the glass substrate is bonded with the image sensor wafer through a bonding layer;
the back of the image sensor wafer is provided with a TSV through hole, and a first passivation layer, a second passivation layer, a metal circuit layer and a solder mask layer are sequentially formed in the back of the image sensor wafer and the TSV through hole.
Optionally, an opening is formed in the solder mask layer, and a bump or a printed solder ball is made in the opening.
Optionally, the TSV through hole is a second-order inclined hole with an angle of 50-70 degrees, and includes a first-order platform and a second-order platform.
Optionally, the first passivation layer covers the first stage mesa and remains 5-50 microns at the second stage mesa; the second passivation layer completely covers the plane of the second-stage platform.
Optionally, the thickness of the glass substrate is 50-500 μm, and both surfaces of the glass substrate are plated with anti-reflection layers.
Optionally, the thickness of the bonding layer is not less than 1 μm, and the light transmittance is not less than 99%.
Optionally, the metal circuit layer is manufactured by physical vapor deposition, electroplating and electroless plating.
Optionally, the solder mask layer is manufactured by a spin coating or screen printing glue process, and the thickness of the solder mask layer is not less than 1 μm.
Optionally, the image sensor wafer includes a silicon substrate, and an image sensor wafer functional layer, a metal pad layer and a microlens formed on the silicon substrate.
The utility model provides an among the high reliability image sensor wafer level packaging structure, include: the image sensor comprises an image sensor wafer and a glass carrier plate, wherein the glass carrier plate comprises a glass substrate, and the glass substrate is bonded with the image sensor wafer through a bonding layer; the back of the image sensor wafer is provided with a TSV through hole, and a first passivation layer, a second passivation layer, a metal circuit layer and a solder mask layer are sequentially formed in the back of the image sensor wafer and the TSV through hole.
The utility model discloses a high luminousness bonding layer forms no cavity packaging structure, strengthens the anti high temperature and high humidity reliability of encapsulation chip greatly, solves the bonding layering problem that appears in the reliability easily. Meanwhile, the first passivation layer and the second passivation layer are respectively formed through a two-step passivation method, so that the passivation glue volume of the packaging body can be reduced, and a protrusion is formed on the surface of the second-step platform of the TSV through hole, the thickness of the passivation layer on the surface of the chip is reduced, the thickness uniformity of the solder mask during spin coating is improved, and the cold and heat impact reliability resistance of the packaging body can be enhanced. The utility model discloses a packaging technology is simple, and is with low costs, and encapsulation efficiency and yield are high, are fit for extensive volume production and use.
Drawings
Fig. 1 is a schematic diagram of a wafer level package structure of a high reliability image sensor provided by the present invention;
FIG. 2 is a schematic structural diagram of a glass carrier;
FIG. 3 is a schematic view of an image sensor wafer;
FIG. 4 is a schematic view of a glass carrier and an image sensor wafer bonded together;
FIG. 5 is a schematic diagram of making TSV through holes and pre-cuts;
FIG. 6 is a schematic illustration of spraying a first passivation layer;
FIG. 7 is a schematic illustration of spraying a second passivation layer;
FIG. 8 is a schematic diagram of fabricating a metal wiring layer;
FIG. 9 is a schematic view of making a solder mask;
fig. 10 is an enlarged schematic view of a second level mesa in a TSV via.
Detailed Description
The present invention provides a high reliability image sensor wafer level package structure, which is described in detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
Example one
The utility model provides a high reliability image sensor wafer level packaging structure, its structure is shown in figure 1. The high-reliability image sensor wafer level packaging structure comprises an image sensor wafer and a glass carrier plate, wherein the image sensor wafer comprises a silicon substrate 105, and an image sensor wafer functional layer 107, a metal pad layer 108 and a micro lens 109 which are formed on the silicon substrate 105. The glass carrier comprises a glass substrate 302, and the glass substrate 302 is bonded with the image sensor wafer through a bonding layer 301. Preferably, the thickness of the glass substrate 302 is 50 to 500 μm, and both surfaces are plated with anti-reflection layers. The bonding layer 301 has a thickness of not less than 1 μm and a light transmittance of not less than 99%.
Furthermore, a TSV through hole is formed in the back surface of the image sensor wafer, and a first passivation layer 101, a second passivation layer 102, a metal circuit layer 103 and a solder resist layer 104 are sequentially formed in the back surface of the image sensor wafer and the TSV through hole; furthermore, the solder mask layer 104 has openings formed therein, and bumps or solder balls 106 are formed in the openings. The metal circuit layer 103 is manufactured by physical vapor deposition, electroplating and chemical plating; the solder mask layer 104 is manufactured by a spin coating or screen printing glue process, and the thickness of the solder mask layer is not less than 1 mu m.
Specifically, referring to fig. 1, the TSV through hole is a second-order inclined hole with an angle of 50 ° -70 °, and includes a first-order terrace 201 and a second-order terrace 202. The first passivation layer 101 covers the first stage platform 201 and remains 5-50 microns at the second stage platform 202; the second passivation layer 102 completely covers the plane of the second stage mesa 202.
Example two
The high-reliability wafer level packaging structure of the image sensor in the first embodiment is prepared by the following method:
specifically, a glass carrier and an image sensor wafer are provided. Specifically, the glass carrier is shown in fig. 2 and includes a glass substrate 302 and a bonding layer 301 spin-coated on the glass substrate 302; further, the thickness of the glass substrate 302 is 50-500 μm, and both surfaces are plated with anti-reflection layers; the bonding layer 301 is a high-light-transmittance bonding layer, the thickness of the bonding layer is not less than 1 μm, and the light transmittance is not less than 99%. As shown in fig. 3, the image sensor wafer includes a silicon substrate 105, and an image sensor wafer functional layer 107, a metal pad layer 108 and a microlens 109 formed on the silicon substrate 105. The glass carrier plate shown in fig. 2 is bonded to the image sensor wafer shown in fig. 3, as shown in fig. 4.
Thinning the back of the image sensor wafer, namely the silicon substrate 105 to a target thickness by grinding, dry etching and other methods; then, a TSV through hole 110 is formed by photolithography and dry etching, and the image sensor wafer functional layer 107 is scribed by laser to form a pre-cut groove 111, as shown in fig. 5. The manufactured TSV through hole 110 reaches the metal pad layer 108; the TSV 110 is preferably a second-order inclined hole with an angle of 50-70 degrees and comprises a first-order platform 201 and a second-order platform 202.
Referring to fig. 6 and 7, passivation is performed in two steps by spraying, the first passivation step forms a first passivation layer 101 covering the first step platform 201 and remains 5-50 μm at the second step platform 202, and the second passivation step forms a second passivation layer 102 completely covering the first step platform 201 and the second step platform 202.
Referring to fig. 8, the metal circuit layer 103 is formed by physical vapor deposition, electroplating and chemical plating to complete electrical connection, and then the solder resist layer 104 is formed by spin coating or screen printing, wherein the thickness of the solder resist layer is not less than 1um, as shown in fig. 9.
Finally, opening the solder mask layer 104, making bumps or printing solder balls 106 in the openings, and finally cutting to form single packaged chips capable of being interconnected with the outside, as shown in fig. 1.
The packaging method utilizes the high-light-transmittance bonding layer to form a cavity-free packaging structure, and the high-temperature and high-humidity resistance reliability of the packaged chip is greatly enhanced. Meanwhile, the passivation layer is formed through a two-step passivation method, so that the passivation glue volume of the packaging body can be reduced, a protrusion is formed on the surface of the second-step platform of the TSV through hole, the thickness of the passivation layer on the surface of the chip is reduced, the thickness uniformity of the solder mask layer during spin coating is improved, and the cold and heat impact resistance reliability of the packaging body can be enhanced as shown in FIG. 10. And finally, a laser grooving mode is used, so that the cracking and microcrack expansion of a chip functional layer low-k material caused by mechanical cutting are avoided, and the packaging reliability is enhanced.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.
Claims (9)
1. A wafer level package structure of a high reliability image sensor is characterized by comprising:
an image sensor wafer;
the glass carrier comprises a glass substrate (302), wherein the glass substrate (302) is bonded with the image sensor wafer through a bonding layer (301);
the back surface of the image sensor wafer is provided with a TSV through hole, and a first passivation layer (101), a second passivation layer (102), a metal circuit layer (103) and a solder mask layer (104) are sequentially formed in the back surface of the image sensor wafer and the TSV through hole.
2. The wafer level package structure of claim 1, wherein the solder mask layer (104) has an opening formed therein, and the opening has a bump or a printed solder ball (106) formed therein.
3. The wafer level package structure of claim 1, wherein the TSV is a second-order inclined hole with an angle of 50-70 degrees and comprises a first-order terrace (201) and a second-order terrace (202).
4. The high reliability image sensor wafer level package structure of claim 3, wherein the first passivation layer (101) covers the first level platform (201) and is retained at the second level platform (202) by 5-50 μm; the second passivation layer (102) completely covers the plane of the second stage mesa (202).
5. The wafer level package structure of claim 1, wherein the glass substrate (302) has a thickness of 50-500 μm and is coated with anti-reflection layers on both sides.
6. The wafer level package structure of claim 1, wherein the bonding layer (301) has a thickness not less than 1 μm and a light transmittance not less than 99%.
7. The wafer-level packaging structure of claim 1, wherein the metal circuit layer (103) is fabricated by physical vapor deposition, electroplating and electroless plating.
8. The wafer level package structure of claim 1, wherein the solder mask layer (104) is formed by spin coating or screen printing, and has a thickness not less than 1 μm.
9. The high reliability image sensor wafer level package structure of claim 1, wherein the image sensor wafer comprises a silicon substrate (105) and an image sensor wafer functional layer (107), a metal pad layer (108) and a micro lens (109) formed on the silicon substrate (105).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201921082388.9U CN210040201U (en) | 2019-07-11 | 2019-07-11 | High-reliability wafer-level packaging structure of image sensor |
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| CN201921082388.9U CN210040201U (en) | 2019-07-11 | 2019-07-11 | High-reliability wafer-level packaging structure of image sensor |
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| CN210040201U true CN210040201U (en) | 2020-02-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110246859A (en) * | 2019-07-11 | 2019-09-17 | 中国电子科技集团公司第五十八研究所 | A kind of high reliability image sensor wafer level packaging methods and structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110246859A (en) * | 2019-07-11 | 2019-09-17 | 中国电子科技集团公司第五十八研究所 | A kind of high reliability image sensor wafer level packaging methods and structure |
| CN110246859B (en) * | 2019-07-11 | 2024-04-09 | 中国电子科技集团公司第五十八研究所 | High-reliability image sensor wafer level packaging method and structure |
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