CN210007629U - AC-AC voltage regulating circuit - Google Patents
AC-AC voltage regulating circuit Download PDFInfo
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- CN210007629U CN210007629U CN201920638529.4U CN201920638529U CN210007629U CN 210007629 U CN210007629 U CN 210007629U CN 201920638529 U CN201920638529 U CN 201920638529U CN 210007629 U CN210007629 U CN 210007629U
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Abstract
The utility model provides an AC-AC voltage regulating circuit, including main topological circuit and drive control circuit, main topological circuit includes four MOS pipe charge and discharge circuits, the drive circuit of alternative work, MOS pipe Q3 and Q4 continuously conduct when the positive half cycle of alternating current waveform, when control Q1 is opened, Q2 closes, when Q1 and Q3 open, electric capacity, inductance discharge, lead to electric capacity other terminal voltage rising, charge for other inductance, electric capacity, make alternating current signal boost, when control Q2 and Q4 open, Q1 closes, side inductance, electric capacity discharge, lead to electric capacity to reduce, make other terminal voltage, inductance discharge, make alternating current signal step-down.
Description
Technical Field
The utility model relates to an electronic circuit field, in particular to kinds of AC-AC voltage regulating circuit.
Background
The power energy is the main energy in the modern times, various devices cannot be powered, the voltage required by the devices for working is different, the power voltage needs constant voltage boosting or voltage reduction, the current alternating current power voltage boosting and reducing is realized by a transformer and an inverter, but the transformer is large in size, the output is fixed and cannot be adjusted, the inverter is low in efficiency, and the high-efficiency selection is not available.
SUMMERY OF THE UTILITY MODEL
The utility model provides an kinds of AC-AC voltage regulating circuit has the characteristics that can reduce energy loss, improve voltage conversion efficiency.
According to the utility model provides an kinds of AC-AC voltage control circuit, including main topological circuit and drive control circuit;
the master topology circuit comprises four MOS tube charging and discharging circuits, namely a th MOS tube charging and discharging circuit, a second MOS tube charging and discharging circuit, a third MOS tube charging and discharging circuit and a fourth MOS tube charging and discharging circuit, wherein the th MOS tube charging and discharging circuit comprises a th N-channel MOS tube Q1, a grid electrode of a th N-channel MOS tube Q1 is connected with a th driving signal O1, the third MOS tube charging and discharging circuit comprises a third N-channel MOS tube Q3, a source electrode of the third N-channel MOS tube Q3 is connected with a source electrode of a th N-channel MOS tube Q1, a grid electrode of the third N-channel MOS tube Q3 is connected with a third driving signal O3, the second MOS tube charging and discharging circuit comprises a second N-channel MOS tube Q2, a grid electrode of the second N-channel MOS tube Q2, the fourth MOS tube charging and discharging circuit comprises a fourth N-channel MOS tube Q4, a source electrode of the fourth N-channel MOS tube Q4 is connected with a source electrode of the second N-channel MOS tube Q42, a fourth N-channel MOS tube Q5928 is connected with a twenty-channel MOS tube drain electrode of a twenty- , and a non-channel MOS tube drain electrode of a twenty-channel MOS tube Q-channel MOS tube;
the drain electrode of the N-channel MOS tube Q1 is connected with the end of an input alternating current power supply through a inductor L1, the drain electrode of the third N-channel MOS tube Q3 is connected with the other end of the input alternating current power supply, the drain electrode of the second N-channel MOS tube Q2 is connected with the end of an output alternating current power supply through a second inductor L2, and the drain electrode of the fourth N-channel MOS tube Q4 is connected with the other end of the output alternating current power supply;
the drive control circuit comprises an th drive control circuit and a second drive control circuit, the th drive control circuit comprises a th drive circuit and a third drive circuit which work simultaneously to output drive signals, the second drive control circuit comprises a second drive circuit and a fourth drive circuit which work simultaneously to output drive signals, the th drive control circuit and the second drive control circuit work alternately, the th drive circuit outputs a th drive signal O1, the second drive circuit outputs a second drive signal O2, the third drive circuit outputs a third drive signal O3, and the fourth drive circuit outputs a fourth drive signal O4.
An N-channel MOS tube charging and discharging circuit comprises an eighth diode D8, a twenty-third nonpolar capacitor C23 and a twenty-seventh resistor R27, wherein the twenty-third nonpolar capacitor C23 and the twenty-seventh resistor R27 are connected in series, the end of the circuit after the series connection is connected with the drain electrode of the N-channel MOS tube Q1, the other end of the circuit is connected with the source electrode of the N-channel MOS tube Q1, the positive electrode of the eighth diode D8 is connected with the source electrode of the N-channel MOS tube Q1, and the negative electrode of the eighth diode D8 is connected with the drain electrode of the N-channel MOS tube Q1.
The four MOS tube charging and discharging circuits are circuits with the same charging and discharging structure.
The th drive control circuit comprises a th comparator, a th drive control chip U1, a th drive circuit and a third drive circuit, wherein the second drive control circuit comprises a second comparator, a second drive control chip U2, a second drive circuit and a fourth drive circuit;
the in-phase input end of the comparator is connected with the input alternating voltage of the main topological circuit, and the anti-phase end of the comparator is connected with the adjustable direct voltage VCC;
the th driving control chip U1 inputs the adjustable square wave PWM and the output HO of the comparator, and outputs two paths of complementary signals of a th high level signal HO1 and a th low level signal LO1, and the second driving control chip U2 inputs the adjustable square wave PWM and the output LO of the second comparator, and outputs two paths of complementary signals of a second high level signal HO2 and a second low level signal LO 2;
the input end of the th driving circuit inputs a high level signal HO1 and outputs a th driving signal O1, the input end of the second driving circuit inputs a th low level signal LO1 and outputs a second driving signal O2, the input end of the third driving circuit inputs a second high level signal HO2 and outputs a third driving signal O3, and the input end of the fourth driving circuit inputs a second low level signal LO2 and outputs a fourth driving signal O4.
The adjustable square wave PWM generating circuit comprises a PWM wave generating chip, wherein the CT end of the PWM wave generating chip is connected to GND through a fifth point capacitor C5, the RT end of the PWM wave generating chip is connected to GND through a resistor R1, the non-inverting input end of the error amplifier is connected with a reference voltage, and the inverting input end of the error amplifier is connected with a tenth slide rheostat R10, so that the duty ratio of the PWM wave is adjustable.
fixed ends of the tenth sliding rheostat R10 are connected with a direct current voltage VCC through a ninth resistor R9, the other fixed ends are connected with GND, and the sliding ends are connected with the inverting input end of the error amplifier.
The main topology circuit further comprises a twenty-fourth resistor R24, a twenty-ninth resistor R29 and a thirty- resistor R31 which are connected in series, wherein a end of the twenty-fourth resistor R24 is connected with a end for outputting alternating current power, a thirty- resistor R31 is connected with another end for outputting alternating current power, a -th alternating current signal output interface is connected between the twenty-fourth resistor R24 and the twenty-ninth resistor R29, and a second alternating current signal output interface is connected between the twenty-ninth resistor R29 and the thirty- resistor R31;
the reference voltage reference circuit further comprises a feedback circuit, the feedback circuit comprises a rectifier D9, two input ends and FB1 of the rectifier D9 are connected with the th alternating current signal output end, another input ends FB2 are connected with the second alternating current signal output end, and the output end FBV of the rectifier outputs the reference voltage.
The adjustable dc voltage VCC is adjustable through a sliding varistor circuit.
The th driving circuit comprises a third driving control chip, which is connected to a th high level signal HO1 and controls to output a th driving signal O1.
VS5 between the N-channel MOS tube Q1 and the third N-channel MOS tube Q3 is respectively connected to the output stage working voltage VS1 of the th driving circuit and the output stage working voltage VS3 of the third driving circuit, and VS6 between the second N-channel MOS tube Q2 and the fourth N-channel MOS tube Q4 is respectively connected to the output stage working voltage VS2 of the second driving circuit and the output stage working voltage VS4 of the fourth driving circuit.
Compared with the prior art, the utility model discloses can be applied to the circuit and step up, step down, the direct conversion of alternating voltage is alternating voltage, and the middle loss of energy when having reduced alternating voltage conversion to make output voltage satisfy the voltage demand that equipment is different, efficient, small.
Drawings
Fig. 1 is a schematic diagram of a main topology circuit structure of an embodiment of the present invention.
Fig. 2 is a schematic diagram of the comparator circuit and the second comparator circuit according to an embodiment of the present invention at .
Fig. 3 is a schematic diagram of a peripheral circuit connection structure of a th driving control chip according to an embodiment of the present invention at .
Fig. 4 is a schematic diagram of a peripheral circuit connection structure of a second driving control chip according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a PWM generating circuit according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a driving circuit of an embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a second driving circuit according to an embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a third driving circuit according to an embodiment of the present invention.
Fig. 9 is a schematic structural diagram of a fourth driving circuit according to an embodiment of the present invention.
Fig. 10 is a schematic structural diagram of a feedback circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in detail below in with reference to the accompanying drawings and embodiments.
Any of the features disclosed in this specification (including the abstract and drawings) may be replaced by alternative features serving an equivalent or similar purpose, unless expressly stated otherwise, i.e. each feature is simply examples of a series of equivalent or similar features, unless expressly stated otherwise.
According to the utility model provides an kinds of AC-AC voltage control circuit, including main topological circuit and drive control circuit;
as shown in fig. 1, the master topology circuit comprises four MOS tube charging and discharging circuits, namely a MOS tube charging circuit, a second MOS tube charging and discharging circuit, a third MOS tube charging and discharging circuit and a fourth MOS tube charging and discharging circuit, wherein the MOS tube charging and discharging circuit comprises a N-channel MOS tube Q1, a gate of a N-channel MOS tube Q1 is connected with a -th driving signal O1, the third MOS tube charging and discharging circuit comprises a third N-channel MOS tube Q3, a source of the third N-channel MOS tube Q3 is connected with a source of a N-channel MOS tube Q1, and a gate of the third N-channel MOS tube Q3 is connected with a third driving signal O3, the second MOS tube charging and discharging circuit comprises a second N-channel MOS tube Q2, a gate of the second N-channel MOS tube Q3923, the fourth MOS tube charging and discharging circuit comprises a fourth N-channel MOS tube Q4, a source of the fourth N-channel MOS tube Q4 is connected with a second N-channel MOS tube Q2, a drain of a drain electrode of a twenty-channel MOS tube Q8628, and a drain electrode of a twenty-channel MOS tube Q21N-channel MOS tube Q8628;
the drain electrode of the N-channel MOS tube Q1 is connected with the end of an input alternating current power supply through a inductor L1, the drain electrode of the third N-channel MOS tube Q3 is connected with the other end of the input alternating current power supply, the drain electrode of the second N-channel MOS tube Q2 is connected with the end of an output alternating current power supply through a second inductor L2, and the drain electrode of the fourth N-channel MOS tube Q4 is connected with the other end of the output alternating current power supply;
the drive control circuit comprises an th drive control circuit and a second drive control circuit, the th drive control circuit comprises a th drive circuit and a third drive circuit which work simultaneously to output drive signals, the second drive control circuit comprises a second drive circuit and a fourth drive circuit which work simultaneously to output drive signals, the th drive control circuit and the second drive control circuit work alternately, the th drive circuit outputs a th drive signal O1, the second drive circuit outputs a second drive signal O2, the third drive circuit outputs a third drive signal O3, and the fourth drive circuit outputs a fourth drive signal O4.
Based on above-mentioned circuit structure, main topological circuit can produce the chopping function, and the alternating current can regard it as the sinusoidal alternating current that positive half cycle and negative half cycle constitute jointly, then carries out the chopping processing to the electric power waveform of positive negative cycle respectively, and the back is handled just like the buck-boost in the direct current electric power after the chopping to realize the adjustable function of input alternating voltage drive control circuit and second drive control circuit alternate work, thereby four MOS pipes in the drive main circuit structure of developing the utility model discloses can be applied to the circuit and step up, step down, the direct conversion of alternating voltage is alternating voltage, and the middle loss of energy when having reduced alternating voltage conversion to make output voltage satisfy the different voltage demand of equipment, efficient, small.
As the embodiments of the present invention, as shown IN fig. 1, the end of the input AC power supply is AC IN1, the other end of the input AC power supply is AC IN2, the end of the output AC power supply is AC OUT1, the other end of the output AC power supply is AC OUT2, a twenty-sixth-polarity capacitor C26 is connected between AC OUT1 and AC OUT2, the positive electrode of the twenty-sixth-polarity capacitor C26 is connected to AC OUT1, and the negative electrode of the twenty-sixth-polarity capacitor C26 is connected to AC OUT 2.
As the utility model discloses an embodiments, N channel MOS pipe charge-discharge circuit, including eighth diode D8, twenty-third nonpolar electric capacity C23 and twenty-seventh resistance R27, twenty-third nonpolar electric capacity C23 and twenty-seventh resistance R27 establish ties, and circuit end after establishing ties links to each other with the drain electrode of N channel MOS pipe Q1, and end links to each other with the source electrode of channel MOS pipe Q1, the positive pole of eighth diode D8 links to each other with the source electrode of channel MOS pipe Q1, and the negative pole links to each other with the drain electrode of channel MOS pipe Q1.
As the utility model discloses an embodiments, four MOS pipe charge-discharge circuit are the circuit of same charge-discharge structure.
As shown in FIG. 1, in the alternately working driving circuit, when the alternating current is in a positive half period, Q3 and Q4 are continuously conducted, when Q1 and Q3 are controlled to be opened, Q2 is closed, when Q1 and Q3 are opened, the capacitor and the inductor are discharged, the end voltage of the other of the capacitor is increased, other inductors and capacitors are charged, the alternating current signal is boosted, when Q2 and Q4 are controlled to be opened, Q1 is closed, the inductor and the capacitor on the side are discharged, the end voltage of the capacitor is reduced, other capacitors and inductors are discharged, and the alternating current signal is reduced.
The utility model discloses an kind of implementation ways, the drive control circuit includes th comparator, th drive control chip U1, th drive circuit and third drive circuit, the second drive control circuit includes second comparator, second drive control chip U2, second drive circuit and fourth drive circuit;
the in-phase input end of the comparator is connected with the input alternating voltage of the main topological circuit, and the anti-phase end of the comparator is connected with the adjustable direct voltage VCC;
the th driving control chip U1 inputs the adjustable square wave PWM and the output HO of the comparator, and outputs two paths of complementary signals of a th high level signal HO1 and a th low level signal LO1, and the second driving control chip U2 inputs the adjustable square wave PWM and the output LO of the second comparator, and outputs two paths of complementary signals of a second high level signal HO2 and a second low level signal LO 2;
the input end of the th driving circuit inputs a high level signal HO1 and outputs a th driving signal O1, the input end of the second driving circuit inputs a th low level signal LO1 and outputs a second driving signal O2, the input end of the third driving circuit inputs a second high level signal HO2 and outputs a third driving signal O3, and the input end of the fourth driving circuit inputs a second low level signal LO2 and outputs a fourth driving signal O4.
As the utility model discloses an kind of implementation modes, as shown IN FIG. 2, chip LM393 is adopted to the comparator and second comparator, realize the positive negative cycle judgement to the alternating current to the realization is to drive control chip U1 and the enabling end of second drive control chip U2, as shown IN FIG. 1, it has twenty third resistance R23 and thirty resistance R30 to establish ties between two ports of input alternating current, link to each other with 3 feet and 6 feet of chip LM393 respectively between twenty third resistance R23 and the thirty resistance R30, two comparator input signal IN1 and the input signal IN2 of chip LM393 insert the input alternating current voltage SGAC IN of main topology circuit respectively, realize the judgement to the positive negative cycle of alternating current.
As the embodiments of the present invention, as shown in FIG. 3, the driving control chip U1 employs a chip IR2104 whose 3 pins are connected to the output HO of the comparator, and 2 pins are connected to the adjustable square wave PWM outputted by the PWM wave generating circuit, 5 pins are connected to the low level signal LO1, and 7 pins are connected to the high level signal HO1, as shown in FIG. 4, the second driving control chip U2 employs a chip IR2104 whose 3 pins are connected to the output LO of the second comparator, and 2 pins are connected to the adjustable square wave PWM outputted by the PWM wave generating circuit, 5 pins are connected to the second low level signal LO2, and 7 pins are connected to the second high level signal HO 2.
The driving circuit comprises a th comparator circuit, a second comparator circuit, a main topological circuit and four driving control circuits, wherein the voltage of the inverting end of the comparator is controlled by a sliding rheostat, the input voltage of the main topological circuit is connected to the inverting end of the th comparator, so that the comparator circuit is controlled to output high level, the voltage of the inverting end of the comparator is controlled by the sliding rheostat, the input voltage of the main topological circuit is connected to the inverting end of the second comparator, so that the comparator circuit is controlled to output low level, high and low level signals and square waves with adjustable duty ratio generated by a PWM wave circuit are input into a driving control chip, so that complementary high and low levels are output, the two driving control circuits output four signals, namely two complementary waveforms which are respectively input to the input ends of the four driving circuits, so that the logic control chip works alternately, PWM waves with constant voltage difference of are output and are sent to the main topological circuit, so that MOS tubes work alternately, and meanwhile, the working.
As the utility model discloses an kind of implementation manners, adjustable square wave PWM's production circuit includes that the PWM ripples produces the chip, and the CT end is connected to GND through fifth point electric capacity C5, and the RT end is connected to GND through resistance R1, and error amplifier cophase input termination benchmark reference voltage, inverting input termination ten slide rheostat R10 realize that the duty cycle of PWM ripples is adjustable.
As shown in FIG. 5, as embodiments, a PWM generating circuit takes TL494 as a control core and matches with a peripheral circuit to generate PWWM wave (square wave) signals with controllable duty ratio, in the present embodiment, PWM waves are generated based on TL494 as a main control chip to drive a main topology structure to generate a chopping function, a driving circuit outputs four PWM wave signals to be input into different MOS tubes of the main topology structure, after the PWM wave signal voltage is compared with a reference signal voltage, the Q1 and the Q3 are controlled to be opened, the other MOS tubes are closed, when the Q1 and the Q3 are opened and the other two MOS tubes are closed, the capacitor and the inductor discharge to cause the voltage of the capacitor to rise, the terminal voltage is charged to the other inductor and capacitor to boost the alternating current signal, when the PWM signal voltage output by the driving circuit is compared with the reference signal voltage, the Q1 and the Q3 are controlled to be closed, the other MOS tubes are opened, the square wave and the capacitor at side discharges to cause the voltage of the terminal of the capacitor to fall, the capacitor discharges to cause the other capacitor and the capacitor to discharge, when the alternating current signal voltage is input into the topology structure, the capacitor discharges, and the capacitor discharges when the main topology structure discharges the main topology structure, the.
As the utility model discloses an kinds of implementation ways, as shown in FIG. 5, stiff ends of tenth slide rheostat R10 connect direct current voltage VCC through ninth resistance R9, another fixed termination GND, the slip termination the inverting input of error amplifier adjusting 10 th slide rheostat realizes that TL494 chip 7 th pin voltage is adjustable, and forms the comparator with 8 th pin reference voltage, outputs the PWM ripples that the duty cycle is adjustable.
The implementation modes of the present invention are that the main topology circuit further includes a twenty-fourth resistor R24, a twenty-ninth resistor R29 and a thirty- resistor R31 connected in series, the end of the twenty-fourth resistor R24 is connected to the end of the output ac power supply, and the thirty- resistor R31 is connected to the other end of the output ac power supply, the ac signal output interface is connected between the twenty-fourth resistor R24 and the twenty-ninth resistor R29, and the second ac signal output interface is connected between the twenty-ninth resistor R29 and the thirty- resistor R31;
the reference voltage reference circuit further comprises a feedback circuit, as shown in fig. 10, the feedback circuit comprises a rectifier D9, two input ends of the rectifier D9, FB1 is connected with the ac signal output end, another input ends FB2 is connected with the second ac signal output end, and the output end FBV of the rectifier outputs the reference voltage.
In this embodiment, the output end of the main topology performs ac sampling, and the sampling signal is output to the 8 th pin reference voltage of the main chip TL494 through the feedback circuit to implement the feedback network. The output end of the main topology circuit is divided to obtain an alternating current signal, the alternating current signal is input into the rectifier, and a stable direct current signal is obtained by utilizing the functions of rectification and filtering. Input to the non-inverting terminal of the error amplifier of the PWM wave generating circuit. The feedback circuit samples the output power signal and carries out rectification and filtering processing to convert the alternating current signal into a direct current signal, and the direct current signal is used as a feedback signal to be sent to the PWM generating circuit, so that hardware closed loop is realized, and the purpose of voltage stabilization is achieved.
As shown in fig. 2, the pin 2 of the chip LM393 is connected to the sliding end of the eighteenth sliding rheostat R18, the two fixed ends of the eighteenth sliding rheostat R18 are connected to GND, the other end is connected to the dc voltage VCC through the sixteenth resistor R16, the pin 5 of the chip LM393 is connected to the sliding end of the nineteenth sliding rheostat R19, the two fixed ends of the nineteenth sliding rheostat R19 are connected to GND, and the other end is connected to the dc voltage VCC through the seventeenth resistor R17.
As embodiments of the present invention, as shown in fig. 6, the driving circuit includes a third driving control chip, which uses a chip IR2117 to access a th high level signal HO1 to control and output a th driving signal O1., a 2 nd pin of the chip IR2117 is accessed to a th high level signal HO1, a 7 th pin outputs a th driving signal O1, and 4 th and 5 th pins are suspended.
As embodiments of the present invention, the th, second, third and fourth driving circuits have the same circuit configuration as shown in fig. 7 to 9.
As the embodiments of the present invention, as shown in FIG. 1 and FIG. 6 to FIG. 9, VS5 between the N-channel MOS transistor Q1 and the third N-channel MOS transistor Q3 is connected to the VS1 of the output stage of the th driving circuit and the VS3 of the output stage of the third driving circuit respectively, and VS6 between the second N-channel MOS transistor Q2 and the fourth N-channel MOS transistor Q4 is connected to the VS2 of the output stage of the second driving circuit and the VS4 of the output stage of the fourth driving circuit respectively.
VS1, VS2, VS3, VS4 provide high reference voltages for the control driving signals output by O1, O2, O3, O4. because the AC voltage in the AC circuit may be hundreds of volts, and the voltage of the driving signal is only 12 volts, which is not enough to open the MOS transistor, high reference voltages need to be provided to make the MOS transistor conduct.
Claims (10)
- A AC-AC voltage regulating circuit, which is characterized by comprising a main topological circuit and a driving control circuit;the master topology circuit comprises four MOS tube charging and discharging circuits, namely a th MOS tube charging and discharging circuit, a second MOS tube charging and discharging circuit, a third MOS tube charging and discharging circuit and a fourth MOS tube charging and discharging circuit, wherein the th MOS tube charging and discharging circuit comprises a th N-channel MOS tube Q1, a grid electrode of a th N-channel MOS tube Q1 is connected with a th driving signal O1, the third MOS tube charging and discharging circuit comprises a third N-channel MOS tube Q3, a source electrode of the third N-channel MOS tube Q3 is connected with a source electrode of a th N-channel MOS tube Q1, a grid electrode of the third N-channel MOS tube Q3 is connected with a third driving signal O3, the second MOS tube charging and discharging circuit comprises a second N-channel MOS tube Q2, a grid electrode of the second N-channel MOS tube Q2, the fourth MOS tube charging and discharging circuit comprises a fourth N-channel MOS tube Q4, a source electrode of the fourth N-channel MOS tube Q4 is connected with a source electrode of the second N-channel MOS tube Q42, a fourth N-channel MOS tube Q5928 is connected with a twenty-channel MOS tube drain electrode of a twenty- , and a non-channel MOS tube drain electrode of a twenty-channel MOS tube Q-channel MOS tube;the drain electrode of the N-channel MOS tube Q1 is connected with the end of an input alternating current power supply through a inductor L1, the drain electrode of the third N-channel MOS tube Q3 is connected with the other end of the input alternating current power supply, the drain electrode of the second N-channel MOS tube Q2 is connected with the end of an output alternating current power supply through a second inductor L2, and the drain electrode of the fourth N-channel MOS tube Q4 is connected with the other end of the output alternating current power supply;the drive control circuit comprises an th drive control circuit and a second drive control circuit, the th drive control circuit comprises a th drive circuit and a third drive circuit which work simultaneously to output drive signals, the second drive control circuit comprises a second drive circuit and a fourth drive circuit which work simultaneously to output drive signals, the th drive control circuit and the second drive control circuit work alternately, the th drive circuit outputs a th drive signal O1, the second drive circuit outputs a second drive signal O2, the third drive circuit outputs a third drive signal O3, and the fourth drive circuit outputs a fourth drive signal O4.
- 2. The AC-AC voltage regulation circuit of claim 1, wherein the N-channel MOS transistor charging and discharging circuit comprises an eighth diode D8, a twenty-third non-polar capacitor C23 and a twenty-seventh resistor R27, the twenty-third non-polar capacitor C23 and the twenty-seventh resistor R27 are connected in series, one end of the series circuit is connected with the drain of the N-channel MOS transistor Q1, the other end of the series circuit is connected with the source of the N-channel MOS transistor Q1, the anode of the eighth diode D8 is connected with the source of the N-channel MOS transistor Q1, and the cathode of the eighth diode D8 is connected with the drain of the N-channel MOS transistor Q1.
- 3. The AC-AC voltage regulating circuit according to claim 1 or 2, wherein the four MOS transistor charging and discharging circuits are circuits of the same charging and discharging structure.
- 4. The AC-AC voltage regulating circuit according to claim 1, wherein said driving control circuit comprises a th comparator, a th driving control chip U1, a th driving circuit and a third driving circuit, said second driving control circuit comprises a second comparator, a second driving control chip U2, a second driving circuit and a fourth driving circuit;the in-phase input end of the comparator is connected with the input alternating voltage of the main topological circuit, and the anti-phase end of the comparator is connected with the adjustable direct voltage VCC;the driving control chip U1 inputs the output HO of the adjustable square wave PWM and comparator and outputs two complementary signals HO1 and LO1 of high level signal and low level signal, the second driving control chip U2 inputs the adjustable square wave PWM and the output LO of the second comparator and outputs two complementary signals HO2 and LO2 of second high level signal, the input end of the driving circuit inputs the high level signal HO1 and outputs the driving signal O1, the input end of the second driving circuit inputs the low level signal LO1 and outputs the second driving signal O2, the input end of the third driving circuit inputs the second high level signal HO2 and outputs the third driving signal O3, and the input end of the fourth driving circuit inputs the second low level signal LO2 and outputs the fourth driving signal O4.
- 5. The AC-AC voltage regulation circuit of claim 4, wherein the generation circuit of the adjustable square wave PWM comprises a PWM wave generation chip, the CT terminal is connected to GND through a fifth point capacitor C5, the RT terminal is connected to GND through a resistor R1, the non-inverting input terminal of the error amplifier is connected with a reference voltage, and the inverting input terminal of the error amplifier is connected with a tenth slide rheostat R10, so that the duty ratio of the PWM wave is adjustable.
- 6. The AC-AC voltage regulating circuit according to claim 5, wherein fixed ends of a tenth sliding rheostat R10 are connected to the DC voltage VCC through a ninth resistor R9, another fixed ends are connected to GND, and the sliding ends are connected to the inverting input end of the error amplifier.
- 7. The AC-AC voltage regulation circuit of claim 5, wherein the main topology circuit further comprises a twenty-fourth resistor R24, a twenty-ninth resistor R29 and a thirty resistor R31 connected in series, wherein a terminal of the twenty-fourth resistor R24 is connected with an terminal of the output AC power supply, a thirty resistor R31 is connected with another terminal of the output AC power supply, a AC signal output interface is connected between the twenty-fourth resistor R24 and the twenty-ninth resistor R29, and a second AC signal output interface is connected between the twenty-ninth resistor R29 and the thirty resistor R31;the reference voltage reference circuit further comprises a feedback circuit, the feedback circuit comprises a rectifier D9, two input ends and FB1 of the rectifier D9 are connected with the th alternating current signal output end, another input ends FB2 are connected with the second alternating current signal output end, and the output end FBV of the rectifier outputs the reference voltage.
- 8. The AC-AC voltage regulation circuit of claim 4 wherein the adjustable DC voltage VCC is adjustable through a sliding rheostat circuit.
- 9. The AC-AC voltage regulating circuit according to claim 4, wherein said th driving circuit comprises a third driving control chip for receiving a th high level signal HO1 and controlling to output a th driving signal O1.
- 10. The AC-AC voltage regulation circuit of claim 4, wherein VS5 between the N-channel MOS transistor Q1 and the third N-channel MOS transistor Q3 is connected to the output stage operating voltage VS1 of the th driving circuit and the output stage operating voltage VS3 of the third driving circuit respectively, and VS6 between the second N-channel MOS transistor Q2 and the fourth N-channel MOS transistor Q4 is connected to the output stage operating voltage VS2 of the second driving circuit and the output stage operating voltage VS4 of the fourth driving circuit respectively.
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| CN201920638529.4U CN210007629U (en) | 2019-05-07 | 2019-05-07 | AC-AC voltage regulating circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110022073A (en) * | 2019-05-07 | 2019-07-16 | 成都信息工程大学 | A kind of AC-AC voltage regulator circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110022073A (en) * | 2019-05-07 | 2019-07-16 | 成都信息工程大学 | A kind of AC-AC voltage regulator circuit |
| CN110022073B (en) * | 2019-05-07 | 2024-01-30 | 成都信息工程大学 | AC-AC voltage regulating circuit |
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