CN209980780U - Low-power-consumption multi-channel audio coding and decoding chip - Google Patents
Low-power-consumption multi-channel audio coding and decoding chip Download PDFInfo
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Abstract
The embodiment of the utility model provides a low-power consumption multichannel audio coding decodes chip, include: the device comprises a 6-channel analog-to-digital converter, a digital filter, a 2-channel digital-to-analog converter and a digital audio interface; the output end of the 6-channel analog-to-digital converter ADC is connected with the input end of the digital filter, and the output end of the digital filter is respectively connected with the 2-channel digital-to-analog converter and the digital audio interface. The chip can realize the acquisition, coding and decoding of up to 6 channels of audio signals, and greatly reduces the complexity, cost and power consumption of the system compared with the mainstream A/D chip in the market which can only acquire two channels of signals.
Description
Technical Field
The utility model relates to a chip technical field especially relates to a low-power consumption multichannel audio coding decodes chip.
Background
With the development of speech recognition and dialog systems, intelligent speech interaction technology has attracted more and more attention. The voice interaction cannot be separated from the collection of audio signals, and the parallel collection of multi-channel signals is always the core technology in the field of signal processing, particularly based on arrays.
Array signal processing often needs to acquire a plurality of sensors at the same time so as to design a corresponding array signal processing algorithm by using phase difference information between each path of signals. In the design process of the acquisition system, the data channels are multiple, the data throughput is large, the data transmission rate is high, and the real-time requirement is high.
Parallel acquisition systems for multi-channel audio signals typically employ integrated a/D chips to accomplish the acquisition. However, the mainstream a/D chips in the market generally can only collect two channels of signals, and if more channels of audio signals need to be collected, multiple a/D chips must be cascaded, which not only increases the complexity of the system, but also increases the cost and power consumption of the system.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a overcome above-mentioned problem or solve above-mentioned problem's low-power consumption multichannel audio coding decoding chip at least partially.
The embodiment of the utility model provides a low-power consumption multichannel audio coding decodes chip, include: the device comprises a 6-channel analog-to-digital converter, a digital filter, a 2-channel digital-to-analog converter and a digital audio interface; the output end of the 6-channel analog-to-digital converter ADC is connected with the input end of the digital filter, and the output end of the digital filter is respectively connected with the 2-channel digital-to-analog converter and the digital audio interface.
Further, the input end of each channel analog-to-digital converter in the 6-channel analog-to-digital converter is connected with a first mute function circuit, and the first mute circuit is connected with the output end of the programmable gain amplifier.
Furthermore, the output end of each channel digital-to-analog converter in the 2-channel digital-to-analog converter is connected with a second mute function circuit.
Further, the analog-to-digital converter is a 24-bit Sigma-Delta type converter, operates at 128 times oversampling rate, has a sampling rate ranging from 8kHz to 96kHz, and includes a digital high-pass filter and a digital volume control circuit.
Further, the digital-to-analog converter is a 24-bit Sigma-Delta type converter, and works at 128 times of oversampling rate, and the sampling rate ranges from 8kHz to 96 kHz.
Furthermore, the system also comprises a crystal oscillator, a control interface and a successive approximation type analog-to-digital converter.
The embodiment of the utility model provides a pair of low-power consumption multichannel audio coding decodes chip, it includes: the device comprises a 6-channel analog-to-digital converter, a digital filter, a 2-channel digital-to-analog converter and a digital audio interface; the output end of the 6-channel analog-to-digital converter ADC is connected with the input end of the digital filter, and the output end of the digital filter is respectively connected with the 2-channel digital-to-analog converter and the digital audio interface. The chip can realize the acquisition, coding and decoding of up to 6 channels of audio signals, and greatly reduces the complexity, cost and power consumption of the system compared with the mainstream A/D chip in the market which can only acquire two channels of signals.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a low-power consumption multi-channel audio encoding and decoding chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Fig. 1 is a schematic circuit diagram of a low-power consumption multi-channel audio encoding and decoding chip provided by an embodiment of the present invention, as shown in fig. 1, including: the device comprises a 6-channel analog-to-digital converter, a digital filter, a 2-channel digital-to-analog converter and a digital audio interface; the output end of the 6-channel analog-to-digital converter ADC is connected with the input end of the digital filter, and the output end of the digital filter is respectively connected with the 2-channel digital-to-analog converter and the digital audio interface.
Specifically, when the chip is in operation, the input configuration can accept up to 6 single-ended analog signals or multiple forms of stereo differential, stereo single-ended signals. An input Audio signal is encoded and decoded by an analog-to-Digital converter (ADC), filtered by a Digital filter (Digital Filters), and then output from a Digital Audio Interface (Digital Audio Interface) or a Digital-to-analog converter (DAC).
The embodiment of the utility model provides a pair of low-power consumption multichannel audio coding decodes chip, it includes: the device comprises a 6-channel analog-to-digital converter, a digital filter, a 2-channel digital-to-analog converter and a digital audio interface; the output end of the 6-channel analog-to-digital converter ADC is connected with the input end of the digital filter, and the output end of the digital filter is respectively connected with the 2-channel digital-to-analog converter and the digital audio interface. The chip can realize the acquisition, coding and decoding of up to 6 channels of audio signals, and greatly reduces the complexity, cost and power consumption of the system compared with the mainstream A/D chip in the market which can only acquire two channels of signals.
In the above embodiment, referring again to fig. 1, the input terminal of each of the 6-channel analog-to-digital converters is connected to the first mute function circuit, and the first mute circuit is connected to the output terminal of the programmable gain amplifier.
Specifically, for each channel in the 6-channel analog-to-digital converter, besides one analog-to-digital converter, a first Mute function circuit (Mute) and a programmable gain amplifier (VOL) are provided, and the programmable gain amplifier is connected with the input end of the analog-to-digital converter in the channel through the first Mute function circuit.
Each path of input signals can be subjected to volume adjustment by using a programmable gain amplifier in each path, and a mute function can be realized by using a first mute function circuit in each path.
In the above embodiment, referring to fig. 1 again, the output end of each channel digital-to-analog converter in the 2-channel digital-to-analog converter is connected to the second mute function circuit.
Specifically, each channel in the 2-channel digital-to-analog converter can realize the mute function by using the second mute function circuit.
In the above embodiment the analog to digital converter is a 24 bit Sigma Delta type converter operating at 128 times oversampling rate, with a sampling rate in the range 8kHz to 96kHz, and includes a digital high pass filter and a digital volume control circuit.
In particular, the digital high-pass filter is a selectable high-pass filter, and the direct current offset can be eliminated by enabling or disabling the register.
In the above embodiment, the digital to analog converter is a 24 bit Sigma Delta type converter operating at 128 times the oversampling rate and having a sampling rate in the range of 8kHz to 96 kHz.
In the above embodiment, referring again to fig. 1, the chip further includes a crystal oscillator, a control interface, and a successive approximation type analog-to-digital converter.
In particular, a crystal Oscillator (OSC) circuit provides a local clock for the chip. The control interface (ControlInterface) realizes I2C communication with the main control chip. A successive approximation analog-to-digital converter (SAR ADC) is used for the chip wake-up function.
In addition, it should be noted that the audio codec chip has a built-in hardware Automatic Level Control (ALC) function. The ALC is used for continuously adjusting the PGA gain to keep the recording volume constant and not changing with the change of the input level. To achieve the best noise performance, ALC adjusts the gain using an analog PGA rather than a digital approach. This ensures that ADC noise is not amplified when the signal level is low. To ensure that high quality audio is obtained during gain changes, the ALC uses a very small gain step. One potential problem with ALC is that the PGA gain may become very large for small input signals. The side effect is that noise is amplified along with the target signal. To avoid this phenomenon, noise gate technology may be used. The noise gate will truncate the ADC output when the signal level is below a set threshold.
The audio coding and decoding chip can be opened or closed according to requirements, so that the power consumption is reduced. These sections include ADCs, DACs, and PLLs. Furthermore, the operating mode of certain functions can be configured by means of control registers: power saving, normal mode. When the chip is in the power saving mode, the chip can be awakened through a successive approximation analog-to-digital converter (SAR ADC).
The serial control bus of the audio coding and decoding chip supports I2C and SPI protocol. The serial audio bus can be programmed to I2S, left/right alignment, or TDM pattern. All standard integer multiple clock frequencies and fractional master clock frequencies can be flexibly generated from 8MHz to 27MHz by programming the PLL.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (6)
1. A low-power consumption multi-channel audio coding and decoding chip is characterized by comprising: the device comprises a 6-channel analog-to-digital converter, a digital filter, a 2-channel digital-to-analog converter and a digital audio interface; the output end of the 6-channel analog-to-digital converter ADC is connected with the input end of the digital filter, and the output end of the digital filter is respectively connected with the 2-channel digital-to-analog converter and the digital audio interface.
2. The low power consumption multi-channel audio coding and decoding chip of claim 1, wherein the input terminal of each of the 6-channel analog-to-digital converters is connected to a first mute function circuit, and the first mute circuit is connected to the output terminal of the programmable gain amplifier.
3. The low-power consumption multi-channel audio coding and decoding chip of claim 1, wherein the output terminal of each of the 2-channel digital-to-analog converters is connected to the second mute function circuit.
4. The low power consumption multi-channel audio codec chip of claim 1, wherein the analog-to-digital converter is a 24-bit Sigma-Delta type converter operating at 128 times oversampling rate, has a sampling rate in the range of 8kHz to 96kHz, and includes a digital high pass filter and a digital volume control circuit.
5. The low power consumption multi-channel audio codec chip of claim 1, wherein the dac is a 24-bit Sigma-Delta converter operating at 128 times oversampling rate and has a sampling rate in the range of 8kHz to 96 kHz.
6. The low-power consumption multi-channel audio coding and decoding chip of claim 1, further comprising a crystal oscillator, a control interface and a successive approximation type analog-to-digital converter.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111970514A (en) * | 2020-08-27 | 2020-11-20 | 深圳职业技术学院 | Military audio-video coding chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111970514A (en) * | 2020-08-27 | 2020-11-20 | 深圳职业技术学院 | Military audio-video coding chip |
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Effective date of registration: 20231020 Address after: 518000 706, Zhonghua science and technology building, Guangxia Road, shangmeilin, Futian District, Shenzhen, Guangdong Province Patentee after: Shenzhen Zhihua Technology Co.,Ltd. Address before: Room 801, 802, 807, and 808, Building 6, Guanggu International Headquarters, No. 62 Guanggu Avenue, Donghu New Technology Development Zone, Wuhan City, Hubei Province, 430074 Patentee before: WUHAN ESHINE-IC TECHNOLOGY Co.,Ltd. |