CN209961325U

CN209961325U - Overhead transmission line wind vibration detection system

Info

Publication number: CN209961325U
Application number: CN201920717869.6U
Authority: CN
Inventors: 王峥; 吴超; 庞振江; 李延; 杨文�; 李良
Original assignee: Beijing Smartchip Microelectronics Technology Co Ltd
Current assignee: Beijing Smartchip Microelectronics Technology Co Ltd
Priority date: 2019-05-17
Filing date: 2019-05-17
Publication date: 2020-01-17
Anticipated expiration: 2029-05-17

Abstract

The utility model discloses an overhead transmission line wind detection system that shakes, including light transceiver module, the signal acquisition module who links to each other with light transceiver module, the data processing module who links to each other with signal acquisition module to and the remote monitoring platform who communicates with data processing module. The optical transceiver module comprises a circulator connected with a sensing optical fiber on the overhead transmission line, a photoelectric detector and an erbium-doped optical fiber amplifier which are connected with the circulator, an amplifier connected with the photoelectric detector, a pulse modulator connected with the erbium-doped optical fiber amplifier, and a narrow linewidth laser connected with the pulse modulator; wherein, the amplifier and the narrow linewidth laser are both connected with the data processing module. Through the design, utilize the utility model discloses but wind vibration discernment and location to the circuit are sensitive, but real-time supervision transmission line's running state takes emergency measures, prevention occurence of failure in advance to improve electric power system's stability, reduce the maintenance cost, promote economic benefits.

Description

Overhead transmission line wind vibration detection system

Technical Field

The utility model belongs to the technical field of the power transmission technique and specifically relates to an overhead transmission line wind shakes detecting system is related to.

Background

With the continuous development of power systems and the continuous construction of smart power grids, the online monitoring technology of power systems is widely regarded. The transmission line under the complicated field environment is easily influenced by various natural disasters to cause safety accidents. Wind-borne vibration of a power transmission line is a long-term and accumulated process, the damage degree of the power transmission line cannot be measured by a direct observation method, and normal and safe operation of the line is seriously threatened, although the detection technology of the power transmission line of a power system is rapidly developed in recent years, and computer management is basically realized. However, most of the test data come from manual inspection, video monitoring, measurement of various electrical sensors and the like, and the traditional detection modes have the defects that only qualitative observation can be carried out, quantitative detection cannot be carried out, power supply maintenance is difficult, electromagnetic interference is easy to cause and the like. The utility model is based on a Phase Sensitive Optical Time domain reflectometer (Phase Sensitive Optical Time domain reflectometry,

) The principle of (2) improves the existing wind vibration detection mode.

The distributed optical fiber sensing technology simultaneously takes the optical fiber as a sensing element and a transmission medium, when light waves are transmitted in the optical fiber, backward Rayleigh scattering, Brillouin scattering and Raman scattering shown in figure 1 can be generated, wherein the backward Rayleigh scattering, Brillouin scattering and Raman scattering are generatedThe rayleigh scattering light has the same frequency as the incident light, the light intensity of the rayleigh scattering light is inversely proportional to the fourth power of the wavelength of the incident light, any point on the optical fiber is a sensing unit, when the optical cable is blown by wind to vibrate, the optical fiber can generate stress deformation, the refractive index of each part of the optical fiber is changed, and finally the phase of the light at the position is changed. The returned light intensity of the interfered Rayleigh backward scattering light changes due to the change of the phase, and the light intensity is analyzed and compared with the signal detected without vibration, so that the exact position of the vibration corresponding to the time of the light intensity change is finally found out, and the strain condition of each position along the line is obtained.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an overhead transmission line wind detection system that shakes mainly solves current power transmission line wind and shakes and detect the unstability, easily receives electromagnetic interference and leads to power transmission system stability low, the problem of power supply maintenance difficulty.

In order to achieve the above object, the utility model adopts the following technical scheme:

a wind vibration detection system for an overhead transmission line comprises an optical transceiver module, a signal acquisition module connected with the optical transceiver module, a data processing module connected with the signal acquisition module, and a remote monitoring platform in communication connection with the data processing module; the optical transceiver module comprises a circulator connected with a sensing optical fiber on the overhead transmission line, a photoelectric detector and an erbium-doped optical fiber amplifier which are connected with the circulator, an amplifier connected with the photoelectric detector, a pulse modulator connected with the erbium-doped optical fiber amplifier, and a narrow linewidth laser connected with the pulse modulator; wherein, amplifier and narrow linewidth laser all link to each other with signal acquisition module.

Furthermore, the signal acquisition module comprises an A/D analog-to-digital conversion module and an FPGA logic control module which are connected with each other; the FPGA logic control module is connected with the narrow linewidth laser and the data processing module, and the A/D analog-to-digital conversion module is connected with the amplifier.

Furthermore, the data processing module comprises an ARM processor with the model number of S3C2440 connected with the FPGA logic control module, an SDRAM random storage module, a FLASH storage module, an LCD control module, a network communication module, a communication interface module and a power supply module which are all connected with the ARM processor, and a GUI graphical user interface connected with the LCD control module, the SDRAM random storage module and the FLASH storage module; the network communication module is in communication connection with the remote monitoring platform.

Specifically, the a/D analog-to-digital conversion module includes an analog-to-digital conversion chip U1 with model number AD9233, and a peripheral control circuit connected to the analog-to-digital conversion chip U1; the peripheral control circuit comprises a capacitor C1 connected between a VIN + pin and a VIN-pin of an analog-to-digital conversion chip U1, a resistor R1 connected with the VIN + pin of the chip U1, an amplifier M1 with a negative power end connected with a resistor R1, a resistor R3 with one end connected with a negative power end of the amplifier M1 and the other end connected with an inverse input end U-of the amplifier M1, resistors R5 and R7 with one end connected with an inverse input end U-of the amplifier M1 after being connected in series and the other end grounded, a resistor R2 with one end connected with a positive power end of the amplifier M1 and the other end connected with a VIN-pin of the analog-to-digital conversion chip U1, a resistor R4 with one end connected with a positive power end of the amplifier M1 and the other end connected with an inverse input end U + of the amplifier M1, a resistor R6 with one end connected with an inverse input end U + of the amplifier M1 and the other end grounded, a capacitor C2 connected between a FB pin, a resistor R8 connected between an RBIAS pin and a SENSE pin of the analog-to-digital conversion chip U1, capacitors C3 and C4 connected with a VREF pin of the analog-to-digital conversion chip U1 at one end and a SENSE pin of the analog-to-digital conversion chip U1 at the other end after being connected in parallel, and a connecting terminal J1 connected with a SENSE pin, a PWDN pin, an SDIO/DCS pin, an OEB pin and a DRGND pin of the analog-to-digital conversion chip U1; one end of each of the resistors R5 and R7 is connected with a VIN-pin of an analog-to-digital conversion chip U1, an AVDD pin of the analog-to-digital conversion chip U1 is connected with 1.8V voltage, DRVDD pins, SCLK/DFS pins and CSB pins of the analog-to-digital conversion chip U1 are connected with 3.3V voltage, D0-D11 pins of the analog-to-digital conversion chip U1 are connected with an I/O interface of the FPGA logic control module through buses, and the rest interfaces of the analog-to-digital conversion chip U1 are connected with the FPGA logic control module.

Specifically, the network communication module comprises a singlechip drive network card chip U2 with the model DM9000, which is connected with the ARM processor through a bus, a control circuit connected with the singlechip drive network card chip U2, and a network interface chip U3 with the model HR901130A, which is connected with the control circuit; the control circuit comprises a resistor R10, a resistor R9, a resistor R11, a resistor C6, a capacitor C7 and a resistor C6867376, wherein one end of the resistor R10 is connected with an INT pin of the singlechip driving network card chip U2, one end of the resistor R9 is connected with a CS pin of the singlechip driving network card chip U2, the other end of the resistor R9 is connected with a 3.3V voltage, one end of the resistor R11 is connected with a BGRES pin of the singlechip driving network card chip U2, the other end of the resistor R11 is grounded, one end of the capacitor C5, C6, C7 and C8 are connected with a VDD pin of the singlechip driving network card chip U2 after being connected in parallel, one end of the capacitor C6327 is connected with a VDD pin of the singlechip driving network card chip U2, the other end of the capacitor C6866 is grounded, one end of the resistor R13 and the light emitting diode D2 are connected with an LED1 pin of the singlechip driving network card chip U2 and the other end of the LED 46, A capacitor C10, a capacitor C9 connected in parallel with the two ends of the serially connected crystal oscillator Y1 and the capacitor C10, capacitors C11, C12 and C13 which are connected in parallel and have one end connected with TXVDD and RXVDD pins of the singlechip-driven network card chip U2 and the other end connected with TXVVDD and RXVDD pins of the singlechip-driven network card chip U2 and are grounded, a capacitor C9 connected in parallel with the two ends of the serially connected crystal oscillator Y1 and the capacitor C10, resistors R13 and R14 which have one end connected with the TX-pin of the singlechip-driven network card chip U2 and have the other end connected with the TX + pin of the singlechip-driven network card chip U2, a capacitor C14 which has one end connected between the resistors R13 and R14 and the other end grounded, a resistor R15 and a capacitor C15 which have one end connected with the RX-pin of the singlechip-driven network card chip U2 and the other end connected with the RX + pin of the singlechip-driven network card chip U2, and have one end connected with the resistors R36, an inductor L1 with one end connected with the Shield pin and the GHS _ GND pin of the network interface chip U3 and the other end grounded, and a connecting terminal J2 connected with the Shield pin and the GHS _ GND pin of the network interface chip U3; the TXVDD pin of the single chip drive network card chip U2 is connected with the CTR and CTT pins of the network interface chip U3, and the TX-, TX +, RX-and RX + pins of the single chip drive network card chip U2 are correspondingly connected with the TD-, TD +, RD-and RD + pins of the network interface chip U3 respectively.

Compared with the prior art, the utility model discloses following beneficial effect has:

(1) the signal acquisition and data processing module of the utility model adopts the framework of the cooperative work of FPGA (EP4CE55) and ARM (S3C2440), wherein the FPGA, the high-speed ADC and the peripheral circuit combination thereof are taken as a slave machine, and mainly completes the control of the optical transceiver module, the acquisition of the sensing electric signal, the preprocessing and the data transmission; the ARM is used as a host, is mainly used for recognizing and decoding data transmitted by the slave machines in cooperation with peripheral circuits of the ARM, extracts wind vibration information from the data, and simultaneously achieves functions of slave machine control, man-machine interaction, network communication and the like.

(2) The utility model discloses a set up the circulator, utilize the transmission of electromagnetic wave in the circulator can only follow the folk prescription to the characteristics in the ring, the rayleigh scattered light turns into the signal of telecommunication by photoelectric detector after the circulator separation again, and this signal of telecommunication is through data processing after the AD sampling again to demodulation out optic fibre wind state and disturbance location everywhere along the line, make the more accuracy of location.

(3) The utility model discloses a set up erbium-doped fiber amplifier, utilize erbium-doped fiber amplifier directly to enlargie the light signal, combine sensing fiber's use, need not convert light signal into the signal of telecommunication, directly amplify the light signal, and, the operating wavelength's of erbium-doped fiber amplifier scope is unanimous with optic fibre minimum loss window, the pumping power that carries out the excitation to the erbium-doped fiber is low, only need dozens of mw, the gain is high, the noise is low, output is big, connection loss is low, because be optic fibre type amplifier, so it is relatively easy with fiber connection, connection loss can be as low as 0.1dB, can reduce circuit's whole consumption.

(4) The utility model discloses a very narrow laser instrument of line width is as the light source, because the light that the narrow line width laser instrument can make to pour into in the sensing optical fiber has very strong coherence, the light intensity that detects so is the coherent stack of all backward rayleigh scattered light intensity in the light pulse wide range, and the system just can survey more faint vibration signal like this.

(5) The utility model discloses utilize pulse modulation, based on the pulse modulation scheme of Semiconductor Optical Amplifier (SOA), SOA realizes the reversal of junction area population through plus forward bias, and the incident stimulated radiation that produces of signal light for signal light is enlargied, and wherein the extinction ratio of switch type SOA can reach more than 40dB, and easy operation realizes the pulse modulation of high rate, high extinction ratio.

Drawings

FIG. 1 is a diagram of Rayleigh scattering spectra in a background art optical fiber.

Fig. 2 shows an overall principle frame body of the present invention.

Fig. 3 is a schematic block diagram of the data processing module of the present invention.

Fig. 4 is a schematic circuit diagram of the a/D analog-to-digital conversion module of the present invention.

Fig. 5 is a schematic circuit diagram of the network communication module of the present invention.

Fig. 6 is a schematic layout diagram of an experimental apparatus in an embodiment of the present invention.

FIG. 7 is a time domain waveform diagram of the test result of suspension point A in the example.

FIG. 8 is a frequency domain waveform of the test result of suspension point A in the example.

FIG. 9 is a time domain waveform diagram of the test result of the suspension point C in the embodiment.

FIG. 10 is a frequency domain waveform of the test result of the suspension point C in the example.

FIG. 11 is a graph showing the positioning result of the vibration of the optical fiber in the example.

Detailed Description

The present invention will be further described with reference to the following description and examples, which include but are not limited to the following examples.

Examples

As shown in fig. 2 and 3, the utility model discloses an overhead transmission line wind shake detecting system, including light transceiver module, the signal acquisition module who links to each other with light transceiver module, the data processing module who links to each other with signal acquisition module to and the remote monitoring platform who communicates with data processing module.

The optical transceiver module comprises a circulator connected with a sensing optical fiber on the overhead transmission line, a photoelectric detector and an erbium-doped optical fiber amplifier which are connected with the circulator, an amplifier connected with the photoelectric detector, a pulse modulator connected with the erbium-doped optical fiber amplifier, and a narrow linewidth laser connected with the pulse modulator; wherein, the amplifier and the narrow linewidth laser are both connected with the data processing module. The signal acquisition module comprises an A/D analog-to-digital conversion module and an FPGA logic control module which are connected with each other; the FPGA logic control module is connected with the narrow linewidth laser and the data processing module, and the A/D analog-to-digital conversion module is connected with the amplifier. During measurement, a narrow line width (within a few kHz) is used as a light source, the light source is changed into pulse light under the action of a pulse modulator, and the pulse light is amplified by an erbium-doped fiber amplifier and then coupled into a sensing fiber by a circulator. During measurement, backward Rayleigh scattered light is converted into an electric signal by the photoelectric detector after being separated by the circulator, and the electric signal is subjected to data processing after being subjected to AD sampling, so that the wind vibration state and disturbance positioning of all positions along the optical fiber are demodulated.

The data processing module comprises an ARM processor with the model number of S3C2440, an SDRAM random storage module, a FLASH storage module, an LCD control module, a network communication module, a communication interface module and a power supply module which are connected with the ARM processor, and a GUI graphical user interface which is connected with the LCD control module, the SDRAM random storage module and the FLASH storage module; the network communication module is in communication connection with the remote monitoring platform.

The utility model discloses still integrated and simplified the connecting circuit of AD9233 with FPGA, as shown in fig. 4, AD analog-to-digital conversion module includes analog-to-digital conversion chip U1 that the model is AD9233 to and the peripheral control circuit who links to each other with analog-to-digital conversion chip U1; the peripheral control circuit comprises a capacitor C1 connected between a VIN + pin and a VIN-pin of an analog-to-digital conversion chip U1, a resistor R1 connected with the VIN + pin of the chip U1, an amplifier M1 with a negative power end connected with a resistor R1, a resistor R3 with one end connected with a negative power end of the amplifier M1 and the other end connected with an inverse input end U-of the amplifier M1, resistors R5 and R7 with one end connected with an inverse input end U-of the amplifier M1 after being connected in series and the other end grounded, a resistor R2 with one end connected with a positive power end of the amplifier M1 and the other end connected with a VIN-pin of the analog-to-digital conversion chip U1, a resistor R4 with one end connected with a positive power end of the amplifier M1 and the other end connected with an inverse input end U + of the amplifier M1, a resistor R6 with one end connected with an inverse input end U + of the amplifier M1 and the other end grounded, a capacitor C2 connected between a FB pin, a resistor R8 connected between an RBIAS pin and a SENSE pin of the analog-to-digital conversion chip U1, capacitors C3 and C4 connected with a VREF pin of the analog-to-digital conversion chip U1 at one end and a SENSE pin of the analog-to-digital conversion chip U1 at the other end after being connected in parallel, and a connecting terminal J1 connected with a SENSE pin, a PWDN pin, an SDIO/DCS pin, an OEB pin and a DRGND pin of the analog-to-digital conversion chip U1; one end of each of the resistors R5 and R7 is connected with a VIN-pin of an analog-to-digital conversion chip U1, an AVDD pin of the analog-to-digital conversion chip U1 is connected with 1.8V voltage, a DRVDD pin, an SCLK/DFS pin and a CSB pin of the analog-to-digital conversion chip U1 are connected with 3.3V voltage, D0-D11 pins of the analog-to-digital conversion chip U1 are connected with an I/O interface of the FPGA logic control module through buses, and the rest interfaces of the analog-to-digital conversion chip U1 are connected with the FPGA logic control module. The sampling clock of the AD9233 is obtained by the FPGA through phase-locked loop generation and frequency division, and is connected to a CLK + pin and a CLK-pin after conversion through a differential circuit. The power interface DRVDD can determine the signal level of the AD9233 parallel output data, and adjust to the VCCIO voltage compatible with the corresponding I/O BANK of the FPGA, so that the direct connection of the AD9233 and the I/O pin of the FPGA can be realized.

Since the S3C2440 chip is not provided with an integrated Ethernet MAC controller, the S3C2440 is realized by adopting the method shown in FIG. 5, and the network communication function is realized through the external bus connection DM 9000. The network communication module comprises a singlechip drive network card chip U2 with the model of DM9000, which is connected with the ARM processor through a bus, a control circuit connected with the singlechip drive network card chip U2, and a network interface chip U3 with the model of HR901130A, which is connected with the control circuit; the control circuit comprises a resistor R10, a resistor R9, a resistor R11, a resistor C6, a capacitor C7 and a resistor C6867376, wherein one end of the resistor R10 is connected with an INT pin of the singlechip driving network card chip U2, one end of the resistor R9 is connected with a CS pin of the singlechip driving network card chip U2, the other end of the resistor R9 is connected with a 3.3V voltage, one end of the resistor R11 is connected with a BGRES pin of the singlechip driving network card chip U2, the other end of the resistor R11 is grounded, one end of the capacitor C5, C6, C7 and C8 are connected with a VDD pin of the singlechip driving network card chip U2 after being connected in parallel, one end of the capacitor C6327 is connected with a VDD pin of the singlechip driving network card chip U2, the other end of the capacitor C6866 is grounded, one end of the resistor R13 and the light emitting diode D2 are connected with an LED1 pin of the singlechip driving network card chip U2 and the other end of the LED 46, A capacitor C10, a capacitor C9 connected in parallel with the two ends of the serially connected crystal oscillator Y1 and the capacitor C10, capacitors C11, C12 and C13 which are connected in parallel and have one end connected with TXVDD and RXVDD pins of the singlechip-driven network card chip U2 and the other end connected with TXVVDD and RXVDD pins of the singlechip-driven network card chip U2 and are grounded, a capacitor C9 connected in parallel with the two ends of the serially connected crystal oscillator Y1 and the capacitor C10, resistors R13 and R14 which have one end connected with the TX-pin of the singlechip-driven network card chip U2 and have the other end connected with the TX + pin of the singlechip-driven network card chip U2, a capacitor C14 which has one end connected between the resistors R13 and R14 and the other end grounded, a resistor R15 and a capacitor C15 which have one end connected with the RX-pin of the singlechip-driven network card chip U2 and the other end connected with the RX + pin of the singlechip-driven network card chip U2, and have one end connected with the resistors R36, an inductor L1 with one end connected with the Shield pin and the GHS _ GND pin of the network interface chip U3 and the other end grounded, and a connecting terminal J2 connected with the Shield pin and the GHS _ GND pin of the network interface chip U3; the TXVDD pin of the single chip drive network card chip U2 is connected with the CTR and CTT pins of the network interface chip U3, and the TX-, TX +, RX-and RX + pins of the single chip drive network card chip U2 are correspondingly connected with the TD-, TD +, RD-and RD + pins of the network interface chip U3 respectively. The DM9000 chip is a highly integrated low-power-consumption fast Ethernet chip and is provided with a general processor interface, an EEPROM interface and a 4K-dword SRAM cache data area (3K-byte Tx first-in first-out buffer; 13K-byte Rx first-in first-out buffer). When the system is powered on, the S3C2440 completes initialization of the DM9000 by configuring the DM9000 internal Network Control Register (NCR), the interrupt register (ISR), and the like through the bus, and then the DM9000 enters a data transceiving waiting state.

S3C2440 when sending data frame to Ethernet, pack the data into UDP or IP data packet first, and send to DM9000 data send buffer memory byte by byte through 8/16/32-bit bus, then fill information such as data length into DM9000 corresponding register, then send enable command, DM9000 MAC-framing the buffered data and data frame information, and send out; when the DM9000 receives ethernet data sent by an external network, it first detects the validity of the data frame, if the frame header flag has an error or there is a CRC error, discards the frame data, otherwise, buffers the data frame in the internal RAM, and notifies the processor through the interrupt flag bit, and the processor processes the data of the RAM received by the DM9000 after receiving the interrupt.

As shown in fig. 6, a detection test performed by the present invention adopts an OPPC-400 cable with a total length of 560m as an experimental object, and in order to simulate the running state of an actual overhead line, the cable is fixed at suspension points a and B of a fixing device by using pre-twisted wires, and the length of the cable between the two suspension points is 60 m; the actual wind vibration is simulated by applying the disturbance of different frequencies (0.5-1.5Hz) after the vibration exciter is connected with the cable (the connection point can move), and the vibration exciter is used

The system performs vibration measurement to judge the test result of the system. In the experiment, in order to comprehensively analyze the strain condition of the line, two optical fibers (single fiber with the length of 280m) in the cable are welded, so that the disturbance at the same position is measured secondarily in the experiment.

The vibration exciter is controlled to apply 1Hz disturbance to a position D220 m away from the starting end, a cable signal within 40s is tested, when external disturbance is applied to the cable, a plurality of vibration frequencies appear compared with the situation that the excitation signal is not applied, but the vibration amplitudes of the suspension points (A and B in the figure) and the disturbance position (D in the figure) are maximum, the frequency peaks of the suspension points and the disturbance position are nearly the same and are far higher than the rest positions, and the strain magnitude of the suspension points is far higher than that of the other cable positions, which is caused by severe strain due to stress concentration of the suspension points.

Fig. 7 shows the time domain waveform of the test result of suspension point a, with a time domain signal amplitude of about-2.5 × 105e at the maximum, and fig. 8 shows the frequency domain waveform of the test result of suspension point a, from which a peak of about-4.21 × 104 appears at a frequency of 1Hz, which is consistent with the frequency of the disturbance applied to the cable by the exciter.

The time domain signal and the frequency domain signal at the selected position C are shown in fig. 9 and 10. The time domain signal amplitude at position C is substantially identical to the suspension point a compared to the suspension point a signal. In the frequency domain, the point A and the point C have a larger difference, the signal intensity of the point A in the frequency domain shows a gradually decreasing trend, and the position C is basically equal.

Fig. 11 shows the positioning experiment result of the fiber vibration measurement, according to the testing environment and method shown in fig. 6, the waveform shows a symmetrical distribution, and the frequency peak of the disturbance point is the largest, and it is observed that the position D at 220m from the starting end is the disturbance application point.

The experimental analysis shows that when the optical fiber is disturbed at a certain frequency, the optical fiber strain changes at a plurality of frequencies, strong frequency peak values can appear near the positions of the suspension point and the disturbance point, the frequency is equal to the excitation frequency, the excitation frequency value can be conveniently given, and the disturbance strength at the position can be identified by analyzing the peak value. The above description may utilize a base

The distributed measurement system completes real-time measurement on the vibration and positioning of the OPPC cable.

The utility model discloses distributed optical fiber sensing monitoring system design based on "FPGA + ARM". The system has high sensitivity, high precision and electricity resistancePhase Sensitive optical time Domain Reflectometry (Phase Sensitive optical time Domain Reflectometry,

) The technology monitors the vibration state and fatigue degree of the line, uses narrow line width (within a few kHz) as a light source, changes the light into pulse light under the action of a pulse modulator, and couples the pulse light into a sensing optical fiber by a circulator after the pulse light is amplified by an erbium-doped optical fiber amplifier. During measurement, backward Rayleigh scattered light is converted into an electric signal by the photoelectric detector after being separated by the circulator, and the electric signal is subjected to data processing after being subjected to AD sampling, so that the wind vibration state and disturbance positioning of all positions along the optical fiber are demodulated. The whole system has powerful functions, works stably and reliably, and simultaneously supports further expansion and secondary development. Experimental test results show that the system is sensitive to wind vibration identification and positioning of the line, the running state of the power transmission line can be monitored in real time, emergency measures are taken in advance, accidents are prevented, and therefore the stability of the power system is improved, maintenance cost is reduced, and economic benefits are improved. Therefore, the method has high use value and popularization value.

The above embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the protection scope of the present invention, but all the insubstantial changes or modifications made in the spirit and the idea of the main design of the present invention, the technical problems solved by the embodiment are still consistent with the present invention, and all should be included in the protection scope of the present invention.

Claims

1. The wind vibration detection system of the overhead transmission line is characterized by comprising an optical transceiver module, a signal acquisition module connected with the optical transceiver module, a data processing module connected with the signal acquisition module and a remote monitoring platform in communication connection with the data processing module;

the optical transceiver module comprises a circulator connected with a sensing optical fiber on the overhead transmission line, a photoelectric detector and an erbium-doped optical fiber amplifier which are connected with the circulator, an amplifier connected with the photoelectric detector, a pulse modulator connected with the erbium-doped optical fiber amplifier, and a narrow linewidth laser connected with the pulse modulator; wherein, the amplifier and the narrow linewidth laser are both connected with the data processing module.

2. The overhead transmission line wind vibration detection system of claim 1, wherein the signal acquisition module comprises an a/D analog-to-digital conversion module and an FPGA logic control module which are connected with each other; the FPGA logic control module is connected with the narrow linewidth laser and the data processing module, and the A/D analog-to-digital conversion module is connected with the amplifier.

3. The system of claim 2, wherein the data processing module comprises an ARM processor of type S3C2440 connected to the FPGA logic control module, an SDRAM random access memory module, a FLASH memory module, an LCD control module, a network communication module, a communication interface module and a power supply module all connected to the ARM processor, and a GUI graphical user interface connected to the LCD control module, the SDRAM random access memory module and the FLASH memory module; the network communication module is in communication connection with the remote monitoring platform.

4. The system for detecting wind vibration of an overhead transmission line according to claim 3, wherein the A/D analog-to-digital conversion module comprises an analog-to-digital conversion chip U1 with the model number of AD9233 and a peripheral control circuit connected with the analog-to-digital conversion chip U1; the peripheral control circuit comprises a capacitor C1 connected between a VIN + pin and a VIN-pin of an analog-to-digital conversion chip U1, a resistor R1 connected with the VIN + pin of the chip U1, an amplifier M1 with a negative power end connected with a resistor R1, a resistor R3 with one end connected with a negative power end of the amplifier M1 and the other end connected with an inverse input end U-of the amplifier M1, resistors R5 and R7 with one end connected with an inverse input end U-of the amplifier M1 after being connected in series and the other end grounded, a resistor R2 with one end connected with a positive power end of the amplifier M1 and the other end connected with a VIN-pin of the analog-to-digital conversion chip U1, a resistor R4 with one end connected with a positive power end of the amplifier M1 and the other end connected with an inverse input end U + of the amplifier M1, a resistor R6 with one end connected with an inverse input end U + of the amplifier M1 and the other end grounded, a capacitor C2 connected between a FB pin, a resistor R8 connected between an RBIAS pin and a SENSE pin of the analog-to-digital conversion chip U1, capacitors C3 and C4 connected with a VREF pin of the analog-to-digital conversion chip U1 at one end and a SENSE pin of the analog-to-digital conversion chip U1 at the other end after being connected in parallel, and a connecting terminal J1 connected with a SENSE pin, a PWDN pin, an SDIO/DCS pin, an OEB pin and a DRGND pin of the analog-to-digital conversion chip U1; one end of each of the resistors R5 and R7 is connected with a VIN-pin of an analog-to-digital conversion chip U1, an AVDD pin of the analog-to-digital conversion chip U1 is connected with 1.8V voltage, a DRVDD pin, an SCLK/DFS pin and a CSB pin of the analog-to-digital conversion chip U1 are connected with 3.3V voltage, D0-D11 pins of the analog-to-digital conversion chip U1 are connected with an I/O interface of the FPGA logic control module through buses, and the rest interfaces of the analog-to-digital conversion chip U1 are connected with the FPGA logic control module.

5. The system for detecting wind vibration of an overhead transmission line according to claim 4, wherein the network communication module comprises a single-chip microcomputer driving network card chip U2 with the model DM9000, which is connected with the ARM processor through a bus, a control circuit connected with the single-chip microcomputer driving network card chip U2, and a network interface chip U3 with the model HR901130A, which is connected with the control circuit; the control circuit comprises a resistor R10, a resistor R9, a resistor R11, a resistor C6, a capacitor C7 and a resistor C6867376, wherein one end of the resistor R10 is connected with an INT pin of the singlechip driving network card chip U2, one end of the resistor R9 is connected with a CS pin of the singlechip driving network card chip U2, the other end of the resistor R9 is connected with a 3.3V voltage, one end of the resistor R11 is connected with a BGRES pin of the singlechip driving network card chip U2, the other end of the resistor R11 is grounded, one end of the capacitor C5, C6, C7 and C8 are connected with a VDD pin of the singlechip driving network card chip U2 after being connected in parallel, one end of the capacitor C6327 is connected with a VDD pin of the singlechip driving network card chip U2, the other end of the capacitor C6866 is grounded, one end of the resistor R13 and the light emitting diode D2 are connected with an LED1 pin of the singlechip driving network card chip U2 and the other end of the LED 46, A capacitor C10, a capacitor C9 connected in parallel with the two ends of the serially connected crystal oscillator Y1 and the capacitor C10, capacitors C11, C12 and C13 which are connected in parallel and have one end connected with TXVDD and RXVDD pins of the singlechip-driven network card chip U2 and the other end connected with TXVVDD and RXVDD pins of the singlechip-driven network card chip U2 and are grounded, a capacitor C9 connected in parallel with the two ends of the serially connected crystal oscillator Y1 and the capacitor C10, resistors R13 and R14 which have one end connected with the TX-pin of the singlechip-driven network card chip U2 and have the other end connected with the TX + pin of the singlechip-driven network card chip U2, a capacitor C14 which has one end connected between the resistors R13 and R14 and the other end grounded, a resistor R15 and a capacitor C15 which have one end connected with the RX-pin of the singlechip-driven network card chip U2 and the other end connected with the RX + pin of the singlechip-driven network card chip U2, and have one end connected with the resistors R36, an inductor L1 with one end connected with the Shield pin and the GHS _ GND pin of the network interface chip U3 and the other end grounded, and a connecting terminal J2 connected with the Shield pin and the GHS _ GND pin of the network interface chip U3; the TXVDD pin of the single chip drive network card chip U2 is connected with the CTR and CTT pins of the network interface chip U3, and the TX-, TX +, RX-and RX + pins of the single chip drive network card chip U2 are correspondingly connected with the TD-, TD +, RD-and RD + pins of the network interface chip U3 respectively.